171 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zve64x,+experimental-zvqdotq \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+experimental-zvqdotq \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i32> @intrinsic_vqdotus_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vqdotus_vx_nxv1i32_i32:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma11; CHECK-NEXT: vqdotus.vx v8, v9, a012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.nxv1i32.i32(15 <vscale x 1 x i32> %0,16 <vscale x 4 x i8> %1,17 i32 %2,18 iXLen %3, iXLen 0)19 20 ret <vscale x 1 x i32> %a21}22 23define <vscale x 2 x i32> @intrinsic_vqdotus_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vqdotus_vx_nxv2i32_i32:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma27; CHECK-NEXT: vqdotus.vx v8, v9, a028; CHECK-NEXT: ret29entry:30 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.nxv2i32.i32(31 <vscale x 2 x i32> %0,32 <vscale x 8 x i8> %1,33 i32 %2,34 iXLen %3, iXLen 0)35 36 ret <vscale x 2 x i32> %a37}38 39define <vscale x 4 x i32> @intrinsic_vqdotus_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, iXLen %3) nounwind {40; CHECK-LABEL: intrinsic_vqdotus_vx_nxv4i32_i32:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, ma43; CHECK-NEXT: vqdotus.vx v8, v10, a044; CHECK-NEXT: ret45entry:46 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.nxv4i32.i32(47 <vscale x 4 x i32> %0,48 <vscale x 16 x i8> %1,49 i32 %2,50 iXLen %3, iXLen 0)51 52 ret <vscale x 4 x i32> %a53}54 55define <vscale x 8 x i32> @intrinsic_vqdotus_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vqdotus_vx_nxv8i32_i32:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, ma59; CHECK-NEXT: vqdotus.vx v8, v12, a060; CHECK-NEXT: ret61entry:62 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.nxv8i32.i32(63 <vscale x 8 x i32> %0,64 <vscale x 32 x i8> %1,65 i32 %2,66 iXLen %3, iXLen 0)67 68 ret <vscale x 8 x i32> %a69}70 71define <vscale x 16 x i32> @intrinsic_vqdotus_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, iXLen %3) nounwind {72; CHECK-LABEL: intrinsic_vqdotus_vx_nxv16i32_i32:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma75; CHECK-NEXT: vqdotus.vx v8, v16, a076; CHECK-NEXT: ret77entry:78 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.nxv16i32.i32(79 <vscale x 16 x i32> %0,80 <vscale x 64 x i8> %1,81 i32 %2,82 iXLen %3, iXLen 0)83 84 ret <vscale x 16 x i32> %a85}86 87define <vscale x 1 x i32> @intrinsic_vqdotus_mask_vx_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 4 x i8> %1, i32 %2, <vscale x 1 x i1> %m, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv1i32_i32:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, mu91; CHECK-NEXT: vqdotus.vx v8, v9, a0, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 1 x i32> @llvm.riscv.vqdotus.mask.nxv1i32.i32(95 <vscale x 1 x i32> %0,96 <vscale x 4 x i8> %1,97 i32 %2,98 <vscale x 1 x i1> %m,99 iXLen %3, iXLen 0)100 101 ret <vscale x 1 x i32> %a102}103 104define <vscale x 2 x i32> @intrinsic_vqdotus_mask_vx_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 8 x i8> %1, i32 %2, <vscale x 2 x i1> %m, iXLen %3) nounwind {105; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv2i32_i32:106; CHECK: # %bb.0: # %entry107; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, mu108; CHECK-NEXT: vqdotus.vx v8, v9, a0, v0.t109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 2 x i32> @llvm.riscv.vqdotus.mask.nxv2i32.i32(112 <vscale x 2 x i32> %0,113 <vscale x 8 x i8> %1,114 i32 %2,115 <vscale x 2 x i1> %m,116 iXLen %3, iXLen 0)117 118 ret <vscale x 2 x i32> %a119}120 121define <vscale x 4 x i32> @intrinsic_vqdotus_mask_vx_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 16 x i8> %1, i32 %2, <vscale x 4 x i1> %m, iXLen %3) nounwind {122; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv4i32_i32:123; CHECK: # %bb.0: # %entry124; CHECK-NEXT: vsetvli zero, a1, e32, m2, tu, mu125; CHECK-NEXT: vqdotus.vx v8, v10, a0, v0.t126; CHECK-NEXT: ret127entry:128 %a = call <vscale x 4 x i32> @llvm.riscv.vqdotus.mask.nxv4i32.i32(129 <vscale x 4 x i32> %0,130 <vscale x 16 x i8> %1,131 i32 %2,132 <vscale x 4 x i1> %m,133 iXLen %3, iXLen 0)134 135 ret <vscale x 4 x i32> %a136}137 138define <vscale x 8 x i32> @intrinsic_vqdotus_mask_vx_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 32 x i8> %1, i32 %2, <vscale x 8 x i1> %m, iXLen %3) nounwind {139; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv8i32_i32:140; CHECK: # %bb.0: # %entry141; CHECK-NEXT: vsetvli zero, a1, e32, m4, tu, mu142; CHECK-NEXT: vqdotus.vx v8, v12, a0, v0.t143; CHECK-NEXT: ret144entry:145 %a = call <vscale x 8 x i32> @llvm.riscv.vqdotus.mask.nxv8i32.i32(146 <vscale x 8 x i32> %0,147 <vscale x 32 x i8> %1,148 i32 %2,149 <vscale x 8 x i1> %m,150 iXLen %3, iXLen 0)151 152 ret <vscale x 8 x i32> %a153}154 155define <vscale x 16 x i32> @intrinsic_vqdotus_mask_vx_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 64 x i8> %1, i32 %2, <vscale x 16 x i1> %m, iXLen %3) nounwind {156; CHECK-LABEL: intrinsic_vqdotus_mask_vx_nxv16i32_i32:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, mu159; CHECK-NEXT: vqdotus.vx v8, v16, a0, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i32> @llvm.riscv.vqdotus.mask.nxv16i32.i32(163 <vscale x 16 x i32> %0,164 <vscale x 64 x i8> %1,165 i32 %2,166 <vscale x 16 x i1> %m,167 iXLen %3, iXLen 0)168 169 ret <vscale x 16 x i32> %a170}171