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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma11; CHECK-NEXT: vredmax.vs v8, v9, v1012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(15 <vscale x 8 x i8> %0,16 <vscale x 1 x i8> %1,17 <vscale x 8 x i8> %2,18 iXLen %3)19 20 ret <vscale x 8 x i8> %a21}22 23define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma27; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(31 <vscale x 8 x i8> %0,32 <vscale x 1 x i8> %1,33 <vscale x 8 x i8> %2,34 <vscale x 1 x i1> %3,35 iXLen %4)36 37 ret <vscale x 8 x i8> %a38}39 40define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {41; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma44; CHECK-NEXT: vredmax.vs v8, v9, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(48 <vscale x 8 x i8> %0,49 <vscale x 2 x i8> %1,50 <vscale x 8 x i8> %2,51 iXLen %3)52 53 ret <vscale x 8 x i8> %a54}55 56define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma60; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(64 <vscale x 8 x i8> %0,65 <vscale x 2 x i8> %1,66 <vscale x 8 x i8> %2,67 <vscale x 2 x i1> %3,68 iXLen %4)69 70 ret <vscale x 8 x i8> %a71}72 73define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {74; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma77; CHECK-NEXT: vredmax.vs v8, v9, v1078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(81 <vscale x 8 x i8> %0,82 <vscale x 4 x i8> %1,83 <vscale x 8 x i8> %2,84 iXLen %3)85 86 ret <vscale x 8 x i8> %a87}88 89define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma93; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(97 <vscale x 8 x i8> %0,98 <vscale x 4 x i8> %1,99 <vscale x 8 x i8> %2,100 <vscale x 4 x i1> %3,101 iXLen %4)102 103 ret <vscale x 8 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {107; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma110; CHECK-NEXT: vredmax.vs v8, v9, v10111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(114 <vscale x 8 x i8> %0,115 <vscale x 8 x i8> %1,116 <vscale x 8 x i8> %2,117 iXLen %3)118 119 ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma126; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(130 <vscale x 8 x i8> %0,131 <vscale x 8 x i8> %1,132 <vscale x 8 x i8> %2,133 <vscale x 8 x i1> %3,134 iXLen %4)135 136 ret <vscale x 8 x i8> %a137}138 139define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {140; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma143; CHECK-NEXT: vredmax.vs v8, v10, v9144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(147 <vscale x 8 x i8> %0,148 <vscale x 16 x i8> %1,149 <vscale x 8 x i8> %2,150 iXLen %3)151 152 ret <vscale x 8 x i8> %a153}154 155define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, ma159; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(163 <vscale x 8 x i8> %0,164 <vscale x 16 x i8> %1,165 <vscale x 8 x i8> %2,166 <vscale x 16 x i1> %3,167 iXLen %4)168 169 ret <vscale x 8 x i8> %a170}171 172define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {173; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma176; CHECK-NEXT: vredmax.vs v8, v12, v9177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(180 <vscale x 8 x i8> %0,181 <vscale x 32 x i8> %1,182 <vscale x 8 x i8> %2,183 iXLen %3)184 185 ret <vscale x 8 x i8> %a186}187 188define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma192; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(196 <vscale x 8 x i8> %0,197 <vscale x 32 x i8> %1,198 <vscale x 8 x i8> %2,199 <vscale x 32 x i1> %3,200 iXLen %4)201 202 ret <vscale x 8 x i8> %a203}204 205define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {206; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma209; CHECK-NEXT: vredmax.vs v8, v9, v10210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(213 <vscale x 4 x i16> %0,214 <vscale x 1 x i16> %1,215 <vscale x 4 x i16> %2,216 iXLen %3)217 218 ret <vscale x 4 x i16> %a219}220 221define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma225; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(229 <vscale x 4 x i16> %0,230 <vscale x 1 x i16> %1,231 <vscale x 4 x i16> %2,232 <vscale x 1 x i1> %3,233 iXLen %4)234 235 ret <vscale x 4 x i16> %a236}237 238define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {239; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma242; CHECK-NEXT: vredmax.vs v8, v9, v10243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(246 <vscale x 4 x i16> %0,247 <vscale x 2 x i16> %1,248 <vscale x 4 x i16> %2,249 iXLen %3)250 251 ret <vscale x 4 x i16> %a252}253 254define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma258; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(262 <vscale x 4 x i16> %0,263 <vscale x 2 x i16> %1,264 <vscale x 4 x i16> %2,265 <vscale x 2 x i1> %3,266 iXLen %4)267 268 ret <vscale x 4 x i16> %a269}270 271define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {272; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma275; CHECK-NEXT: vredmax.vs v8, v9, v10276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(279 <vscale x 4 x i16> %0,280 <vscale x 4 x i16> %1,281 <vscale x 4 x i16> %2,282 iXLen %3)283 284 ret <vscale x 4 x i16> %a285}286 287define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma291; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(295 <vscale x 4 x i16> %0,296 <vscale x 4 x i16> %1,297 <vscale x 4 x i16> %2,298 <vscale x 4 x i1> %3,299 iXLen %4)300 301 ret <vscale x 4 x i16> %a302}303 304define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {305; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma308; CHECK-NEXT: vredmax.vs v8, v10, v9309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(312 <vscale x 4 x i16> %0,313 <vscale x 8 x i16> %1,314 <vscale x 4 x i16> %2,315 iXLen %3)316 317 ret <vscale x 4 x i16> %a318}319 320define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma324; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(328 <vscale x 4 x i16> %0,329 <vscale x 8 x i16> %1,330 <vscale x 4 x i16> %2,331 <vscale x 8 x i1> %3,332 iXLen %4)333 334 ret <vscale x 4 x i16> %a335}336 337define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {338; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma341; CHECK-NEXT: vredmax.vs v8, v12, v9342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(345 <vscale x 4 x i16> %0,346 <vscale x 16 x i16> %1,347 <vscale x 4 x i16> %2,348 iXLen %3)349 350 ret <vscale x 4 x i16> %a351}352 353define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma357; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(361 <vscale x 4 x i16> %0,362 <vscale x 16 x i16> %1,363 <vscale x 4 x i16> %2,364 <vscale x 16 x i1> %3,365 iXLen %4)366 367 ret <vscale x 4 x i16> %a368}369 370define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {371; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma374; CHECK-NEXT: vredmax.vs v8, v16, v9375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(378 <vscale x 4 x i16> %0,379 <vscale x 32 x i16> %1,380 <vscale x 4 x i16> %2,381 iXLen %3)382 383 ret <vscale x 4 x i16> %a384}385 386define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma390; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(394 <vscale x 4 x i16> %0,395 <vscale x 32 x i16> %1,396 <vscale x 4 x i16> %2,397 <vscale x 32 x i1> %3,398 iXLen %4)399 400 ret <vscale x 4 x i16> %a401}402 403define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {404; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma407; CHECK-NEXT: vredmax.vs v8, v9, v10408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(411 <vscale x 2 x i32> %0,412 <vscale x 1 x i32> %1,413 <vscale x 2 x i32> %2,414 iXLen %3)415 416 ret <vscale x 2 x i32> %a417}418 419define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma423; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(427 <vscale x 2 x i32> %0,428 <vscale x 1 x i32> %1,429 <vscale x 2 x i32> %2,430 <vscale x 1 x i1> %3,431 iXLen %4)432 433 ret <vscale x 2 x i32> %a434}435 436define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {437; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma440; CHECK-NEXT: vredmax.vs v8, v9, v10441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(444 <vscale x 2 x i32> %0,445 <vscale x 2 x i32> %1,446 <vscale x 2 x i32> %2,447 iXLen %3)448 449 ret <vscale x 2 x i32> %a450}451 452define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma456; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(460 <vscale x 2 x i32> %0,461 <vscale x 2 x i32> %1,462 <vscale x 2 x i32> %2,463 <vscale x 2 x i1> %3,464 iXLen %4)465 466 ret <vscale x 2 x i32> %a467}468 469define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {470; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma473; CHECK-NEXT: vredmax.vs v8, v10, v9474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(477 <vscale x 2 x i32> %0,478 <vscale x 4 x i32> %1,479 <vscale x 2 x i32> %2,480 iXLen %3)481 482 ret <vscale x 2 x i32> %a483}484 485define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma489; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(493 <vscale x 2 x i32> %0,494 <vscale x 4 x i32> %1,495 <vscale x 2 x i32> %2,496 <vscale x 4 x i1> %3,497 iXLen %4)498 499 ret <vscale x 2 x i32> %a500}501 502define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {503; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma506; CHECK-NEXT: vredmax.vs v8, v12, v9507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(510 <vscale x 2 x i32> %0,511 <vscale x 8 x i32> %1,512 <vscale x 2 x i32> %2,513 iXLen %3)514 515 ret <vscale x 2 x i32> %a516}517 518define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma522; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(526 <vscale x 2 x i32> %0,527 <vscale x 8 x i32> %1,528 <vscale x 2 x i32> %2,529 <vscale x 8 x i1> %3,530 iXLen %4)531 532 ret <vscale x 2 x i32> %a533}534 535define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {536; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma539; CHECK-NEXT: vredmax.vs v8, v16, v9540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(543 <vscale x 2 x i32> %0,544 <vscale x 16 x i32> %1,545 <vscale x 2 x i32> %2,546 iXLen %3)547 548 ret <vscale x 2 x i32> %a549}550 551define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, ma555; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(559 <vscale x 2 x i32> %0,560 <vscale x 16 x i32> %1,561 <vscale x 2 x i32> %2,562 <vscale x 16 x i1> %3,563 iXLen %4)564 565 ret <vscale x 2 x i32> %a566}567 568define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {569; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma572; CHECK-NEXT: vredmax.vs v8, v9, v10573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(576 <vscale x 1 x i64> %0,577 <vscale x 1 x i64> %1,578 <vscale x 1 x i64> %2,579 iXLen %3)580 581 ret <vscale x 1 x i64> %a582}583 584define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma588; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(592 <vscale x 1 x i64> %0,593 <vscale x 1 x i64> %1,594 <vscale x 1 x i64> %2,595 <vscale x 1 x i1> %3,596 iXLen %4)597 598 ret <vscale x 1 x i64> %a599}600 601define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {602; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma605; CHECK-NEXT: vredmax.vs v8, v10, v9606; CHECK-NEXT: ret607entry:608 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(609 <vscale x 1 x i64> %0,610 <vscale x 2 x i64> %1,611 <vscale x 1 x i64> %2,612 iXLen %3)613 614 ret <vscale x 1 x i64> %a615}616 617define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {618; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma621; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t622; CHECK-NEXT: ret623entry:624 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(625 <vscale x 1 x i64> %0,626 <vscale x 2 x i64> %1,627 <vscale x 1 x i64> %2,628 <vscale x 2 x i1> %3,629 iXLen %4)630 631 ret <vscale x 1 x i64> %a632}633 634define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {635; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma638; CHECK-NEXT: vredmax.vs v8, v12, v9639; CHECK-NEXT: ret640entry:641 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(642 <vscale x 1 x i64> %0,643 <vscale x 4 x i64> %1,644 <vscale x 1 x i64> %2,645 iXLen %3)646 647 ret <vscale x 1 x i64> %a648}649 650define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {651; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma654; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t655; CHECK-NEXT: ret656entry:657 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(658 <vscale x 1 x i64> %0,659 <vscale x 4 x i64> %1,660 <vscale x 1 x i64> %2,661 <vscale x 4 x i1> %3,662 iXLen %4)663 664 ret <vscale x 1 x i64> %a665}666 667define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, iXLen %3) nounwind {668; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma671; CHECK-NEXT: vredmax.vs v8, v16, v9672; CHECK-NEXT: ret673entry:674 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(675 <vscale x 1 x i64> %0,676 <vscale x 8 x i64> %1,677 <vscale x 1 x i64> %2,678 iXLen %3)679 680 ret <vscale x 1 x i64> %a681}682 683define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {684; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma687; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t688; CHECK-NEXT: ret689entry:690 %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(691 <vscale x 1 x i64> %0,692 <vscale x 8 x i64> %1,693 <vscale x 1 x i64> %2,694 <vscale x 8 x i1> %3,695 iXLen %4)696 697 ret <vscale x 1 x i64> %a698}699