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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define bfloat @vreduce_fmin_nxv4bf16(<vscale x 4 x bfloat> %val) {8; CHECK-LABEL: vreduce_fmin_nxv4bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma11; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v812; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma13; CHECK-NEXT: vfredmin.vs v8, v10, v1014; CHECK-NEXT: vfmv.f.s fa5, v815; CHECK-NEXT: fcvt.bf16.s fa0, fa516; CHECK-NEXT: ret17 %s = call bfloat @llvm.vector.reduce.fmin.nxv4bf16(<vscale x 4 x bfloat> %val)18 ret bfloat %s19}20 21define bfloat @vreduce_fmax_nxv4bf16(<vscale x 4 x bfloat> %val) {22; CHECK-LABEL: vreduce_fmax_nxv4bf16:23; CHECK: # %bb.0:24; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma25; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v826; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma27; CHECK-NEXT: vfredmax.vs v8, v10, v1028; CHECK-NEXT: vfmv.f.s fa5, v829; CHECK-NEXT: fcvt.bf16.s fa0, fa530; CHECK-NEXT: ret31 %s = call bfloat @llvm.vector.reduce.fmax.nxv4bf16(<vscale x 4 x bfloat> %val)32 ret bfloat %s33}34 35define bfloat @vreduce_fmin_nnan_nxv4bf16(<vscale x 4 x bfloat> %val) {36; CHECK-LABEL: vreduce_fmin_nnan_nxv4bf16:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma39; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v840; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma41; CHECK-NEXT: vfredmin.vs v8, v10, v1042; CHECK-NEXT: vfmv.f.s fa5, v843; CHECK-NEXT: fcvt.bf16.s fa0, fa544; CHECK-NEXT: ret45 %s = call nnan bfloat @llvm.vector.reduce.fmin.nxv4bf16(<vscale x 4 x bfloat> %val)46 ret bfloat %s47}48 49define bfloat @vreduce_fmax_nnan_nxv4bf16(<vscale x 4 x bfloat> %val) {50; CHECK-LABEL: vreduce_fmax_nnan_nxv4bf16:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma53; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v854; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma55; CHECK-NEXT: vfredmax.vs v8, v10, v1056; CHECK-NEXT: vfmv.f.s fa5, v857; CHECK-NEXT: fcvt.bf16.s fa0, fa558; CHECK-NEXT: ret59 %s = call nnan bfloat @llvm.vector.reduce.fmax.nxv4bf16(<vscale x 4 x bfloat> %val)60 ret bfloat %s61}62 63define bfloat @vreduce_fminimum_nxv4bf16(<vscale x 4 x bfloat> %val) {64; CHECK-LABEL: vreduce_fminimum_nxv4bf16:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma67; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v868; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma69; CHECK-NEXT: vmfne.vv v8, v10, v1070; CHECK-NEXT: vcpop.m a0, v871; CHECK-NEXT: beqz a0, .LBB4_272; CHECK-NEXT: # %bb.1:73; CHECK-NEXT: lui a0, 52326474; CHECK-NEXT: fmv.w.x fa5, a075; CHECK-NEXT: fcvt.bf16.s fa0, fa576; CHECK-NEXT: ret77; CHECK-NEXT: .LBB4_2:78; CHECK-NEXT: vfredmin.vs v8, v10, v1079; CHECK-NEXT: vfmv.f.s fa5, v880; CHECK-NEXT: fcvt.bf16.s fa0, fa581; CHECK-NEXT: ret82 %s = call bfloat @llvm.vector.reduce.fminimum.nxv4bf16(<vscale x 4 x bfloat> %val)83 ret bfloat %s84}85 86define bfloat @vreduce_fmaximum_nxv4bf16(<vscale x 4 x bfloat> %val) {87; CHECK-LABEL: vreduce_fmaximum_nxv4bf16:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma90; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v891; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma92; CHECK-NEXT: vmfne.vv v8, v10, v1093; CHECK-NEXT: vcpop.m a0, v894; CHECK-NEXT: beqz a0, .LBB5_295; CHECK-NEXT: # %bb.1:96; CHECK-NEXT: lui a0, 52326497; CHECK-NEXT: fmv.w.x fa5, a098; CHECK-NEXT: fcvt.bf16.s fa0, fa599; CHECK-NEXT: ret100; CHECK-NEXT: .LBB5_2:101; CHECK-NEXT: vfredmax.vs v8, v10, v10102; CHECK-NEXT: vfmv.f.s fa5, v8103; CHECK-NEXT: fcvt.bf16.s fa0, fa5104; CHECK-NEXT: ret105 %s = call bfloat @llvm.vector.reduce.fmaximum.nxv4bf16(<vscale x 4 x bfloat> %val)106 ret bfloat %s107}108 109define bfloat @vreduce_fminimum_nnan_nxv4bf16(<vscale x 4 x bfloat> %val) {110; CHECK-LABEL: vreduce_fminimum_nnan_nxv4bf16:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma113; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8114; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma115; CHECK-NEXT: vfredmin.vs v8, v10, v10116; CHECK-NEXT: vfmv.f.s fa5, v8117; CHECK-NEXT: fcvt.bf16.s fa0, fa5118; CHECK-NEXT: ret119 %s = call nnan bfloat @llvm.vector.reduce.fminimum.nxv4bf16(<vscale x 4 x bfloat> %val)120 ret bfloat %s121}122 123define bfloat @vreduce_fmaximum_nnan_nxv4bf16(<vscale x 4 x bfloat> %val) {124; CHECK-LABEL: vreduce_fmaximum_nnan_nxv4bf16:125; CHECK: # %bb.0:126; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma127; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8128; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma129; CHECK-NEXT: vfredmax.vs v8, v10, v10130; CHECK-NEXT: vfmv.f.s fa5, v8131; CHECK-NEXT: fcvt.bf16.s fa0, fa5132; CHECK-NEXT: ret133 %s = call nnan bfloat @llvm.vector.reduce.fmaximum.nxv4bf16(<vscale x 4 x bfloat> %val)134 ret bfloat %s135}136 137