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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN10 11define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %val) {12; ZVFH-LABEL: vreduce_fmin_nxv4f16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma15; ZVFH-NEXT: vfredmin.vs v8, v8, v816; ZVFH-NEXT: vfmv.f.s fa0, v817; ZVFH-NEXT: ret18;19; ZVFHMIN-LABEL: vreduce_fmin_nxv4f16:20; ZVFHMIN: # %bb.0:21; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma22; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v823; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma24; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v1025; ZVFHMIN-NEXT: vfmv.f.s fa5, v826; ZVFHMIN-NEXT: fcvt.h.s fa0, fa527; ZVFHMIN-NEXT: ret28 %s = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %val)29 ret half %s30}31 32define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %val) {33; ZVFH-LABEL: vreduce_fmax_nxv4f16:34; ZVFH: # %bb.0:35; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma36; ZVFH-NEXT: vfredmax.vs v8, v8, v837; ZVFH-NEXT: vfmv.f.s fa0, v838; ZVFH-NEXT: ret39;40; ZVFHMIN-LABEL: vreduce_fmax_nxv4f16:41; ZVFHMIN: # %bb.0:42; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma43; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v844; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma45; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v1046; ZVFHMIN-NEXT: vfmv.f.s fa5, v847; ZVFHMIN-NEXT: fcvt.h.s fa0, fa548; ZVFHMIN-NEXT: ret49 %s = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %val)50 ret half %s51}52 53define half @vreduce_fmin_nnan_nxv4f16(<vscale x 4 x half> %val) {54; ZVFH-LABEL: vreduce_fmin_nnan_nxv4f16:55; ZVFH: # %bb.0:56; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma57; ZVFH-NEXT: vfredmin.vs v8, v8, v858; ZVFH-NEXT: vfmv.f.s fa0, v859; ZVFH-NEXT: ret60;61; ZVFHMIN-LABEL: vreduce_fmin_nnan_nxv4f16:62; ZVFHMIN: # %bb.0:63; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma64; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v865; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma66; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v1067; ZVFHMIN-NEXT: vfmv.f.s fa5, v868; ZVFHMIN-NEXT: fcvt.h.s fa0, fa569; ZVFHMIN-NEXT: ret70 %s = call nnan half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %val)71 ret half %s72}73 74define half @vreduce_fmax_nnan_nxv4f16(<vscale x 4 x half> %val) {75; ZVFH-LABEL: vreduce_fmax_nnan_nxv4f16:76; ZVFH: # %bb.0:77; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma78; ZVFH-NEXT: vfredmax.vs v8, v8, v879; ZVFH-NEXT: vfmv.f.s fa0, v880; ZVFH-NEXT: ret81;82; ZVFHMIN-LABEL: vreduce_fmax_nnan_nxv4f16:83; ZVFHMIN: # %bb.0:84; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma85; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v886; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma87; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v1088; ZVFHMIN-NEXT: vfmv.f.s fa5, v889; ZVFHMIN-NEXT: fcvt.h.s fa0, fa590; ZVFHMIN-NEXT: ret91 %s = call nnan half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %val)92 ret half %s93}94 95define half @vreduce_fminimum_nxv4f16(<vscale x 4 x half> %val) {96; ZVFH-LABEL: vreduce_fminimum_nxv4f16:97; ZVFH: # %bb.0:98; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma99; ZVFH-NEXT: vmfne.vv v9, v8, v8100; ZVFH-NEXT: vcpop.m a0, v9101; ZVFH-NEXT: beqz a0, .LBB4_2102; ZVFH-NEXT: # %bb.1:103; ZVFH-NEXT: lui a0, 8104; ZVFH-NEXT: addi a0, a0, -512105; ZVFH-NEXT: fmv.h.x fa0, a0106; ZVFH-NEXT: ret107; ZVFH-NEXT: .LBB4_2:108; ZVFH-NEXT: vfredmin.vs v8, v8, v8109; ZVFH-NEXT: vfmv.f.s fa0, v8110; ZVFH-NEXT: ret111;112; ZVFHMIN-LABEL: vreduce_fminimum_nxv4f16:113; ZVFHMIN: # %bb.0:114; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma115; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8116; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma117; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10118; ZVFHMIN-NEXT: vcpop.m a0, v8119; ZVFHMIN-NEXT: beqz a0, .LBB4_2120; ZVFHMIN-NEXT: # %bb.1:121; ZVFHMIN-NEXT: lui a0, 523264122; ZVFHMIN-NEXT: fmv.w.x fa5, a0123; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5124; ZVFHMIN-NEXT: ret125; ZVFHMIN-NEXT: .LBB4_2:126; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10127; ZVFHMIN-NEXT: vfmv.f.s fa5, v8128; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5129; ZVFHMIN-NEXT: ret130 %s = call half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half> %val)131 ret half %s132}133 134define half @vreduce_fmaximum_nxv4f16(<vscale x 4 x half> %val) {135; ZVFH-LABEL: vreduce_fmaximum_nxv4f16:136; ZVFH: # %bb.0:137; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma138; ZVFH-NEXT: vmfne.vv v9, v8, v8139; ZVFH-NEXT: vcpop.m a0, v9140; ZVFH-NEXT: beqz a0, .LBB5_2141; ZVFH-NEXT: # %bb.1:142; ZVFH-NEXT: lui a0, 8143; ZVFH-NEXT: addi a0, a0, -512144; ZVFH-NEXT: fmv.h.x fa0, a0145; ZVFH-NEXT: ret146; ZVFH-NEXT: .LBB5_2:147; ZVFH-NEXT: vfredmax.vs v8, v8, v8148; ZVFH-NEXT: vfmv.f.s fa0, v8149; ZVFH-NEXT: ret150;151; ZVFHMIN-LABEL: vreduce_fmaximum_nxv4f16:152; ZVFHMIN: # %bb.0:153; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma154; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8155; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma156; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10157; ZVFHMIN-NEXT: vcpop.m a0, v8158; ZVFHMIN-NEXT: beqz a0, .LBB5_2159; ZVFHMIN-NEXT: # %bb.1:160; ZVFHMIN-NEXT: lui a0, 523264161; ZVFHMIN-NEXT: fmv.w.x fa5, a0162; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5163; ZVFHMIN-NEXT: ret164; ZVFHMIN-NEXT: .LBB5_2:165; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10166; ZVFHMIN-NEXT: vfmv.f.s fa5, v8167; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5168; ZVFHMIN-NEXT: ret169 %s = call half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half> %val)170 ret half %s171}172 173define half @vreduce_fminimum_nnan_nxv4f16(<vscale x 4 x half> %val) {174; ZVFH-LABEL: vreduce_fminimum_nnan_nxv4f16:175; ZVFH: # %bb.0:176; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma177; ZVFH-NEXT: vfredmin.vs v8, v8, v8178; ZVFH-NEXT: vfmv.f.s fa0, v8179; ZVFH-NEXT: ret180;181; ZVFHMIN-LABEL: vreduce_fminimum_nnan_nxv4f16:182; ZVFHMIN: # %bb.0:183; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma184; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8185; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma186; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10187; ZVFHMIN-NEXT: vfmv.f.s fa5, v8188; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5189; ZVFHMIN-NEXT: ret190 %s = call nnan half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half> %val)191 ret half %s192}193 194define half @vreduce_fmaximum_nnan_nxv4f16(<vscale x 4 x half> %val) {195; ZVFH-LABEL: vreduce_fmaximum_nnan_nxv4f16:196; ZVFH: # %bb.0:197; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma198; ZVFH-NEXT: vfredmax.vs v8, v8, v8199; ZVFH-NEXT: vfmv.f.s fa0, v8200; ZVFH-NEXT: ret201;202; ZVFHMIN-LABEL: vreduce_fmaximum_nnan_nxv4f16:203; ZVFHMIN: # %bb.0:204; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma205; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8206; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma207; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10208; ZVFHMIN-NEXT: vfmv.f.s fa5, v8209; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5210; ZVFHMIN-NEXT: ret211 %s = call nnan half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half> %val)212 ret half %s213}214 215