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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v,+m -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define half @vreduce_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {8; CHECK-LABEL: vreduce_fadd_nxv1f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma11; CHECK-NEXT: vfmv.s.f v9, fa012; CHECK-NEXT: vfredusum.vs v8, v8, v913; CHECK-NEXT: vfmv.f.s fa0, v814; CHECK-NEXT: ret15 %red = call reassoc half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)16 ret half %red17}18 19define half @vreduce_ord_fadd_nxv1f16(<vscale x 1 x half> %v, half %s) {20; CHECK-LABEL: vreduce_ord_fadd_nxv1f16:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma23; CHECK-NEXT: vfmv.s.f v9, fa024; CHECK-NEXT: vfredosum.vs v8, v8, v925; CHECK-NEXT: vfmv.f.s fa0, v826; CHECK-NEXT: ret27 %red = call half @llvm.vector.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v)28 ret half %red29}30 31define half @vreduce_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {32; CHECK-LABEL: vreduce_fadd_nxv2f16:33; CHECK: # %bb.0:34; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma35; CHECK-NEXT: vfmv.s.f v9, fa036; CHECK-NEXT: vfredusum.vs v8, v8, v937; CHECK-NEXT: vfmv.f.s fa0, v838; CHECK-NEXT: ret39 %red = call reassoc half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)40 ret half %red41}42 43define half @vreduce_ord_fadd_nxv2f16(<vscale x 2 x half> %v, half %s) {44; CHECK-LABEL: vreduce_ord_fadd_nxv2f16:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma47; CHECK-NEXT: vfmv.s.f v9, fa048; CHECK-NEXT: vfredosum.vs v8, v8, v949; CHECK-NEXT: vfmv.f.s fa0, v850; CHECK-NEXT: ret51 %red = call half @llvm.vector.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v)52 ret half %red53}54 55define half @vreduce_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {56; CHECK-LABEL: vreduce_fadd_nxv4f16:57; CHECK: # %bb.0:58; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma59; CHECK-NEXT: vfmv.s.f v9, fa060; CHECK-NEXT: vfredusum.vs v8, v8, v961; CHECK-NEXT: vfmv.f.s fa0, v862; CHECK-NEXT: ret63 %red = call reassoc half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)64 ret half %red65}66 67define half @vreduce_ord_fadd_nxv4f16(<vscale x 4 x half> %v, half %s) {68; CHECK-LABEL: vreduce_ord_fadd_nxv4f16:69; CHECK: # %bb.0:70; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma71; CHECK-NEXT: vfmv.s.f v9, fa072; CHECK-NEXT: vfredosum.vs v8, v8, v973; CHECK-NEXT: vfmv.f.s fa0, v874; CHECK-NEXT: ret75 %red = call half @llvm.vector.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v)76 ret half %red77}78 79define float @vreduce_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {80; CHECK-LABEL: vreduce_fadd_nxv1f32:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma83; CHECK-NEXT: vfmv.s.f v9, fa084; CHECK-NEXT: vfredusum.vs v8, v8, v985; CHECK-NEXT: vfmv.f.s fa0, v886; CHECK-NEXT: ret87 %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)88 ret float %red89}90 91define float @vreduce_ord_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {92; CHECK-LABEL: vreduce_ord_fadd_nxv1f32:93; CHECK: # %bb.0:94; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma95; CHECK-NEXT: vfmv.s.f v9, fa096; CHECK-NEXT: vfredosum.vs v8, v8, v997; CHECK-NEXT: vfmv.f.s fa0, v898; CHECK-NEXT: ret99 %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)100 ret float %red101}102 103define float @vreduce_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {104; CHECK-LABEL: vreduce_fwadd_nxv1f32:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma107; CHECK-NEXT: vfmv.s.f v9, fa0108; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma109; CHECK-NEXT: vfwredusum.vs v8, v8, v9110; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma111; CHECK-NEXT: vfmv.f.s fa0, v8112; CHECK-NEXT: ret113 %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>114 %red = call reassoc float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)115 ret float %red116}117 118define float @vreduce_ord_fwadd_nxv1f32(<vscale x 1 x half> %v, float %s) {119; CHECK-LABEL: vreduce_ord_fwadd_nxv1f32:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma122; CHECK-NEXT: vfmv.s.f v9, fa0123; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma124; CHECK-NEXT: vfwredosum.vs v8, v8, v9125; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma126; CHECK-NEXT: vfmv.f.s fa0, v8127; CHECK-NEXT: ret128 %e = fpext <vscale x 1 x half> %v to <vscale x 1 x float>129 %red = call float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %e)130 ret float %red131}132 133define float @vreduce_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {134; CHECK-LABEL: vreduce_fadd_nxv2f32:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma137; CHECK-NEXT: vfmv.s.f v9, fa0138; CHECK-NEXT: vfredusum.vs v8, v8, v9139; CHECK-NEXT: vfmv.f.s fa0, v8140; CHECK-NEXT: ret141 %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)142 ret float %red143}144 145define float @vreduce_ord_fadd_nxv2f32(<vscale x 2 x float> %v, float %s) {146; CHECK-LABEL: vreduce_ord_fadd_nxv2f32:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma149; CHECK-NEXT: vfmv.s.f v9, fa0150; CHECK-NEXT: vfredosum.vs v8, v8, v9151; CHECK-NEXT: vfmv.f.s fa0, v8152; CHECK-NEXT: ret153 %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v)154 ret float %red155}156 157define float @vreduce_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {158; CHECK-LABEL: vreduce_fwadd_nxv2f32:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma161; CHECK-NEXT: vfmv.s.f v9, fa0162; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma163; CHECK-NEXT: vfwredusum.vs v8, v8, v9164; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma165; CHECK-NEXT: vfmv.f.s fa0, v8166; CHECK-NEXT: ret167 %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>168 %red = call reassoc float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)169 ret float %red170}171 172define float @vreduce_ord_fwadd_nxv2f32(<vscale x 2 x half> %v, float %s) {173; CHECK-LABEL: vreduce_ord_fwadd_nxv2f32:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma176; CHECK-NEXT: vfmv.s.f v9, fa0177; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma178; CHECK-NEXT: vfwredosum.vs v8, v8, v9179; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma180; CHECK-NEXT: vfmv.f.s fa0, v8181; CHECK-NEXT: ret182 %e = fpext <vscale x 2 x half> %v to <vscale x 2 x float>183 %red = call float @llvm.vector.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %e)184 ret float %red185}186 187define float @vreduce_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {188; CHECK-LABEL: vreduce_fadd_nxv4f32:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma191; CHECK-NEXT: vfmv.s.f v10, fa0192; CHECK-NEXT: vfredusum.vs v8, v8, v10193; CHECK-NEXT: vfmv.f.s fa0, v8194; CHECK-NEXT: ret195 %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)196 ret float %red197}198 199define float @vreduce_ord_fadd_nxv4f32(<vscale x 4 x float> %v, float %s) {200; CHECK-LABEL: vreduce_ord_fadd_nxv4f32:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma203; CHECK-NEXT: vfmv.s.f v10, fa0204; CHECK-NEXT: vfredosum.vs v8, v8, v10205; CHECK-NEXT: vfmv.f.s fa0, v8206; CHECK-NEXT: ret207 %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v)208 ret float %red209}210 211define float @vreduce_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {212; CHECK-LABEL: vreduce_fwadd_nxv4f32:213; CHECK: # %bb.0:214; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma215; CHECK-NEXT: vfmv.s.f v9, fa0216; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma217; CHECK-NEXT: vfwredusum.vs v8, v8, v9218; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma219; CHECK-NEXT: vfmv.f.s fa0, v8220; CHECK-NEXT: ret221 %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>222 %red = call reassoc float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)223 ret float %red224}225 226define float @vreduce_ord_fwadd_nxv4f32(<vscale x 4 x half> %v, float %s) {227; CHECK-LABEL: vreduce_ord_fwadd_nxv4f32:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma230; CHECK-NEXT: vfmv.s.f v9, fa0231; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma232; CHECK-NEXT: vfwredosum.vs v8, v8, v9233; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma234; CHECK-NEXT: vfmv.f.s fa0, v8235; CHECK-NEXT: ret236 %e = fpext <vscale x 4 x half> %v to <vscale x 4 x float>237 %red = call float @llvm.vector.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %e)238 ret float %red239}240 241define double @vreduce_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {242; CHECK-LABEL: vreduce_fadd_nxv1f64:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma245; CHECK-NEXT: vfmv.s.f v9, fa0246; CHECK-NEXT: vfredusum.vs v8, v8, v9247; CHECK-NEXT: vfmv.f.s fa0, v8248; CHECK-NEXT: ret249 %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)250 ret double %red251}252 253define double @vreduce_ord_fadd_nxv1f64(<vscale x 1 x double> %v, double %s) {254; CHECK-LABEL: vreduce_ord_fadd_nxv1f64:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma257; CHECK-NEXT: vfmv.s.f v9, fa0258; CHECK-NEXT: vfredosum.vs v8, v8, v9259; CHECK-NEXT: vfmv.f.s fa0, v8260; CHECK-NEXT: ret261 %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v)262 ret double %red263}264 265define double @vreduce_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {266; CHECK-LABEL: vreduce_fwadd_nxv1f64:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma269; CHECK-NEXT: vfmv.s.f v9, fa0270; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma271; CHECK-NEXT: vfwredusum.vs v8, v8, v9272; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma273; CHECK-NEXT: vfmv.f.s fa0, v8274; CHECK-NEXT: ret275 %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>276 %red = call reassoc double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)277 ret double %red278}279 280define double @vreduce_ord_fwadd_nxv1f64(<vscale x 1 x float> %v, double %s) {281; CHECK-LABEL: vreduce_ord_fwadd_nxv1f64:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma284; CHECK-NEXT: vfmv.s.f v9, fa0285; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma286; CHECK-NEXT: vfwredosum.vs v8, v8, v9287; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma288; CHECK-NEXT: vfmv.f.s fa0, v8289; CHECK-NEXT: ret290 %e = fpext <vscale x 1 x float> %v to <vscale x 1 x double>291 %red = call double @llvm.vector.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %e)292 ret double %red293}294 295define double @vreduce_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {296; CHECK-LABEL: vreduce_fadd_nxv2f64:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma299; CHECK-NEXT: vfmv.s.f v10, fa0300; CHECK-NEXT: vfredusum.vs v8, v8, v10301; CHECK-NEXT: vfmv.f.s fa0, v8302; CHECK-NEXT: ret303 %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)304 ret double %red305}306 307define double @vreduce_ord_fadd_nxv2f64(<vscale x 2 x double> %v, double %s) {308; CHECK-LABEL: vreduce_ord_fadd_nxv2f64:309; CHECK: # %bb.0:310; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma311; CHECK-NEXT: vfmv.s.f v10, fa0312; CHECK-NEXT: vfredosum.vs v8, v8, v10313; CHECK-NEXT: vfmv.f.s fa0, v8314; CHECK-NEXT: ret315 %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v)316 ret double %red317}318 319define double @vreduce_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {320; CHECK-LABEL: vreduce_fwadd_nxv2f64:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma323; CHECK-NEXT: vfmv.s.f v9, fa0324; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma325; CHECK-NEXT: vfwredusum.vs v8, v8, v9326; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma327; CHECK-NEXT: vfmv.f.s fa0, v8328; CHECK-NEXT: ret329 %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>330 %red = call reassoc double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)331 ret double %red332}333 334define double @vreduce_ord_fwadd_nxv2f64(<vscale x 2 x float> %v, double %s) {335; CHECK-LABEL: vreduce_ord_fwadd_nxv2f64:336; CHECK: # %bb.0:337; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma338; CHECK-NEXT: vfmv.s.f v9, fa0339; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma340; CHECK-NEXT: vfwredosum.vs v8, v8, v9341; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma342; CHECK-NEXT: vfmv.f.s fa0, v8343; CHECK-NEXT: ret344 %e = fpext <vscale x 2 x float> %v to <vscale x 2 x double>345 %red = call double @llvm.vector.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %e)346 ret double %red347}348 349define double @vreduce_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {350; CHECK-LABEL: vreduce_fadd_nxv4f64:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma353; CHECK-NEXT: vfmv.s.f v12, fa0354; CHECK-NEXT: vfredusum.vs v8, v8, v12355; CHECK-NEXT: vfmv.f.s fa0, v8356; CHECK-NEXT: ret357 %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)358 ret double %red359}360 361define double @vreduce_ord_fadd_nxv4f64(<vscale x 4 x double> %v, double %s) {362; CHECK-LABEL: vreduce_ord_fadd_nxv4f64:363; CHECK: # %bb.0:364; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma365; CHECK-NEXT: vfmv.s.f v12, fa0366; CHECK-NEXT: vfredosum.vs v8, v8, v12367; CHECK-NEXT: vfmv.f.s fa0, v8368; CHECK-NEXT: ret369 %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v)370 ret double %red371}372 373define double @vreduce_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {374; CHECK-LABEL: vreduce_fwadd_nxv4f64:375; CHECK: # %bb.0:376; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma377; CHECK-NEXT: vfmv.s.f v10, fa0378; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma379; CHECK-NEXT: vfwredusum.vs v8, v8, v10380; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma381; CHECK-NEXT: vfmv.f.s fa0, v8382; CHECK-NEXT: ret383 %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>384 %red = call reassoc double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)385 ret double %red386}387 388define double @vreduce_ord_fwadd_nxv4f64(<vscale x 4 x float> %v, double %s) {389; CHECK-LABEL: vreduce_ord_fwadd_nxv4f64:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma392; CHECK-NEXT: vfmv.s.f v10, fa0393; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma394; CHECK-NEXT: vfwredosum.vs v8, v8, v10395; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma396; CHECK-NEXT: vfmv.f.s fa0, v8397; CHECK-NEXT: ret398 %e = fpext <vscale x 4 x float> %v to <vscale x 4 x double>399 %red = call double @llvm.vector.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %e)400 ret double %red401}402 403define half @vreduce_fmin_nxv1f16(<vscale x 1 x half> %v) {404; CHECK-LABEL: vreduce_fmin_nxv1f16:405; CHECK: # %bb.0:406; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma407; CHECK-NEXT: vfredmin.vs v8, v8, v8408; CHECK-NEXT: vfmv.f.s fa0, v8409; CHECK-NEXT: ret410 %red = call half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)411 ret half %red412}413 414define half @vreduce_fmin_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {415; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans:416; CHECK: # %bb.0:417; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma418; CHECK-NEXT: vfredmin.vs v8, v8, v8419; CHECK-NEXT: vfmv.f.s fa0, v8420; CHECK-NEXT: ret421 %red = call nnan half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)422 ret half %red423}424 425define half @vreduce_fmin_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {426; CHECK-LABEL: vreduce_fmin_nxv1f16_nonans_noinfs:427; CHECK: # %bb.0:428; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma429; CHECK-NEXT: vfredmin.vs v8, v8, v8430; CHECK-NEXT: vfmv.f.s fa0, v8431; CHECK-NEXT: ret432 %red = call nnan ninf half @llvm.vector.reduce.fmin.nxv1f16(<vscale x 1 x half> %v)433 ret half %red434}435 436define half @vreduce_fmin_nxv2f16(<vscale x 2 x half> %v) {437; CHECK-LABEL: vreduce_fmin_nxv2f16:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma440; CHECK-NEXT: vfredmin.vs v8, v8, v8441; CHECK-NEXT: vfmv.f.s fa0, v8442; CHECK-NEXT: ret443 %red = call half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half> %v)444 ret half %red445}446 447define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %v) {448; CHECK-LABEL: vreduce_fmin_nxv4f16:449; CHECK: # %bb.0:450; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma451; CHECK-NEXT: vfredmin.vs v8, v8, v8452; CHECK-NEXT: vfmv.f.s fa0, v8453; CHECK-NEXT: ret454 %red = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %v)455 ret half %red456}457 458define half @vreduce_fmin_nxv64f16(<vscale x 64 x half> %v) {459; CHECK-LABEL: vreduce_fmin_nxv64f16:460; CHECK: # %bb.0:461; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma462; CHECK-NEXT: vfmin.vv v8, v8, v16463; CHECK-NEXT: vfredmin.vs v8, v8, v8464; CHECK-NEXT: vfmv.f.s fa0, v8465; CHECK-NEXT: ret466 %red = call half @llvm.vector.reduce.fmin.nxv64f16(<vscale x 64 x half> %v)467 ret half %red468}469 470define float @vreduce_fmin_nxv1f32(<vscale x 1 x float> %v) {471; CHECK-LABEL: vreduce_fmin_nxv1f32:472; CHECK: # %bb.0:473; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma474; CHECK-NEXT: vfredmin.vs v8, v8, v8475; CHECK-NEXT: vfmv.f.s fa0, v8476; CHECK-NEXT: ret477 %red = call float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)478 ret float %red479}480 481define float @vreduce_fmin_nxv1f32_nonans(<vscale x 1 x float> %v) {482; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma485; CHECK-NEXT: vfredmin.vs v8, v8, v8486; CHECK-NEXT: vfmv.f.s fa0, v8487; CHECK-NEXT: ret488 %red = call nnan float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)489 ret float %red490}491 492define float @vreduce_fmin_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {493; CHECK-LABEL: vreduce_fmin_nxv1f32_nonans_noinfs:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma496; CHECK-NEXT: vfredmin.vs v8, v8, v8497; CHECK-NEXT: vfmv.f.s fa0, v8498; CHECK-NEXT: ret499 %red = call nnan ninf float @llvm.vector.reduce.fmin.nxv1f32(<vscale x 1 x float> %v)500 ret float %red501}502 503define float @vreduce_fmin_nxv2f32(<vscale x 2 x float> %v) {504; CHECK-LABEL: vreduce_fmin_nxv2f32:505; CHECK: # %bb.0:506; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma507; CHECK-NEXT: vfredmin.vs v8, v8, v8508; CHECK-NEXT: vfmv.f.s fa0, v8509; CHECK-NEXT: ret510 %red = call float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float> %v)511 ret float %red512}513 514define float @vreduce_fmin_nxv4f32(<vscale x 4 x float> %v) {515; CHECK-LABEL: vreduce_fmin_nxv4f32:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma518; CHECK-NEXT: vfredmin.vs v8, v8, v8519; CHECK-NEXT: vfmv.f.s fa0, v8520; CHECK-NEXT: ret521 %red = call float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float> %v)522 ret float %red523}524 525define float @vreduce_fmin_nxv32f32(<vscale x 32 x float> %v) {526; CHECK-LABEL: vreduce_fmin_nxv32f32:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma529; CHECK-NEXT: vfmin.vv v8, v8, v16530; CHECK-NEXT: vfredmin.vs v8, v8, v8531; CHECK-NEXT: vfmv.f.s fa0, v8532; CHECK-NEXT: ret533 %red = call float @llvm.vector.reduce.fmin.nxv32f32(<vscale x 32 x float> %v)534 ret float %red535}536 537define double @vreduce_fmin_nxv1f64(<vscale x 1 x double> %v) {538; CHECK-LABEL: vreduce_fmin_nxv1f64:539; CHECK: # %bb.0:540; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma541; CHECK-NEXT: vfredmin.vs v8, v8, v8542; CHECK-NEXT: vfmv.f.s fa0, v8543; CHECK-NEXT: ret544 %red = call double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)545 ret double %red546}547 548define double @vreduce_fmin_nxv1f64_nonans(<vscale x 1 x double> %v) {549; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans:550; CHECK: # %bb.0:551; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma552; CHECK-NEXT: vfredmin.vs v8, v8, v8553; CHECK-NEXT: vfmv.f.s fa0, v8554; CHECK-NEXT: ret555 %red = call nnan double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)556 ret double %red557}558 559define double @vreduce_fmin_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {560; CHECK-LABEL: vreduce_fmin_nxv1f64_nonans_noinfs:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma563; CHECK-NEXT: vfredmin.vs v8, v8, v8564; CHECK-NEXT: vfmv.f.s fa0, v8565; CHECK-NEXT: ret566 %red = call nnan ninf double @llvm.vector.reduce.fmin.nxv1f64(<vscale x 1 x double> %v)567 ret double %red568}569 570define double @vreduce_fmin_nxv2f64(<vscale x 2 x double> %v) {571; CHECK-LABEL: vreduce_fmin_nxv2f64:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma574; CHECK-NEXT: vfredmin.vs v8, v8, v8575; CHECK-NEXT: vfmv.f.s fa0, v8576; CHECK-NEXT: ret577 %red = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %v)578 ret double %red579}580 581define double @vreduce_fmin_nxv4f64(<vscale x 4 x double> %v) {582; CHECK-LABEL: vreduce_fmin_nxv4f64:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma585; CHECK-NEXT: vfredmin.vs v8, v8, v8586; CHECK-NEXT: vfmv.f.s fa0, v8587; CHECK-NEXT: ret588 %red = call double @llvm.vector.reduce.fmin.nxv4f64(<vscale x 4 x double> %v)589 ret double %red590}591 592define double @vreduce_fmin_nxv16f64(<vscale x 16 x double> %v) {593; CHECK-LABEL: vreduce_fmin_nxv16f64:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma596; CHECK-NEXT: vfmin.vv v8, v8, v16597; CHECK-NEXT: vfredmin.vs v8, v8, v8598; CHECK-NEXT: vfmv.f.s fa0, v8599; CHECK-NEXT: ret600 %red = call double @llvm.vector.reduce.fmin.nxv16f64(<vscale x 16 x double> %v)601 ret double %red602}603 604define half @vreduce_fmax_nxv1f16(<vscale x 1 x half> %v) {605; CHECK-LABEL: vreduce_fmax_nxv1f16:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma608; CHECK-NEXT: vfredmax.vs v8, v8, v8609; CHECK-NEXT: vfmv.f.s fa0, v8610; CHECK-NEXT: ret611 %red = call half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)612 ret half %red613}614 615define half @vreduce_fmax_nxv1f16_nonans(<vscale x 1 x half> %v) #0 {616; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma619; CHECK-NEXT: vfredmax.vs v8, v8, v8620; CHECK-NEXT: vfmv.f.s fa0, v8621; CHECK-NEXT: ret622 %red = call nnan half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)623 ret half %red624}625 626define half @vreduce_fmax_nxv1f16_nonans_noinfs(<vscale x 1 x half> %v) #1 {627; CHECK-LABEL: vreduce_fmax_nxv1f16_nonans_noinfs:628; CHECK: # %bb.0:629; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma630; CHECK-NEXT: vfredmax.vs v8, v8, v8631; CHECK-NEXT: vfmv.f.s fa0, v8632; CHECK-NEXT: ret633 %red = call nnan ninf half @llvm.vector.reduce.fmax.nxv1f16(<vscale x 1 x half> %v)634 ret half %red635}636 637define half @vreduce_fmax_nxv2f16(<vscale x 2 x half> %v) {638; CHECK-LABEL: vreduce_fmax_nxv2f16:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma641; CHECK-NEXT: vfredmax.vs v8, v8, v8642; CHECK-NEXT: vfmv.f.s fa0, v8643; CHECK-NEXT: ret644 %red = call half @llvm.vector.reduce.fmax.nxv2f16(<vscale x 2 x half> %v)645 ret half %red646}647 648define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %v) {649; CHECK-LABEL: vreduce_fmax_nxv4f16:650; CHECK: # %bb.0:651; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma652; CHECK-NEXT: vfredmax.vs v8, v8, v8653; CHECK-NEXT: vfmv.f.s fa0, v8654; CHECK-NEXT: ret655 %red = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %v)656 ret half %red657}658 659define half @vreduce_fmax_nxv64f16(<vscale x 64 x half> %v) {660; CHECK-LABEL: vreduce_fmax_nxv64f16:661; CHECK: # %bb.0:662; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma663; CHECK-NEXT: vfmax.vv v8, v8, v16664; CHECK-NEXT: vfredmax.vs v8, v8, v8665; CHECK-NEXT: vfmv.f.s fa0, v8666; CHECK-NEXT: ret667 %red = call half @llvm.vector.reduce.fmax.nxv64f16(<vscale x 64 x half> %v)668 ret half %red669}670 671define float @vreduce_fmax_nxv1f32(<vscale x 1 x float> %v) {672; CHECK-LABEL: vreduce_fmax_nxv1f32:673; CHECK: # %bb.0:674; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma675; CHECK-NEXT: vfredmax.vs v8, v8, v8676; CHECK-NEXT: vfmv.f.s fa0, v8677; CHECK-NEXT: ret678 %red = call float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)679 ret float %red680}681 682define float @vreduce_fmax_nxv1f32_nonans(<vscale x 1 x float> %v) {683; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans:684; CHECK: # %bb.0:685; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma686; CHECK-NEXT: vfredmax.vs v8, v8, v8687; CHECK-NEXT: vfmv.f.s fa0, v8688; CHECK-NEXT: ret689 %red = call nnan float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)690 ret float %red691}692 693define float @vreduce_fmax_nxv1f32_nonans_noinfs(<vscale x 1 x float> %v) {694; CHECK-LABEL: vreduce_fmax_nxv1f32_nonans_noinfs:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma697; CHECK-NEXT: vfredmax.vs v8, v8, v8698; CHECK-NEXT: vfmv.f.s fa0, v8699; CHECK-NEXT: ret700 %red = call nnan ninf float @llvm.vector.reduce.fmax.nxv1f32(<vscale x 1 x float> %v)701 ret float %red702}703 704define float @vreduce_fmax_nxv2f32(<vscale x 2 x float> %v) {705; CHECK-LABEL: vreduce_fmax_nxv2f32:706; CHECK: # %bb.0:707; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma708; CHECK-NEXT: vfredmax.vs v8, v8, v8709; CHECK-NEXT: vfmv.f.s fa0, v8710; CHECK-NEXT: ret711 %red = call float @llvm.vector.reduce.fmax.nxv2f32(<vscale x 2 x float> %v)712 ret float %red713}714 715define float @vreduce_fmax_nxv4f32(<vscale x 4 x float> %v) {716; CHECK-LABEL: vreduce_fmax_nxv4f32:717; CHECK: # %bb.0:718; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma719; CHECK-NEXT: vfredmax.vs v8, v8, v8720; CHECK-NEXT: vfmv.f.s fa0, v8721; CHECK-NEXT: ret722 %red = call float @llvm.vector.reduce.fmax.nxv4f32(<vscale x 4 x float> %v)723 ret float %red724}725 726define float @vreduce_fmax_nxv32f32(<vscale x 32 x float> %v) {727; CHECK-LABEL: vreduce_fmax_nxv32f32:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma730; CHECK-NEXT: vfmax.vv v8, v8, v16731; CHECK-NEXT: vfredmax.vs v8, v8, v8732; CHECK-NEXT: vfmv.f.s fa0, v8733; CHECK-NEXT: ret734 %red = call float @llvm.vector.reduce.fmax.nxv32f32(<vscale x 32 x float> %v)735 ret float %red736}737 738define double @vreduce_fmax_nxv1f64(<vscale x 1 x double> %v) {739; CHECK-LABEL: vreduce_fmax_nxv1f64:740; CHECK: # %bb.0:741; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma742; CHECK-NEXT: vfredmax.vs v8, v8, v8743; CHECK-NEXT: vfmv.f.s fa0, v8744; CHECK-NEXT: ret745 %red = call double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)746 ret double %red747}748 749define double @vreduce_fmax_nxv1f64_nonans(<vscale x 1 x double> %v) {750; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma753; CHECK-NEXT: vfredmax.vs v8, v8, v8754; CHECK-NEXT: vfmv.f.s fa0, v8755; CHECK-NEXT: ret756 %red = call nnan double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)757 ret double %red758}759 760define double @vreduce_fmax_nxv1f64_nonans_noinfs(<vscale x 1 x double> %v) {761; CHECK-LABEL: vreduce_fmax_nxv1f64_nonans_noinfs:762; CHECK: # %bb.0:763; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma764; CHECK-NEXT: vfredmax.vs v8, v8, v8765; CHECK-NEXT: vfmv.f.s fa0, v8766; CHECK-NEXT: ret767 %red = call nnan ninf double @llvm.vector.reduce.fmax.nxv1f64(<vscale x 1 x double> %v)768 ret double %red769}770 771define double @vreduce_fmax_nxv2f64(<vscale x 2 x double> %v) {772; CHECK-LABEL: vreduce_fmax_nxv2f64:773; CHECK: # %bb.0:774; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma775; CHECK-NEXT: vfredmax.vs v8, v8, v8776; CHECK-NEXT: vfmv.f.s fa0, v8777; CHECK-NEXT: ret778 %red = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %v)779 ret double %red780}781 782define double @vreduce_fmax_nxv4f64(<vscale x 4 x double> %v) {783; CHECK-LABEL: vreduce_fmax_nxv4f64:784; CHECK: # %bb.0:785; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma786; CHECK-NEXT: vfredmax.vs v8, v8, v8787; CHECK-NEXT: vfmv.f.s fa0, v8788; CHECK-NEXT: ret789 %red = call double @llvm.vector.reduce.fmax.nxv4f64(<vscale x 4 x double> %v)790 ret double %red791}792 793define double @vreduce_fmax_nxv16f64(<vscale x 16 x double> %v) {794; CHECK-LABEL: vreduce_fmax_nxv16f64:795; CHECK: # %bb.0:796; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma797; CHECK-NEXT: vfmax.vv v8, v8, v16798; CHECK-NEXT: vfredmax.vs v8, v8, v8799; CHECK-NEXT: vfmv.f.s fa0, v8800; CHECK-NEXT: ret801 %red = call double @llvm.vector.reduce.fmax.nxv16f64(<vscale x 16 x double> %v)802 ret double %red803}804 805define float @vreduce_nsz_fadd_nxv1f32(<vscale x 1 x float> %v, float %s) {806; CHECK-LABEL: vreduce_nsz_fadd_nxv1f32:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma809; CHECK-NEXT: vfmv.s.f v9, fa0810; CHECK-NEXT: vfredusum.vs v8, v8, v9811; CHECK-NEXT: vfmv.f.s fa0, v8812; CHECK-NEXT: ret813 %red = call reassoc nsz float @llvm.vector.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v)814 ret float %red815}816 817; Test Widen VECREDUCE_SEQ_FADD818 819define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {820; CHECK-LABEL: vreduce_ord_fadd_nxv3f16:821; CHECK: # %bb.0:822; CHECK-NEXT: csrr a0, vlenb823; CHECK-NEXT: srli a1, a0, 3824; CHECK-NEXT: srli a0, a0, 2825; CHECK-NEXT: add a0, a0, a1826; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma827; CHECK-NEXT: vfmv.s.f v9, fa0828; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma829; CHECK-NEXT: vfredosum.vs v9, v8, v9830; CHECK-NEXT: vfmv.f.s fa0, v9831; CHECK-NEXT: ret832 %red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)833 ret half %red834}835 836define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {837; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:838; CHECK: # %bb.0:839; CHECK-NEXT: csrr a0, vlenb840; CHECK-NEXT: srli a1, a0, 2841; CHECK-NEXT: sub a0, a0, a1842; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma843; CHECK-NEXT: vfmv.s.f v10, fa0844; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma845; CHECK-NEXT: vfredosum.vs v10, v8, v10846; CHECK-NEXT: vfmv.f.s fa0, v10847; CHECK-NEXT: ret848 %red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)849 ret half %red850}851 852define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) {853; CHECK-LABEL: vreduce_ord_fadd_nxv10f16:854; CHECK: # %bb.0:855; CHECK-NEXT: csrr a0, vlenb856; CHECK-NEXT: srli a1, a0, 2857; CHECK-NEXT: add a0, a0, a1858; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma859; CHECK-NEXT: vfmv.s.f v12, fa0860; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma861; CHECK-NEXT: vfredosum.vs v12, v8, v12862; CHECK-NEXT: vfmv.f.s fa0, v12863; CHECK-NEXT: ret864 %red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v)865 ret half %red866}867 868define half @vreduce_ord_fadd_nxv12f16(<vscale x 12 x half> %v, half %s) {869; CHECK-LABEL: vreduce_ord_fadd_nxv12f16:870; CHECK: # %bb.0:871; CHECK-NEXT: csrr a0, vlenb872; CHECK-NEXT: srli a1, a0, 1873; CHECK-NEXT: add a0, a0, a1874; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma875; CHECK-NEXT: vfmv.s.f v12, fa0876; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma877; CHECK-NEXT: vfredosum.vs v12, v8, v12878; CHECK-NEXT: vfmv.f.s fa0, v12879; CHECK-NEXT: ret880 %red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v)881 ret half %red882}883 884; Test Widen vector reduce type (fadd/fmin/fmax)885define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {886; CHECK-LABEL: vreduce_fadd_nxv3f16:887; CHECK: # %bb.0:888; CHECK-NEXT: csrr a0, vlenb889; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma890; CHECK-NEXT: vfmv.s.f v9, fa0891; CHECK-NEXT: srli a1, a0, 3892; CHECK-NEXT: srli a0, a0, 2893; CHECK-NEXT: add a0, a0, a1894; CHECK-NEXT: lui a1, 1048568895; CHECK-NEXT: vmv.s.x v10, a1896; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma897; CHECK-NEXT: vfredusum.vs v10, v8, v9898; CHECK-NEXT: vfmv.f.s fa0, v10899; CHECK-NEXT: ret900 %red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)901 ret half %red902}903 904define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {905; CHECK-LABEL: vreduce_fadd_nxv6f16:906; CHECK: # %bb.0:907; CHECK-NEXT: csrr a0, vlenb908; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma909; CHECK-NEXT: vfmv.s.f v10, fa0910; CHECK-NEXT: srli a1, a0, 2911; CHECK-NEXT: sub a0, a0, a1912; CHECK-NEXT: lui a1, 1048568913; CHECK-NEXT: vmv.s.x v11, a1914; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma915; CHECK-NEXT: vfredusum.vs v11, v8, v10916; CHECK-NEXT: vfmv.f.s fa0, v11917; CHECK-NEXT: ret918 %red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)919 ret half %red920}921 922define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) {923; CHECK-LABEL: vreduce_fmin_nxv10f16:924; CHECK: # %bb.0:925; CHECK-NEXT: csrr a0, vlenb926; CHECK-NEXT: srli a1, a0, 2927; CHECK-NEXT: add a0, a0, a1928; CHECK-NEXT: lui a1, 8929; CHECK-NEXT: addi a1, a1, -512930; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma931; CHECK-NEXT: vmv.s.x v12, a1932; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma933; CHECK-NEXT: vfredmin.vs v12, v8, v12934; CHECK-NEXT: vfmv.f.s fa0, v12935; CHECK-NEXT: ret936 %red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v)937 ret half %red938}939 940define half @vreduce_fmax_nxv12f16(<vscale x 12 x half> %v) {941; CHECK-LABEL: vreduce_fmax_nxv12f16:942; CHECK: # %bb.0:943; CHECK-NEXT: csrr a0, vlenb944; CHECK-NEXT: srli a1, a0, 1945; CHECK-NEXT: add a0, a0, a1946; CHECK-NEXT: li a1, -512947; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma948; CHECK-NEXT: vmv.s.x v12, a1949; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma950; CHECK-NEXT: vfredmax.vs v12, v8, v12951; CHECK-NEXT: vfmv.f.s fa0, v12952; CHECK-NEXT: ret953 %red = call half @llvm.vector.reduce.fmax.nxv12f16(<vscale x 12 x half> %v)954 ret half %red955}956