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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN10 11define half @vpreduce_fmin_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {12; ZVFH-LABEL: vpreduce_fmin_nxv4f16:13; ZVFH: # %bb.0:14; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma15; ZVFH-NEXT: vfmv.s.f v9, fa016; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma17; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t18; ZVFH-NEXT: vfmv.f.s fa0, v919; ZVFH-NEXT: ret20;21; ZVFHMIN-LABEL: vpreduce_fmin_nxv4f16:22; ZVFHMIN: # %bb.0:23; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma24; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v825; ZVFHMIN-NEXT: fcvt.s.h fa5, fa026; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma27; ZVFHMIN-NEXT: vfmv.s.f v8, fa528; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma29; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t30; ZVFHMIN-NEXT: vfmv.f.s fa5, v831; ZVFHMIN-NEXT: fcvt.h.s fa0, fa532; ZVFHMIN-NEXT: ret33 %s = call half @llvm.vp.reduce.fmin.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)34 ret half %s35}36 37define half @vpreduce_fmax_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {38; ZVFH-LABEL: vpreduce_fmax_nxv4f16:39; ZVFH: # %bb.0:40; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma41; ZVFH-NEXT: vfmv.s.f v9, fa042; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma43; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t44; ZVFH-NEXT: vfmv.f.s fa0, v945; ZVFH-NEXT: ret46;47; ZVFHMIN-LABEL: vpreduce_fmax_nxv4f16:48; ZVFHMIN: # %bb.0:49; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma50; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v851; ZVFHMIN-NEXT: fcvt.s.h fa5, fa052; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma53; ZVFHMIN-NEXT: vfmv.s.f v8, fa554; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma55; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t56; ZVFHMIN-NEXT: vfmv.f.s fa5, v857; ZVFHMIN-NEXT: fcvt.h.s fa0, fa558; ZVFHMIN-NEXT: ret59 %s = call half @llvm.vp.reduce.fmax.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)60 ret half %s61}62 63define half @vpreduce_fmin_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {64; ZVFH-LABEL: vpreduce_fmin_nnan_nxv4f16:65; ZVFH: # %bb.0:66; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma67; ZVFH-NEXT: vfmv.s.f v9, fa068; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma69; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t70; ZVFH-NEXT: vfmv.f.s fa0, v971; ZVFH-NEXT: ret72;73; ZVFHMIN-LABEL: vpreduce_fmin_nnan_nxv4f16:74; ZVFHMIN: # %bb.0:75; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma76; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v877; ZVFHMIN-NEXT: fcvt.s.h fa5, fa078; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma79; ZVFHMIN-NEXT: vfmv.s.f v8, fa580; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma81; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t82; ZVFHMIN-NEXT: vfmv.f.s fa5, v883; ZVFHMIN-NEXT: fcvt.h.s fa0, fa584; ZVFHMIN-NEXT: ret85 %s = call nnan half @llvm.vp.reduce.fmin.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)86 ret half %s87}88 89define half @vpreduce_fmax_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {90; ZVFH-LABEL: vpreduce_fmax_nnan_nxv4f16:91; ZVFH: # %bb.0:92; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma93; ZVFH-NEXT: vfmv.s.f v9, fa094; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma95; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t96; ZVFH-NEXT: vfmv.f.s fa0, v997; ZVFH-NEXT: ret98;99; ZVFHMIN-LABEL: vpreduce_fmax_nnan_nxv4f16:100; ZVFHMIN: # %bb.0:101; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma102; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8103; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0104; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma105; ZVFHMIN-NEXT: vfmv.s.f v8, fa5106; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma107; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t108; ZVFHMIN-NEXT: vfmv.f.s fa5, v8109; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5110; ZVFHMIN-NEXT: ret111 %s = call nnan half @llvm.vp.reduce.fmax.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)112 ret half %s113}114 115define half @vpreduce_fminimum_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {116; ZVFH-LABEL: vpreduce_fminimum_nxv4f16:117; ZVFH: # %bb.0:118; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma119; ZVFH-NEXT: vmfne.vv v9, v8, v8, v0.t120; ZVFH-NEXT: fcvt.s.h fa5, fa0121; ZVFH-NEXT: vcpop.m a1, v9, v0.t122; ZVFH-NEXT: feq.s a2, fa5, fa5123; ZVFH-NEXT: xori a2, a2, 1124; ZVFH-NEXT: or a1, a1, a2125; ZVFH-NEXT: beqz a1, .LBB4_2126; ZVFH-NEXT: # %bb.1:127; ZVFH-NEXT: lui a0, 8128; ZVFH-NEXT: addi a0, a0, -512129; ZVFH-NEXT: fmv.h.x fa0, a0130; ZVFH-NEXT: ret131; ZVFH-NEXT: .LBB4_2:132; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma133; ZVFH-NEXT: vfmv.s.f v9, fa0134; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma135; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t136; ZVFH-NEXT: vfmv.f.s fa0, v9137; ZVFH-NEXT: ret138;139; ZVFHMIN-LABEL: vpreduce_fminimum_nxv4f16:140; ZVFHMIN: # %bb.0:141; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma142; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8143; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0144; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma145; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t146; ZVFHMIN-NEXT: feq.s a1, fa5, fa5147; ZVFHMIN-NEXT: vcpop.m a2, v8, v0.t148; ZVFHMIN-NEXT: xori a1, a1, 1149; ZVFHMIN-NEXT: or a1, a2, a1150; ZVFHMIN-NEXT: beqz a1, .LBB4_2151; ZVFHMIN-NEXT: # %bb.1:152; ZVFHMIN-NEXT: lui a0, 523264153; ZVFHMIN-NEXT: fmv.w.x fa5, a0154; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5155; ZVFHMIN-NEXT: ret156; ZVFHMIN-NEXT: .LBB4_2:157; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma158; ZVFHMIN-NEXT: vfmv.s.f v8, fa5159; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma160; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t161; ZVFHMIN-NEXT: vfmv.f.s fa5, v8162; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5163; ZVFHMIN-NEXT: ret164 %s = call half @llvm.vp.reduce.fminimum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)165 ret half %s166}167 168define half @vpreduce_fmaximum_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {169; ZVFH-LABEL: vpreduce_fmaximum_nxv4f16:170; ZVFH: # %bb.0:171; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma172; ZVFH-NEXT: vmfne.vv v9, v8, v8, v0.t173; ZVFH-NEXT: fcvt.s.h fa5, fa0174; ZVFH-NEXT: vcpop.m a1, v9, v0.t175; ZVFH-NEXT: feq.s a2, fa5, fa5176; ZVFH-NEXT: xori a2, a2, 1177; ZVFH-NEXT: or a1, a1, a2178; ZVFH-NEXT: beqz a1, .LBB5_2179; ZVFH-NEXT: # %bb.1:180; ZVFH-NEXT: lui a0, 8181; ZVFH-NEXT: addi a0, a0, -512182; ZVFH-NEXT: fmv.h.x fa0, a0183; ZVFH-NEXT: ret184; ZVFH-NEXT: .LBB5_2:185; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma186; ZVFH-NEXT: vfmv.s.f v9, fa0187; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma188; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t189; ZVFH-NEXT: vfmv.f.s fa0, v9190; ZVFH-NEXT: ret191;192; ZVFHMIN-LABEL: vpreduce_fmaximum_nxv4f16:193; ZVFHMIN: # %bb.0:194; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma195; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8196; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0197; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma198; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10, v0.t199; ZVFHMIN-NEXT: feq.s a1, fa5, fa5200; ZVFHMIN-NEXT: vcpop.m a2, v8, v0.t201; ZVFHMIN-NEXT: xori a1, a1, 1202; ZVFHMIN-NEXT: or a1, a2, a1203; ZVFHMIN-NEXT: beqz a1, .LBB5_2204; ZVFHMIN-NEXT: # %bb.1:205; ZVFHMIN-NEXT: lui a0, 523264206; ZVFHMIN-NEXT: fmv.w.x fa5, a0207; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5208; ZVFHMIN-NEXT: ret209; ZVFHMIN-NEXT: .LBB5_2:210; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma211; ZVFHMIN-NEXT: vfmv.s.f v8, fa5212; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma213; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t214; ZVFHMIN-NEXT: vfmv.f.s fa5, v8215; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5216; ZVFHMIN-NEXT: ret217 %s = call half @llvm.vp.reduce.fmaximum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)218 ret half %s219}220 221define half @vpreduce_fminimum_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {222; ZVFH-LABEL: vpreduce_fminimum_nnan_nxv4f16:223; ZVFH: # %bb.0:224; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma225; ZVFH-NEXT: vfmv.s.f v9, fa0226; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma227; ZVFH-NEXT: vfredmin.vs v9, v8, v9, v0.t228; ZVFH-NEXT: vfmv.f.s fa0, v9229; ZVFH-NEXT: ret230;231; ZVFHMIN-LABEL: vpreduce_fminimum_nnan_nxv4f16:232; ZVFHMIN: # %bb.0:233; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma234; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8235; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0236; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma237; ZVFHMIN-NEXT: vfmv.s.f v8, fa5238; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma239; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v8, v0.t240; ZVFHMIN-NEXT: vfmv.f.s fa5, v8241; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5242; ZVFHMIN-NEXT: ret243 %s = call nnan half @llvm.vp.reduce.fminimum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)244 ret half %s245}246 247define half @vpreduce_fmaximum_nnan_nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {248; ZVFH-LABEL: vpreduce_fmaximum_nnan_nxv4f16:249; ZVFH: # %bb.0:250; ZVFH-NEXT: vsetivli zero, 1, e16, m1, ta, ma251; ZVFH-NEXT: vfmv.s.f v9, fa0252; ZVFH-NEXT: vsetvli zero, a0, e16, m1, ta, ma253; ZVFH-NEXT: vfredmax.vs v9, v8, v9, v0.t254; ZVFH-NEXT: vfmv.f.s fa0, v9255; ZVFH-NEXT: ret256;257; ZVFHMIN-LABEL: vpreduce_fmaximum_nnan_nxv4f16:258; ZVFHMIN: # %bb.0:259; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma260; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8261; ZVFHMIN-NEXT: fcvt.s.h fa5, fa0262; ZVFHMIN-NEXT: vsetivli zero, 1, e32, m2, ta, ma263; ZVFHMIN-NEXT: vfmv.s.f v8, fa5264; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m2, ta, ma265; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v8, v0.t266; ZVFHMIN-NEXT: vfmv.f.s fa5, v8267; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5268; ZVFHMIN-NEXT: ret269 %s = call nnan half @llvm.vp.reduce.fmaximum.nxv4f16(half %start, <vscale x 4 x half> %val, <vscale x 4 x i1> %m, i32 %evl)270 ret half %s271}272