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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define half @vpreduce_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpreduce_fadd_nxv1f16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma11; CHECK-NEXT: vfmv.s.f v9, fa012; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma13; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t14; CHECK-NEXT: vfmv.f.s fa0, v915; CHECK-NEXT: ret16 %r = call reassoc half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)17 ret half %r18}19 20define half @vpreduce_ord_fadd_nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {21; CHECK-LABEL: vpreduce_ord_fadd_nxv1f16:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma24; CHECK-NEXT: vfmv.s.f v9, fa025; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma26; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t27; CHECK-NEXT: vfmv.f.s fa0, v928; CHECK-NEXT: ret29 %r = call half @llvm.vp.reduce.fadd.nxv1f16(half %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)30 ret half %r31}32 33define half @vpreduce_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vpreduce_fadd_nxv2f16:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma37; CHECK-NEXT: vfmv.s.f v9, fa038; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma39; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t40; CHECK-NEXT: vfmv.f.s fa0, v941; CHECK-NEXT: ret42 %r = call reassoc half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)43 ret half %r44}45 46define half @vpreduce_ord_fadd_nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vpreduce_ord_fadd_nxv2f16:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma50; CHECK-NEXT: vfmv.s.f v9, fa051; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma52; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t53; CHECK-NEXT: vfmv.f.s fa0, v954; CHECK-NEXT: ret55 %r = call half @llvm.vp.reduce.fadd.nxv2f16(half %s, <vscale x 2 x half> %v, <vscale x 2 x i1> %m, i32 %evl)56 ret half %r57}58 59define half @vpreduce_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: vpreduce_fadd_nxv4f16:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma63; CHECK-NEXT: vfmv.s.f v9, fa064; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma65; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t66; CHECK-NEXT: vfmv.f.s fa0, v967; CHECK-NEXT: ret68 %r = call reassoc half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)69 ret half %r70}71 72define half @vpreduce_ord_fadd_nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {73; CHECK-LABEL: vpreduce_ord_fadd_nxv4f16:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma76; CHECK-NEXT: vfmv.s.f v9, fa077; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma78; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t79; CHECK-NEXT: vfmv.f.s fa0, v980; CHECK-NEXT: ret81 %r = call half @llvm.vp.reduce.fadd.nxv4f16(half %s, <vscale x 4 x half> %v, <vscale x 4 x i1> %m, i32 %evl)82 ret half %r83}84 85define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vpreduce_fadd_nxv64f16:87; CHECK: # %bb.0:88; CHECK-NEXT: csrr a2, vlenb89; CHECK-NEXT: srli a1, a2, 190; CHECK-NEXT: slli a2, a2, 291; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma92; CHECK-NEXT: vslidedown.vx v24, v0, a193; CHECK-NEXT: sub a1, a0, a294; CHECK-NEXT: sltu a3, a0, a195; CHECK-NEXT: addi a3, a3, -196; CHECK-NEXT: and a1, a3, a197; CHECK-NEXT: bltu a0, a2, .LBB6_298; CHECK-NEXT: # %bb.1:99; CHECK-NEXT: mv a0, a2100; CHECK-NEXT: .LBB6_2:101; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma102; CHECK-NEXT: vfmv.s.f v25, fa0103; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma104; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t105; CHECK-NEXT: vmv1r.v v0, v24106; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma107; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t108; CHECK-NEXT: vfmv.f.s fa0, v25109; CHECK-NEXT: ret110 %r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)111 ret half %r112}113 114define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {115; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:116; CHECK: # %bb.0:117; CHECK-NEXT: csrr a2, vlenb118; CHECK-NEXT: srli a1, a2, 1119; CHECK-NEXT: slli a2, a2, 2120; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma121; CHECK-NEXT: vslidedown.vx v24, v0, a1122; CHECK-NEXT: sub a1, a0, a2123; CHECK-NEXT: sltu a3, a0, a1124; CHECK-NEXT: addi a3, a3, -1125; CHECK-NEXT: and a1, a3, a1126; CHECK-NEXT: bltu a0, a2, .LBB7_2127; CHECK-NEXT: # %bb.1:128; CHECK-NEXT: mv a0, a2129; CHECK-NEXT: .LBB7_2:130; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma131; CHECK-NEXT: vfmv.s.f v25, fa0132; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma133; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t134; CHECK-NEXT: vmv1r.v v0, v24135; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma136; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t137; CHECK-NEXT: vfmv.f.s fa0, v25138; CHECK-NEXT: ret139 %r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)140 ret half %r141}142 143define float @vpreduce_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {144; CHECK-LABEL: vpreduce_fadd_nxv1f32:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma147; CHECK-NEXT: vfmv.s.f v9, fa0148; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma149; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t150; CHECK-NEXT: vfmv.f.s fa0, v9151; CHECK-NEXT: ret152 %r = call reassoc float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)153 ret float %r154}155 156define float @vpreduce_ord_fadd_nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {157; CHECK-LABEL: vpreduce_ord_fadd_nxv1f32:158; CHECK: # %bb.0:159; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma160; CHECK-NEXT: vfmv.s.f v9, fa0161; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma162; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t163; CHECK-NEXT: vfmv.f.s fa0, v9164; CHECK-NEXT: ret165 %r = call float @llvm.vp.reduce.fadd.nxv1f32(float %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)166 ret float %r167}168 169define float @vpreduce_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {170; CHECK-LABEL: vpreduce_fadd_nxv2f32:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma173; CHECK-NEXT: vfmv.s.f v9, fa0174; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma175; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t176; CHECK-NEXT: vfmv.f.s fa0, v9177; CHECK-NEXT: ret178 %r = call reassoc float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)179 ret float %r180}181 182define float @vpreduce_ord_fadd_nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {183; CHECK-LABEL: vpreduce_ord_fadd_nxv2f32:184; CHECK: # %bb.0:185; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma186; CHECK-NEXT: vfmv.s.f v9, fa0187; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma188; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t189; CHECK-NEXT: vfmv.f.s fa0, v9190; CHECK-NEXT: ret191 %r = call float @llvm.vp.reduce.fadd.nxv2f32(float %s, <vscale x 2 x float> %v, <vscale x 2 x i1> %m, i32 %evl)192 ret float %r193}194 195define float @vpreduce_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {196; CHECK-LABEL: vpreduce_fadd_nxv4f32:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma199; CHECK-NEXT: vfmv.s.f v10, fa0200; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma201; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t202; CHECK-NEXT: vfmv.f.s fa0, v10203; CHECK-NEXT: ret204 %r = call reassoc float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)205 ret float %r206}207 208define float @vpreduce_ord_fadd_nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {209; CHECK-LABEL: vpreduce_ord_fadd_nxv4f32:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma212; CHECK-NEXT: vfmv.s.f v10, fa0213; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma214; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t215; CHECK-NEXT: vfmv.f.s fa0, v10216; CHECK-NEXT: ret217 %r = call float @llvm.vp.reduce.fadd.nxv4f32(float %s, <vscale x 4 x float> %v, <vscale x 4 x i1> %m, i32 %evl)218 ret float %r219}220 221define double @vpreduce_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {222; CHECK-LABEL: vpreduce_fadd_nxv1f64:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma225; CHECK-NEXT: vfmv.s.f v9, fa0226; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma227; CHECK-NEXT: vfredusum.vs v9, v8, v9, v0.t228; CHECK-NEXT: vfmv.f.s fa0, v9229; CHECK-NEXT: ret230 %r = call reassoc double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)231 ret double %r232}233 234define double @vpreduce_ord_fadd_nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {235; CHECK-LABEL: vpreduce_ord_fadd_nxv1f64:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma238; CHECK-NEXT: vfmv.s.f v9, fa0239; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma240; CHECK-NEXT: vfredosum.vs v9, v8, v9, v0.t241; CHECK-NEXT: vfmv.f.s fa0, v9242; CHECK-NEXT: ret243 %r = call double @llvm.vp.reduce.fadd.nxv1f64(double %s, <vscale x 1 x double> %v, <vscale x 1 x i1> %m, i32 %evl)244 ret double %r245}246 247define double @vpreduce_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {248; CHECK-LABEL: vpreduce_fadd_nxv2f64:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma251; CHECK-NEXT: vfmv.s.f v10, fa0252; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma253; CHECK-NEXT: vfredusum.vs v10, v8, v10, v0.t254; CHECK-NEXT: vfmv.f.s fa0, v10255; CHECK-NEXT: ret256 %r = call reassoc double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)257 ret double %r258}259 260define double @vpreduce_ord_fadd_nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {261; CHECK-LABEL: vpreduce_ord_fadd_nxv2f64:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma264; CHECK-NEXT: vfmv.s.f v10, fa0265; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma266; CHECK-NEXT: vfredosum.vs v10, v8, v10, v0.t267; CHECK-NEXT: vfmv.f.s fa0, v10268; CHECK-NEXT: ret269 %r = call double @llvm.vp.reduce.fadd.nxv2f64(double %s, <vscale x 2 x double> %v, <vscale x 2 x i1> %m, i32 %evl)270 ret double %r271}272 273define double @vpreduce_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {274; CHECK-LABEL: vpreduce_fadd_nxv3f64:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma277; CHECK-NEXT: vfmv.s.f v12, fa0278; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma279; CHECK-NEXT: vfredusum.vs v12, v8, v12, v0.t280; CHECK-NEXT: vfmv.f.s fa0, v12281; CHECK-NEXT: ret282 %r = call reassoc double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)283 ret double %r284}285 286define double @vpreduce_ord_fadd_nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {287; CHECK-LABEL: vpreduce_ord_fadd_nxv3f64:288; CHECK: # %bb.0:289; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma290; CHECK-NEXT: vfmv.s.f v12, fa0291; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma292; CHECK-NEXT: vfredosum.vs v12, v8, v12, v0.t293; CHECK-NEXT: vfmv.f.s fa0, v12294; CHECK-NEXT: ret295 %r = call double @llvm.vp.reduce.fadd.nxv3f64(double %s, <vscale x 3 x double> %v, <vscale x 3 x i1> %m, i32 %evl)296 ret double %r297}298 299define double @vpreduce_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: vpreduce_fadd_nxv4f64:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma303; CHECK-NEXT: vfmv.s.f v12, fa0304; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma305; CHECK-NEXT: vfredusum.vs v12, v8, v12, v0.t306; CHECK-NEXT: vfmv.f.s fa0, v12307; CHECK-NEXT: ret308 %r = call reassoc double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)309 ret double %r310}311 312define double @vpreduce_ord_fadd_nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {313; CHECK-LABEL: vpreduce_ord_fadd_nxv4f64:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma316; CHECK-NEXT: vfmv.s.f v12, fa0317; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma318; CHECK-NEXT: vfredosum.vs v12, v8, v12, v0.t319; CHECK-NEXT: vfmv.f.s fa0, v12320; CHECK-NEXT: ret321 %r = call double @llvm.vp.reduce.fadd.nxv4f64(double %s, <vscale x 4 x double> %v, <vscale x 4 x i1> %m, i32 %evl)322 ret double %r323}324 325define float @vpreduce_fminimum_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {326; CHECK-LABEL: vpreduce_fminimum_nxv4f32:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma329; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t330; CHECK-NEXT: feq.s a1, fa0, fa0331; CHECK-NEXT: vcpop.m a2, v10, v0.t332; CHECK-NEXT: xori a1, a1, 1333; CHECK-NEXT: or a1, a2, a1334; CHECK-NEXT: beqz a1, .LBB22_2335; CHECK-NEXT: # %bb.1:336; CHECK-NEXT: lui a0, 523264337; CHECK-NEXT: fmv.w.x fa0, a0338; CHECK-NEXT: ret339; CHECK-NEXT: .LBB22_2:340; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma341; CHECK-NEXT: vfmv.s.f v10, fa0342; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma343; CHECK-NEXT: vfredmin.vs v10, v8, v10, v0.t344; CHECK-NEXT: vfmv.f.s fa0, v10345; CHECK-NEXT: ret346 %s = call float @llvm.vp.reduce.fminimum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)347 ret float %s348}349 350define float @vpreduce_fmaximum_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {351; CHECK-LABEL: vpreduce_fmaximum_nxv4f32:352; CHECK: # %bb.0:353; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma354; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t355; CHECK-NEXT: feq.s a1, fa0, fa0356; CHECK-NEXT: vcpop.m a2, v10, v0.t357; CHECK-NEXT: xori a1, a1, 1358; CHECK-NEXT: or a1, a2, a1359; CHECK-NEXT: beqz a1, .LBB23_2360; CHECK-NEXT: # %bb.1:361; CHECK-NEXT: lui a0, 523264362; CHECK-NEXT: fmv.w.x fa0, a0363; CHECK-NEXT: ret364; CHECK-NEXT: .LBB23_2:365; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma366; CHECK-NEXT: vfmv.s.f v10, fa0367; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma368; CHECK-NEXT: vfredmax.vs v10, v8, v10, v0.t369; CHECK-NEXT: vfmv.f.s fa0, v10370; CHECK-NEXT: ret371 %s = call float @llvm.vp.reduce.fmaximum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)372 ret float %s373}374 375define float @vpreduce_fminimum_nnan_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {376; CHECK-LABEL: vpreduce_fminimum_nnan_nxv4f32:377; CHECK: # %bb.0:378; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma379; CHECK-NEXT: vfmv.s.f v10, fa0380; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma381; CHECK-NEXT: vfredmin.vs v10, v8, v10, v0.t382; CHECK-NEXT: vfmv.f.s fa0, v10383; CHECK-NEXT: ret384 %s = call nnan float @llvm.vp.reduce.fminimum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)385 ret float %s386}387 388define float @vpreduce_fmaximum_nnan_nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {389; CHECK-LABEL: vpreduce_fmaximum_nnan_nxv4f32:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma392; CHECK-NEXT: vfmv.s.f v10, fa0393; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma394; CHECK-NEXT: vfredmax.vs v10, v8, v10, v0.t395; CHECK-NEXT: vfmv.f.s fa0, v10396; CHECK-NEXT: ret397 %s = call nnan float @llvm.vp.reduce.fmaximum.nxv4f32(float %start, <vscale x 4 x float> %val, <vscale x 4 x i1> %m, i32 %evl)398 ret float %s399}400 401define float @vpreduce_fadd_fpext_vp_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {402; CHECK-LABEL: vpreduce_fadd_fpext_vp_nxv1f16_nxv1f32:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma405; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t406; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma407; CHECK-NEXT: vfmv.s.f v8, fa0408; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma409; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t410; CHECK-NEXT: vfmv.f.s fa0, v8411; CHECK-NEXT: ret412 %w = call <vscale x 1 x float> @llvm.vp.fpext(<vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)413 %r = call reassoc float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)414 ret float %r415}416 417define float @vpreduce_ord_fadd_fpext_vp_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {418; CHECK-LABEL: vpreduce_ord_fadd_fpext_vp_fpext_nxv1f16_nxv1f32:419; CHECK: # %bb.0:420; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma421; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t422; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma423; CHECK-NEXT: vfmv.s.f v8, fa0424; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma425; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t426; CHECK-NEXT: vfmv.f.s fa0, v8427; CHECK-NEXT: ret428 %w = call <vscale x 1 x float> @llvm.vp.fpext(<vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 %evl)429 %r = call float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)430 ret float %r431}432 433define double @vpreduce_fadd_fpext_vp_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {434; CHECK-LABEL: vpreduce_fadd_fpext_vp_nxv1f32_nxv1f64:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma437; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t438; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma439; CHECK-NEXT: vfmv.s.f v8, fa0440; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma441; CHECK-NEXT: vfredusum.vs v8, v9, v8, v0.t442; CHECK-NEXT: vfmv.f.s fa0, v8443; CHECK-NEXT: ret444 %w = call <vscale x 1 x double> @llvm.vp.fpext(<vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)445 %r = call reassoc double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)446 ret double %r447}448 449define double @vpreduce_ord_fadd_fpext_vp_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {450; CHECK-LABEL: vpreduce_ord_fadd_fpext_vp_fpext_nxv1f32_nxv1f64:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma453; CHECK-NEXT: vfwcvt.f.f.v v9, v8, v0.t454; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma455; CHECK-NEXT: vfmv.s.f v8, fa0456; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma457; CHECK-NEXT: vfredosum.vs v8, v9, v8, v0.t458; CHECK-NEXT: vfmv.f.s fa0, v8459; CHECK-NEXT: ret460 %w = call <vscale x 1 x double> @llvm.vp.fpext(<vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 %evl)461 %r = call double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)462 ret double %r463}464 465define float @vpreduce_fadd_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {466; CHECK-LABEL: vpreduce_fadd_fpext_nxv1f16_nxv1f32:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma469; CHECK-NEXT: vfmv.s.f v9, fa0470; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma471; CHECK-NEXT: vfwredusum.vs v9, v8, v9, v0.t472; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma473; CHECK-NEXT: vfmv.f.s fa0, v9474; CHECK-NEXT: ret475 %w = fpext <vscale x 1 x half> %v to <vscale x 1 x float>476 %r = call reassoc float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)477 ret float %r478}479 480define float @vpreduce_ord_fadd_fpext_nxv1f16_nxv1f32(float %s, <vscale x 1 x half> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {481; CHECK-LABEL: vpreduce_ord_fadd_fpext_nxv1f16_nxv1f32:482; CHECK: # %bb.0:483; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma484; CHECK-NEXT: vfmv.s.f v9, fa0485; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma486; CHECK-NEXT: vfwredosum.vs v9, v8, v9, v0.t487; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma488; CHECK-NEXT: vfmv.f.s fa0, v9489; CHECK-NEXT: ret490 %w = fpext <vscale x 1 x half> %v to <vscale x 1 x float>491 %r = call float @llvm.vp.reduce.fadd(float %s, <vscale x 1 x float> %w, <vscale x 1 x i1> %m, i32 %evl)492 ret float %r493}494 495define double @vpreduce_fadd_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {496; CHECK-LABEL: vpreduce_fadd_fpext_nxv1f32_nxv1f64:497; CHECK: # %bb.0:498; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma499; CHECK-NEXT: vfmv.s.f v9, fa0500; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma501; CHECK-NEXT: vfwredusum.vs v9, v8, v9, v0.t502; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma503; CHECK-NEXT: vfmv.f.s fa0, v9504; CHECK-NEXT: ret505 %w = fpext <vscale x 1 x float> %v to <vscale x 1 x double>506 %r = call reassoc double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)507 ret double %r508}509 510define double @vpreduce_ord_fadd_fpext_nxv1f32_nxv1f64(double %s, <vscale x 1 x float> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {511; CHECK-LABEL: vpreduce_ord_fadd_fpext_nxv1f32_nxv1f64:512; CHECK: # %bb.0:513; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma514; CHECK-NEXT: vfmv.s.f v9, fa0515; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma516; CHECK-NEXT: vfwredosum.vs v9, v8, v9, v0.t517; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma518; CHECK-NEXT: vfmv.f.s fa0, v9519; CHECK-NEXT: ret520 %w = fpext <vscale x 1 x float> %v to <vscale x 1 x double>521 %r = call double @llvm.vp.reduce.fadd(double %s, <vscale x 1 x double> %w, <vscale x 1 x i1> %m, i32 %evl)522 ret double %r523}524