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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define signext i8 @vpreduce_add_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {8; CHECK-LABEL: vpreduce_add_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma11; CHECK-NEXT: vmv.s.x v9, a012; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma13; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t14; CHECK-NEXT: vmv.x.s a0, v915; CHECK-NEXT: ret16 %r = call i8 @llvm.vp.reduce.add.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)17 ret i8 %r18}19 20define signext i8 @vpreduce_umax_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {21; CHECK-LABEL: vpreduce_umax_nxv1i8:22; CHECK: # %bb.0:23; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma24; CHECK-NEXT: vmv.s.x v9, a025; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma26; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t27; CHECK-NEXT: vmv.x.s a0, v928; CHECK-NEXT: ret29 %r = call i8 @llvm.vp.reduce.umax.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)30 ret i8 %r31}32 33define signext i8 @vpreduce_smax_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vpreduce_smax_nxv1i8:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma37; CHECK-NEXT: vmv.s.x v9, a038; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma39; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t40; CHECK-NEXT: vmv.x.s a0, v941; CHECK-NEXT: ret42 %r = call i8 @llvm.vp.reduce.smax.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)43 ret i8 %r44}45 46define signext i8 @vpreduce_umin_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {47; CHECK-LABEL: vpreduce_umin_nxv1i8:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma50; CHECK-NEXT: vmv.s.x v9, a051; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma52; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t53; CHECK-NEXT: vmv.x.s a0, v954; CHECK-NEXT: ret55 %r = call i8 @llvm.vp.reduce.umin.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)56 ret i8 %r57}58 59define signext i8 @vpreduce_smin_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {60; CHECK-LABEL: vpreduce_smin_nxv1i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma63; CHECK-NEXT: vmv.s.x v9, a064; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma65; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t66; CHECK-NEXT: vmv.x.s a0, v967; CHECK-NEXT: ret68 %r = call i8 @llvm.vp.reduce.smin.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)69 ret i8 %r70}71 72define signext i8 @vpreduce_and_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {73; CHECK-LABEL: vpreduce_and_nxv1i8:74; CHECK: # %bb.0:75; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma76; CHECK-NEXT: vmv.s.x v9, a077; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma78; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t79; CHECK-NEXT: vmv.x.s a0, v980; CHECK-NEXT: ret81 %r = call i8 @llvm.vp.reduce.and.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)82 ret i8 %r83}84 85define signext i8 @vpreduce_or_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {86; CHECK-LABEL: vpreduce_or_nxv1i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma89; CHECK-NEXT: vmv.s.x v9, a090; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma91; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t92; CHECK-NEXT: vmv.x.s a0, v993; CHECK-NEXT: ret94 %r = call i8 @llvm.vp.reduce.or.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)95 ret i8 %r96}97 98define signext i8 @vpreduce_xor_nxv1i8(i8 signext %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {99; CHECK-LABEL: vpreduce_xor_nxv1i8:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma102; CHECK-NEXT: vmv.s.x v9, a0103; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma104; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t105; CHECK-NEXT: vmv.x.s a0, v9106; CHECK-NEXT: ret107 %r = call i8 @llvm.vp.reduce.xor.nxv1i8(i8 %s, <vscale x 1 x i8> %v, <vscale x 1 x i1> %m, i32 %evl)108 ret i8 %r109}110 111define signext i8 @vpreduce_add_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {112; CHECK-LABEL: vpreduce_add_nxv2i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma115; CHECK-NEXT: vmv.s.x v9, a0116; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma117; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t118; CHECK-NEXT: vmv.x.s a0, v9119; CHECK-NEXT: ret120 %r = call i8 @llvm.vp.reduce.add.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)121 ret i8 %r122}123 124define signext i8 @vpreduce_umax_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {125; CHECK-LABEL: vpreduce_umax_nxv2i8:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma128; CHECK-NEXT: vmv.s.x v9, a0129; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma130; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t131; CHECK-NEXT: vmv.x.s a0, v9132; CHECK-NEXT: ret133 %r = call i8 @llvm.vp.reduce.umax.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)134 ret i8 %r135}136 137define signext i8 @vpreduce_smax_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {138; CHECK-LABEL: vpreduce_smax_nxv2i8:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma141; CHECK-NEXT: vmv.s.x v9, a0142; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma143; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t144; CHECK-NEXT: vmv.x.s a0, v9145; CHECK-NEXT: ret146 %r = call i8 @llvm.vp.reduce.smax.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)147 ret i8 %r148}149 150define signext i8 @vpreduce_umin_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {151; CHECK-LABEL: vpreduce_umin_nxv2i8:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma154; CHECK-NEXT: vmv.s.x v9, a0155; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma156; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t157; CHECK-NEXT: vmv.x.s a0, v9158; CHECK-NEXT: ret159 %r = call i8 @llvm.vp.reduce.umin.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)160 ret i8 %r161}162 163define signext i8 @vpreduce_smin_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {164; CHECK-LABEL: vpreduce_smin_nxv2i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma167; CHECK-NEXT: vmv.s.x v9, a0168; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma169; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t170; CHECK-NEXT: vmv.x.s a0, v9171; CHECK-NEXT: ret172 %r = call i8 @llvm.vp.reduce.smin.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)173 ret i8 %r174}175 176define signext i8 @vpreduce_and_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {177; CHECK-LABEL: vpreduce_and_nxv2i8:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma180; CHECK-NEXT: vmv.s.x v9, a0181; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma182; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t183; CHECK-NEXT: vmv.x.s a0, v9184; CHECK-NEXT: ret185 %r = call i8 @llvm.vp.reduce.and.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)186 ret i8 %r187}188 189define signext i8 @vpreduce_or_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {190; CHECK-LABEL: vpreduce_or_nxv2i8:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma193; CHECK-NEXT: vmv.s.x v9, a0194; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma195; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t196; CHECK-NEXT: vmv.x.s a0, v9197; CHECK-NEXT: ret198 %r = call i8 @llvm.vp.reduce.or.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)199 ret i8 %r200}201 202define signext i8 @vpreduce_xor_nxv2i8(i8 signext %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {203; CHECK-LABEL: vpreduce_xor_nxv2i8:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma206; CHECK-NEXT: vmv.s.x v9, a0207; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma208; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t209; CHECK-NEXT: vmv.x.s a0, v9210; CHECK-NEXT: ret211 %r = call i8 @llvm.vp.reduce.xor.nxv2i8(i8 %s, <vscale x 2 x i8> %v, <vscale x 2 x i1> %m, i32 %evl)212 ret i8 %r213}214 215define signext i8 @vpreduce_smax_nxv3i8(i8 signext %s, <vscale x 3 x i8> %v, <vscale x 3 x i1> %m, i32 zeroext %evl) {216; CHECK-LABEL: vpreduce_smax_nxv3i8:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma219; CHECK-NEXT: vmv.s.x v9, a0220; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma221; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t222; CHECK-NEXT: vmv.x.s a0, v9223; CHECK-NEXT: ret224 %r = call i8 @llvm.vp.reduce.smax.nxv3i8(i8 %s, <vscale x 3 x i8> %v, <vscale x 3 x i1> %m, i32 %evl)225 ret i8 %r226}227 228define signext i8 @vpreduce_add_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {229; CHECK-LABEL: vpreduce_add_nxv4i8:230; CHECK: # %bb.0:231; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma232; CHECK-NEXT: vmv.s.x v9, a0233; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma234; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t235; CHECK-NEXT: vmv.x.s a0, v9236; CHECK-NEXT: ret237 %r = call i8 @llvm.vp.reduce.add.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)238 ret i8 %r239}240 241define signext i8 @vpreduce_umax_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {242; CHECK-LABEL: vpreduce_umax_nxv4i8:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma245; CHECK-NEXT: vmv.s.x v9, a0246; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma247; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t248; CHECK-NEXT: vmv.x.s a0, v9249; CHECK-NEXT: ret250 %r = call i8 @llvm.vp.reduce.umax.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)251 ret i8 %r252}253 254define signext i8 @vpreduce_smax_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {255; CHECK-LABEL: vpreduce_smax_nxv4i8:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma258; CHECK-NEXT: vmv.s.x v9, a0259; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma260; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t261; CHECK-NEXT: vmv.x.s a0, v9262; CHECK-NEXT: ret263 %r = call i8 @llvm.vp.reduce.smax.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)264 ret i8 %r265}266 267define signext i8 @vpreduce_umin_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {268; CHECK-LABEL: vpreduce_umin_nxv4i8:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma271; CHECK-NEXT: vmv.s.x v9, a0272; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma273; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t274; CHECK-NEXT: vmv.x.s a0, v9275; CHECK-NEXT: ret276 %r = call i8 @llvm.vp.reduce.umin.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)277 ret i8 %r278}279 280define signext i8 @vpreduce_smin_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {281; CHECK-LABEL: vpreduce_smin_nxv4i8:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma284; CHECK-NEXT: vmv.s.x v9, a0285; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma286; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t287; CHECK-NEXT: vmv.x.s a0, v9288; CHECK-NEXT: ret289 %r = call i8 @llvm.vp.reduce.smin.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)290 ret i8 %r291}292 293define signext i8 @vpreduce_and_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: vpreduce_and_nxv4i8:295; CHECK: # %bb.0:296; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma297; CHECK-NEXT: vmv.s.x v9, a0298; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma299; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t300; CHECK-NEXT: vmv.x.s a0, v9301; CHECK-NEXT: ret302 %r = call i8 @llvm.vp.reduce.and.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)303 ret i8 %r304}305 306define signext i8 @vpreduce_or_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {307; CHECK-LABEL: vpreduce_or_nxv4i8:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma310; CHECK-NEXT: vmv.s.x v9, a0311; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma312; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t313; CHECK-NEXT: vmv.x.s a0, v9314; CHECK-NEXT: ret315 %r = call i8 @llvm.vp.reduce.or.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)316 ret i8 %r317}318 319define signext i8 @vpreduce_xor_nxv4i8(i8 signext %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {320; CHECK-LABEL: vpreduce_xor_nxv4i8:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma323; CHECK-NEXT: vmv.s.x v9, a0324; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma325; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t326; CHECK-NEXT: vmv.x.s a0, v9327; CHECK-NEXT: ret328 %r = call i8 @llvm.vp.reduce.xor.nxv4i8(i8 %s, <vscale x 4 x i8> %v, <vscale x 4 x i1> %m, i32 %evl)329 ret i8 %r330}331 332define signext i16 @vpreduce_add_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {333; CHECK-LABEL: vpreduce_add_nxv1i16:334; CHECK: # %bb.0:335; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma336; CHECK-NEXT: vmv.s.x v9, a0337; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma338; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t339; CHECK-NEXT: vmv.x.s a0, v9340; CHECK-NEXT: ret341 %r = call i16 @llvm.vp.reduce.add.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)342 ret i16 %r343}344 345define signext i16 @vpreduce_umax_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {346; CHECK-LABEL: vpreduce_umax_nxv1i16:347; CHECK: # %bb.0:348; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma349; CHECK-NEXT: vmv.s.x v9, a0350; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma351; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t352; CHECK-NEXT: vmv.x.s a0, v9353; CHECK-NEXT: ret354 %r = call i16 @llvm.vp.reduce.umax.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)355 ret i16 %r356}357 358define signext i16 @vpreduce_smax_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {359; CHECK-LABEL: vpreduce_smax_nxv1i16:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma362; CHECK-NEXT: vmv.s.x v9, a0363; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma364; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t365; CHECK-NEXT: vmv.x.s a0, v9366; CHECK-NEXT: ret367 %r = call i16 @llvm.vp.reduce.smax.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)368 ret i16 %r369}370 371define signext i16 @vpreduce_umin_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vpreduce_umin_nxv1i16:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma375; CHECK-NEXT: vmv.s.x v9, a0376; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma377; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t378; CHECK-NEXT: vmv.x.s a0, v9379; CHECK-NEXT: ret380 %r = call i16 @llvm.vp.reduce.umin.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)381 ret i16 %r382}383 384define signext i16 @vpreduce_smin_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {385; CHECK-LABEL: vpreduce_smin_nxv1i16:386; CHECK: # %bb.0:387; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma388; CHECK-NEXT: vmv.s.x v9, a0389; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma390; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t391; CHECK-NEXT: vmv.x.s a0, v9392; CHECK-NEXT: ret393 %r = call i16 @llvm.vp.reduce.smin.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)394 ret i16 %r395}396 397define signext i16 @vpreduce_and_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {398; CHECK-LABEL: vpreduce_and_nxv1i16:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma401; CHECK-NEXT: vmv.s.x v9, a0402; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma403; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t404; CHECK-NEXT: vmv.x.s a0, v9405; CHECK-NEXT: ret406 %r = call i16 @llvm.vp.reduce.and.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)407 ret i16 %r408}409 410define signext i16 @vpreduce_or_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {411; CHECK-LABEL: vpreduce_or_nxv1i16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma414; CHECK-NEXT: vmv.s.x v9, a0415; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma416; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t417; CHECK-NEXT: vmv.x.s a0, v9418; CHECK-NEXT: ret419 %r = call i16 @llvm.vp.reduce.or.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)420 ret i16 %r421}422 423define signext i16 @vpreduce_xor_nxv1i16(i16 signext %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {424; CHECK-LABEL: vpreduce_xor_nxv1i16:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma427; CHECK-NEXT: vmv.s.x v9, a0428; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma429; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t430; CHECK-NEXT: vmv.x.s a0, v9431; CHECK-NEXT: ret432 %r = call i16 @llvm.vp.reduce.xor.nxv1i16(i16 %s, <vscale x 1 x i16> %v, <vscale x 1 x i1> %m, i32 %evl)433 ret i16 %r434}435 436define signext i16 @vpreduce_add_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {437; CHECK-LABEL: vpreduce_add_nxv2i16:438; CHECK: # %bb.0:439; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma440; CHECK-NEXT: vmv.s.x v9, a0441; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma442; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t443; CHECK-NEXT: vmv.x.s a0, v9444; CHECK-NEXT: ret445 %r = call i16 @llvm.vp.reduce.add.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)446 ret i16 %r447}448 449define signext i16 @vpreduce_umax_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {450; CHECK-LABEL: vpreduce_umax_nxv2i16:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma453; CHECK-NEXT: vmv.s.x v9, a0454; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma455; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t456; CHECK-NEXT: vmv.x.s a0, v9457; CHECK-NEXT: ret458 %r = call i16 @llvm.vp.reduce.umax.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)459 ret i16 %r460}461 462define signext i16 @vpreduce_smax_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {463; CHECK-LABEL: vpreduce_smax_nxv2i16:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma466; CHECK-NEXT: vmv.s.x v9, a0467; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma468; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t469; CHECK-NEXT: vmv.x.s a0, v9470; CHECK-NEXT: ret471 %r = call i16 @llvm.vp.reduce.smax.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)472 ret i16 %r473}474 475define signext i16 @vpreduce_umin_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {476; CHECK-LABEL: vpreduce_umin_nxv2i16:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma479; CHECK-NEXT: vmv.s.x v9, a0480; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma481; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t482; CHECK-NEXT: vmv.x.s a0, v9483; CHECK-NEXT: ret484 %r = call i16 @llvm.vp.reduce.umin.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)485 ret i16 %r486}487 488define signext i16 @vpreduce_smin_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {489; CHECK-LABEL: vpreduce_smin_nxv2i16:490; CHECK: # %bb.0:491; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma492; CHECK-NEXT: vmv.s.x v9, a0493; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma494; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t495; CHECK-NEXT: vmv.x.s a0, v9496; CHECK-NEXT: ret497 %r = call i16 @llvm.vp.reduce.smin.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)498 ret i16 %r499}500 501define signext i16 @vpreduce_and_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {502; CHECK-LABEL: vpreduce_and_nxv2i16:503; CHECK: # %bb.0:504; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma505; CHECK-NEXT: vmv.s.x v9, a0506; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma507; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t508; CHECK-NEXT: vmv.x.s a0, v9509; CHECK-NEXT: ret510 %r = call i16 @llvm.vp.reduce.and.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)511 ret i16 %r512}513 514define signext i16 @vpreduce_or_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {515; CHECK-LABEL: vpreduce_or_nxv2i16:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma518; CHECK-NEXT: vmv.s.x v9, a0519; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma520; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t521; CHECK-NEXT: vmv.x.s a0, v9522; CHECK-NEXT: ret523 %r = call i16 @llvm.vp.reduce.or.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)524 ret i16 %r525}526 527define signext i16 @vpreduce_xor_nxv2i16(i16 signext %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {528; CHECK-LABEL: vpreduce_xor_nxv2i16:529; CHECK: # %bb.0:530; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma531; CHECK-NEXT: vmv.s.x v9, a0532; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma533; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t534; CHECK-NEXT: vmv.x.s a0, v9535; CHECK-NEXT: ret536 %r = call i16 @llvm.vp.reduce.xor.nxv2i16(i16 %s, <vscale x 2 x i16> %v, <vscale x 2 x i1> %m, i32 %evl)537 ret i16 %r538}539 540define signext i16 @vpreduce_add_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {541; CHECK-LABEL: vpreduce_add_nxv4i16:542; CHECK: # %bb.0:543; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma544; CHECK-NEXT: vmv.s.x v9, a0545; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma546; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t547; CHECK-NEXT: vmv.x.s a0, v9548; CHECK-NEXT: ret549 %r = call i16 @llvm.vp.reduce.add.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)550 ret i16 %r551}552 553define signext i16 @vpreduce_umax_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {554; CHECK-LABEL: vpreduce_umax_nxv4i16:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma557; CHECK-NEXT: vmv.s.x v9, a0558; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma559; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t560; CHECK-NEXT: vmv.x.s a0, v9561; CHECK-NEXT: ret562 %r = call i16 @llvm.vp.reduce.umax.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)563 ret i16 %r564}565 566define signext i16 @vpreduce_smax_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {567; CHECK-LABEL: vpreduce_smax_nxv4i16:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma570; CHECK-NEXT: vmv.s.x v9, a0571; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma572; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t573; CHECK-NEXT: vmv.x.s a0, v9574; CHECK-NEXT: ret575 %r = call i16 @llvm.vp.reduce.smax.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)576 ret i16 %r577}578 579define signext i16 @vpreduce_umin_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {580; CHECK-LABEL: vpreduce_umin_nxv4i16:581; CHECK: # %bb.0:582; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma583; CHECK-NEXT: vmv.s.x v9, a0584; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma585; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t586; CHECK-NEXT: vmv.x.s a0, v9587; CHECK-NEXT: ret588 %r = call i16 @llvm.vp.reduce.umin.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)589 ret i16 %r590}591 592define signext i16 @vpreduce_smin_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {593; CHECK-LABEL: vpreduce_smin_nxv4i16:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma596; CHECK-NEXT: vmv.s.x v9, a0597; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma598; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t599; CHECK-NEXT: vmv.x.s a0, v9600; CHECK-NEXT: ret601 %r = call i16 @llvm.vp.reduce.smin.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)602 ret i16 %r603}604 605define signext i16 @vpreduce_and_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {606; CHECK-LABEL: vpreduce_and_nxv4i16:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma609; CHECK-NEXT: vmv.s.x v9, a0610; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma611; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t612; CHECK-NEXT: vmv.x.s a0, v9613; CHECK-NEXT: ret614 %r = call i16 @llvm.vp.reduce.and.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)615 ret i16 %r616}617 618define signext i16 @vpreduce_or_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {619; CHECK-LABEL: vpreduce_or_nxv4i16:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma622; CHECK-NEXT: vmv.s.x v9, a0623; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma624; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t625; CHECK-NEXT: vmv.x.s a0, v9626; CHECK-NEXT: ret627 %r = call i16 @llvm.vp.reduce.or.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)628 ret i16 %r629}630 631define signext i16 @vpreduce_xor_nxv4i16(i16 signext %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {632; CHECK-LABEL: vpreduce_xor_nxv4i16:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma635; CHECK-NEXT: vmv.s.x v9, a0636; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma637; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t638; CHECK-NEXT: vmv.x.s a0, v9639; CHECK-NEXT: ret640 %r = call i16 @llvm.vp.reduce.xor.nxv4i16(i16 %s, <vscale x 4 x i16> %v, <vscale x 4 x i1> %m, i32 %evl)641 ret i16 %r642}643 644define signext i32 @vpreduce_add_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {645; CHECK-LABEL: vpreduce_add_nxv1i32:646; CHECK: # %bb.0:647; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma648; CHECK-NEXT: vmv.s.x v9, a0649; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma650; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t651; CHECK-NEXT: vmv.x.s a0, v9652; CHECK-NEXT: ret653 %r = call i32 @llvm.vp.reduce.add.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)654 ret i32 %r655}656 657define signext i32 @vpreduce_umax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {658; CHECK-LABEL: vpreduce_umax_nxv1i32:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma661; CHECK-NEXT: vmv.s.x v9, a0662; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma663; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t664; CHECK-NEXT: vmv.x.s a0, v9665; CHECK-NEXT: ret666 %r = call i32 @llvm.vp.reduce.umax.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)667 ret i32 %r668}669 670define signext i32 @vpreduce_smax_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {671; CHECK-LABEL: vpreduce_smax_nxv1i32:672; CHECK: # %bb.0:673; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma674; CHECK-NEXT: vmv.s.x v9, a0675; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma676; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t677; CHECK-NEXT: vmv.x.s a0, v9678; CHECK-NEXT: ret679 %r = call i32 @llvm.vp.reduce.smax.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)680 ret i32 %r681}682 683define signext i32 @vpreduce_umin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {684; CHECK-LABEL: vpreduce_umin_nxv1i32:685; CHECK: # %bb.0:686; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma687; CHECK-NEXT: vmv.s.x v9, a0688; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma689; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t690; CHECK-NEXT: vmv.x.s a0, v9691; CHECK-NEXT: ret692 %r = call i32 @llvm.vp.reduce.umin.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)693 ret i32 %r694}695 696define signext i32 @vpreduce_smin_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {697; CHECK-LABEL: vpreduce_smin_nxv1i32:698; CHECK: # %bb.0:699; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma700; CHECK-NEXT: vmv.s.x v9, a0701; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma702; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t703; CHECK-NEXT: vmv.x.s a0, v9704; CHECK-NEXT: ret705 %r = call i32 @llvm.vp.reduce.smin.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)706 ret i32 %r707}708 709define signext i32 @vpreduce_and_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {710; CHECK-LABEL: vpreduce_and_nxv1i32:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma713; CHECK-NEXT: vmv.s.x v9, a0714; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma715; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t716; CHECK-NEXT: vmv.x.s a0, v9717; CHECK-NEXT: ret718 %r = call i32 @llvm.vp.reduce.and.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)719 ret i32 %r720}721 722define signext i32 @vpreduce_or_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {723; CHECK-LABEL: vpreduce_or_nxv1i32:724; CHECK: # %bb.0:725; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma726; CHECK-NEXT: vmv.s.x v9, a0727; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma728; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t729; CHECK-NEXT: vmv.x.s a0, v9730; CHECK-NEXT: ret731 %r = call i32 @llvm.vp.reduce.or.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)732 ret i32 %r733}734 735define signext i32 @vpreduce_xor_nxv1i32(i32 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vpreduce_xor_nxv1i32:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma739; CHECK-NEXT: vmv.s.x v9, a0740; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma741; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t742; CHECK-NEXT: vmv.x.s a0, v9743; CHECK-NEXT: ret744 %r = call i32 @llvm.vp.reduce.xor.nxv1i32(i32 %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 %evl)745 ret i32 %r746}747 748define signext i32 @vpreduce_add_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {749; CHECK-LABEL: vpreduce_add_nxv2i32:750; CHECK: # %bb.0:751; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma752; CHECK-NEXT: vmv.s.x v9, a0753; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma754; CHECK-NEXT: vredsum.vs v9, v8, v9, v0.t755; CHECK-NEXT: vmv.x.s a0, v9756; CHECK-NEXT: ret757 %r = call i32 @llvm.vp.reduce.add.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)758 ret i32 %r759}760 761define signext i32 @vpreduce_umax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {762; CHECK-LABEL: vpreduce_umax_nxv2i32:763; CHECK: # %bb.0:764; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma765; CHECK-NEXT: vmv.s.x v9, a0766; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma767; CHECK-NEXT: vredmaxu.vs v9, v8, v9, v0.t768; CHECK-NEXT: vmv.x.s a0, v9769; CHECK-NEXT: ret770 %r = call i32 @llvm.vp.reduce.umax.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)771 ret i32 %r772}773 774define signext i32 @vpreduce_smax_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {775; CHECK-LABEL: vpreduce_smax_nxv2i32:776; CHECK: # %bb.0:777; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma778; CHECK-NEXT: vmv.s.x v9, a0779; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma780; CHECK-NEXT: vredmax.vs v9, v8, v9, v0.t781; CHECK-NEXT: vmv.x.s a0, v9782; CHECK-NEXT: ret783 %r = call i32 @llvm.vp.reduce.smax.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)784 ret i32 %r785}786 787define signext i32 @vpreduce_umin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {788; CHECK-LABEL: vpreduce_umin_nxv2i32:789; CHECK: # %bb.0:790; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma791; CHECK-NEXT: vmv.s.x v9, a0792; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma793; CHECK-NEXT: vredminu.vs v9, v8, v9, v0.t794; CHECK-NEXT: vmv.x.s a0, v9795; CHECK-NEXT: ret796 %r = call i32 @llvm.vp.reduce.umin.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)797 ret i32 %r798}799 800define signext i32 @vpreduce_smin_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {801; CHECK-LABEL: vpreduce_smin_nxv2i32:802; CHECK: # %bb.0:803; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma804; CHECK-NEXT: vmv.s.x v9, a0805; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma806; CHECK-NEXT: vredmin.vs v9, v8, v9, v0.t807; CHECK-NEXT: vmv.x.s a0, v9808; CHECK-NEXT: ret809 %r = call i32 @llvm.vp.reduce.smin.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)810 ret i32 %r811}812 813define signext i32 @vpreduce_and_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {814; CHECK-LABEL: vpreduce_and_nxv2i32:815; CHECK: # %bb.0:816; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma817; CHECK-NEXT: vmv.s.x v9, a0818; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma819; CHECK-NEXT: vredand.vs v9, v8, v9, v0.t820; CHECK-NEXT: vmv.x.s a0, v9821; CHECK-NEXT: ret822 %r = call i32 @llvm.vp.reduce.and.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)823 ret i32 %r824}825 826define signext i32 @vpreduce_or_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {827; CHECK-LABEL: vpreduce_or_nxv2i32:828; CHECK: # %bb.0:829; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma830; CHECK-NEXT: vmv.s.x v9, a0831; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma832; CHECK-NEXT: vredor.vs v9, v8, v9, v0.t833; CHECK-NEXT: vmv.x.s a0, v9834; CHECK-NEXT: ret835 %r = call i32 @llvm.vp.reduce.or.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)836 ret i32 %r837}838 839define signext i32 @vpreduce_xor_nxv2i32(i32 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {840; CHECK-LABEL: vpreduce_xor_nxv2i32:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma843; CHECK-NEXT: vmv.s.x v9, a0844; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma845; CHECK-NEXT: vredxor.vs v9, v8, v9, v0.t846; CHECK-NEXT: vmv.x.s a0, v9847; CHECK-NEXT: ret848 %r = call i32 @llvm.vp.reduce.xor.nxv2i32(i32 %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 %evl)849 ret i32 %r850}851 852define signext i32 @vpreduce_add_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {853; CHECK-LABEL: vpreduce_add_nxv4i32:854; CHECK: # %bb.0:855; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma856; CHECK-NEXT: vmv.s.x v10, a0857; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma858; CHECK-NEXT: vredsum.vs v10, v8, v10, v0.t859; CHECK-NEXT: vmv.x.s a0, v10860; CHECK-NEXT: ret861 %r = call i32 @llvm.vp.reduce.add.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)862 ret i32 %r863}864 865define signext i32 @vpreduce_umax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {866; CHECK-LABEL: vpreduce_umax_nxv4i32:867; CHECK: # %bb.0:868; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma869; CHECK-NEXT: vmv.s.x v10, a0870; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma871; CHECK-NEXT: vredmaxu.vs v10, v8, v10, v0.t872; CHECK-NEXT: vmv.x.s a0, v10873; CHECK-NEXT: ret874 %r = call i32 @llvm.vp.reduce.umax.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)875 ret i32 %r876}877 878define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {879; CHECK-LABEL: vpreduce_umax_nxv32i32:880; CHECK: # %bb.0:881; CHECK-NEXT: csrr a3, vlenb882; CHECK-NEXT: srli a2, a3, 2883; CHECK-NEXT: slli a3, a3, 1884; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma885; CHECK-NEXT: vslidedown.vx v24, v0, a2886; CHECK-NEXT: sub a2, a1, a3887; CHECK-NEXT: sltu a4, a1, a2888; CHECK-NEXT: addi a4, a4, -1889; CHECK-NEXT: and a2, a4, a2890; CHECK-NEXT: bltu a1, a3, .LBB67_2891; CHECK-NEXT: # %bb.1:892; CHECK-NEXT: mv a1, a3893; CHECK-NEXT: .LBB67_2:894; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma895; CHECK-NEXT: vmv.s.x v25, a0896; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma897; CHECK-NEXT: vredmaxu.vs v25, v8, v25, v0.t898; CHECK-NEXT: vmv1r.v v0, v24899; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma900; CHECK-NEXT: vredmaxu.vs v25, v16, v25, v0.t901; CHECK-NEXT: vmv.x.s a0, v25902; CHECK-NEXT: ret903 %r = call i32 @llvm.vp.reduce.umax.nxv32i32(i32 %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 %evl)904 ret i32 %r905}906 907define signext i32 @vpreduce_smax_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {908; CHECK-LABEL: vpreduce_smax_nxv4i32:909; CHECK: # %bb.0:910; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma911; CHECK-NEXT: vmv.s.x v10, a0912; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma913; CHECK-NEXT: vredmax.vs v10, v8, v10, v0.t914; CHECK-NEXT: vmv.x.s a0, v10915; CHECK-NEXT: ret916 %r = call i32 @llvm.vp.reduce.smax.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)917 ret i32 %r918}919 920define signext i32 @vpreduce_umin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {921; CHECK-LABEL: vpreduce_umin_nxv4i32:922; CHECK: # %bb.0:923; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma924; CHECK-NEXT: vmv.s.x v10, a0925; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma926; CHECK-NEXT: vredminu.vs v10, v8, v10, v0.t927; CHECK-NEXT: vmv.x.s a0, v10928; CHECK-NEXT: ret929 %r = call i32 @llvm.vp.reduce.umin.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)930 ret i32 %r931}932 933define signext i32 @vpreduce_smin_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {934; CHECK-LABEL: vpreduce_smin_nxv4i32:935; CHECK: # %bb.0:936; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma937; CHECK-NEXT: vmv.s.x v10, a0938; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma939; CHECK-NEXT: vredmin.vs v10, v8, v10, v0.t940; CHECK-NEXT: vmv.x.s a0, v10941; CHECK-NEXT: ret942 %r = call i32 @llvm.vp.reduce.smin.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)943 ret i32 %r944}945 946define signext i32 @vpreduce_and_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {947; CHECK-LABEL: vpreduce_and_nxv4i32:948; CHECK: # %bb.0:949; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma950; CHECK-NEXT: vmv.s.x v10, a0951; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma952; CHECK-NEXT: vredand.vs v10, v8, v10, v0.t953; CHECK-NEXT: vmv.x.s a0, v10954; CHECK-NEXT: ret955 %r = call i32 @llvm.vp.reduce.and.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)956 ret i32 %r957}958 959define signext i32 @vpreduce_or_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {960; CHECK-LABEL: vpreduce_or_nxv4i32:961; CHECK: # %bb.0:962; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma963; CHECK-NEXT: vmv.s.x v10, a0964; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma965; CHECK-NEXT: vredor.vs v10, v8, v10, v0.t966; CHECK-NEXT: vmv.x.s a0, v10967; CHECK-NEXT: ret968 %r = call i32 @llvm.vp.reduce.or.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)969 ret i32 %r970}971 972define signext i32 @vpreduce_xor_nxv4i32(i32 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {973; CHECK-LABEL: vpreduce_xor_nxv4i32:974; CHECK: # %bb.0:975; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma976; CHECK-NEXT: vmv.s.x v10, a0977; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma978; CHECK-NEXT: vredxor.vs v10, v8, v10, v0.t979; CHECK-NEXT: vmv.x.s a0, v10980; CHECK-NEXT: ret981 %r = call i32 @llvm.vp.reduce.xor.nxv4i32(i32 %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 %evl)982 ret i32 %r983}984 985define signext i64 @vpreduce_add_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {986; RV32-LABEL: vpreduce_add_nxv1i64:987; RV32: # %bb.0:988; RV32-NEXT: addi sp, sp, -16989; RV32-NEXT: .cfi_def_cfa_offset 16990; RV32-NEXT: sw a0, 8(sp)991; RV32-NEXT: sw a1, 12(sp)992; RV32-NEXT: addi a0, sp, 8993; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma994; RV32-NEXT: vlse64.v v9, (a0), zero995; RV32-NEXT: li a1, 32996; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma997; RV32-NEXT: vredsum.vs v9, v8, v9, v0.t998; RV32-NEXT: vmv.x.s a0, v9999; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1000; RV32-NEXT: vsrl.vx v8, v9, a11001; RV32-NEXT: vmv.x.s a1, v81002; RV32-NEXT: addi sp, sp, 161003; RV32-NEXT: .cfi_def_cfa_offset 01004; RV32-NEXT: ret1005;1006; RV64-LABEL: vpreduce_add_nxv1i64:1007; RV64: # %bb.0:1008; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1009; RV64-NEXT: vmv.s.x v9, a01010; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1011; RV64-NEXT: vredsum.vs v9, v8, v9, v0.t1012; RV64-NEXT: vmv.x.s a0, v91013; RV64-NEXT: ret1014 %r = call i64 @llvm.vp.reduce.add.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1015 ret i64 %r1016}1017 1018define signext i64 @vpwreduce_add_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1019; RV32-LABEL: vpwreduce_add_nxv1i32:1020; RV32: # %bb.0:1021; RV32-NEXT: addi sp, sp, -161022; RV32-NEXT: .cfi_def_cfa_offset 161023; RV32-NEXT: sw a0, 8(sp)1024; RV32-NEXT: sw a1, 12(sp)1025; RV32-NEXT: addi a0, sp, 81026; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1027; RV32-NEXT: vlse64.v v9, (a0), zero1028; RV32-NEXT: li a1, 321029; RV32-NEXT: vsetvli zero, a2, e32, mf2, ta, ma1030; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t1031; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1032; RV32-NEXT: vmv.x.s a0, v91033; RV32-NEXT: vsrl.vx v8, v9, a11034; RV32-NEXT: vmv.x.s a1, v81035; RV32-NEXT: addi sp, sp, 161036; RV32-NEXT: .cfi_def_cfa_offset 01037; RV32-NEXT: ret1038;1039; RV64-LABEL: vpwreduce_add_nxv1i32:1040; RV64: # %bb.0:1041; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1042; RV64-NEXT: vmv.s.x v9, a01043; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1044; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t1045; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma1046; RV64-NEXT: vmv.x.s a0, v91047; RV64-NEXT: ret1048 %e = sext <vscale x 1 x i32> %v to <vscale x 1 x i64>1049 %r = call i64 @llvm.vp.reduce.add.nxv1i64(i64 %s, <vscale x 1 x i64> %e, <vscale x 1 x i1> %m, i32 %evl)1050 ret i64 %r1051}1052 1053define signext i64 @vpwreduce_uadd_nxv1i32(i64 signext %s, <vscale x 1 x i32> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1054; RV32-LABEL: vpwreduce_uadd_nxv1i32:1055; RV32: # %bb.0:1056; RV32-NEXT: addi sp, sp, -161057; RV32-NEXT: .cfi_def_cfa_offset 161058; RV32-NEXT: sw a0, 8(sp)1059; RV32-NEXT: sw a1, 12(sp)1060; RV32-NEXT: addi a0, sp, 81061; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1062; RV32-NEXT: vlse64.v v9, (a0), zero1063; RV32-NEXT: li a1, 321064; RV32-NEXT: vsetvli zero, a2, e32, mf2, ta, ma1065; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t1066; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1067; RV32-NEXT: vmv.x.s a0, v91068; RV32-NEXT: vsrl.vx v8, v9, a11069; RV32-NEXT: vmv.x.s a1, v81070; RV32-NEXT: addi sp, sp, 161071; RV32-NEXT: .cfi_def_cfa_offset 01072; RV32-NEXT: ret1073;1074; RV64-LABEL: vpwreduce_uadd_nxv1i32:1075; RV64: # %bb.0:1076; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1077; RV64-NEXT: vmv.s.x v9, a01078; RV64-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1079; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t1080; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma1081; RV64-NEXT: vmv.x.s a0, v91082; RV64-NEXT: ret1083 %e = sext <vscale x 1 x i32> %v to <vscale x 1 x i64>1084 %r = call i64 @llvm.vp.reduce.add.nxv1i64(i64 %s, <vscale x 1 x i64> %e, <vscale x 1 x i1> %m, i32 %evl)1085 ret i64 %r1086}1087 1088define signext i64 @vpreduce_umax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1089; RV32-LABEL: vpreduce_umax_nxv1i64:1090; RV32: # %bb.0:1091; RV32-NEXT: addi sp, sp, -161092; RV32-NEXT: .cfi_def_cfa_offset 161093; RV32-NEXT: sw a0, 8(sp)1094; RV32-NEXT: sw a1, 12(sp)1095; RV32-NEXT: addi a0, sp, 81096; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1097; RV32-NEXT: vlse64.v v9, (a0), zero1098; RV32-NEXT: li a1, 321099; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1100; RV32-NEXT: vredmaxu.vs v9, v8, v9, v0.t1101; RV32-NEXT: vmv.x.s a0, v91102; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1103; RV32-NEXT: vsrl.vx v8, v9, a11104; RV32-NEXT: vmv.x.s a1, v81105; RV32-NEXT: addi sp, sp, 161106; RV32-NEXT: .cfi_def_cfa_offset 01107; RV32-NEXT: ret1108;1109; RV64-LABEL: vpreduce_umax_nxv1i64:1110; RV64: # %bb.0:1111; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1112; RV64-NEXT: vmv.s.x v9, a01113; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1114; RV64-NEXT: vredmaxu.vs v9, v8, v9, v0.t1115; RV64-NEXT: vmv.x.s a0, v91116; RV64-NEXT: ret1117 %r = call i64 @llvm.vp.reduce.umax.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1118 ret i64 %r1119}1120 1121define signext i64 @vpreduce_smax_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1122; RV32-LABEL: vpreduce_smax_nxv1i64:1123; RV32: # %bb.0:1124; RV32-NEXT: addi sp, sp, -161125; RV32-NEXT: .cfi_def_cfa_offset 161126; RV32-NEXT: sw a0, 8(sp)1127; RV32-NEXT: sw a1, 12(sp)1128; RV32-NEXT: addi a0, sp, 81129; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1130; RV32-NEXT: vlse64.v v9, (a0), zero1131; RV32-NEXT: li a1, 321132; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1133; RV32-NEXT: vredmax.vs v9, v8, v9, v0.t1134; RV32-NEXT: vmv.x.s a0, v91135; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1136; RV32-NEXT: vsrl.vx v8, v9, a11137; RV32-NEXT: vmv.x.s a1, v81138; RV32-NEXT: addi sp, sp, 161139; RV32-NEXT: .cfi_def_cfa_offset 01140; RV32-NEXT: ret1141;1142; RV64-LABEL: vpreduce_smax_nxv1i64:1143; RV64: # %bb.0:1144; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1145; RV64-NEXT: vmv.s.x v9, a01146; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1147; RV64-NEXT: vredmax.vs v9, v8, v9, v0.t1148; RV64-NEXT: vmv.x.s a0, v91149; RV64-NEXT: ret1150 %r = call i64 @llvm.vp.reduce.smax.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1151 ret i64 %r1152}1153 1154define signext i64 @vpreduce_umin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1155; RV32-LABEL: vpreduce_umin_nxv1i64:1156; RV32: # %bb.0:1157; RV32-NEXT: addi sp, sp, -161158; RV32-NEXT: .cfi_def_cfa_offset 161159; RV32-NEXT: sw a0, 8(sp)1160; RV32-NEXT: sw a1, 12(sp)1161; RV32-NEXT: addi a0, sp, 81162; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1163; RV32-NEXT: vlse64.v v9, (a0), zero1164; RV32-NEXT: li a1, 321165; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1166; RV32-NEXT: vredminu.vs v9, v8, v9, v0.t1167; RV32-NEXT: vmv.x.s a0, v91168; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1169; RV32-NEXT: vsrl.vx v8, v9, a11170; RV32-NEXT: vmv.x.s a1, v81171; RV32-NEXT: addi sp, sp, 161172; RV32-NEXT: .cfi_def_cfa_offset 01173; RV32-NEXT: ret1174;1175; RV64-LABEL: vpreduce_umin_nxv1i64:1176; RV64: # %bb.0:1177; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1178; RV64-NEXT: vmv.s.x v9, a01179; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1180; RV64-NEXT: vredminu.vs v9, v8, v9, v0.t1181; RV64-NEXT: vmv.x.s a0, v91182; RV64-NEXT: ret1183 %r = call i64 @llvm.vp.reduce.umin.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1184 ret i64 %r1185}1186 1187define signext i64 @vpreduce_smin_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1188; RV32-LABEL: vpreduce_smin_nxv1i64:1189; RV32: # %bb.0:1190; RV32-NEXT: addi sp, sp, -161191; RV32-NEXT: .cfi_def_cfa_offset 161192; RV32-NEXT: sw a0, 8(sp)1193; RV32-NEXT: sw a1, 12(sp)1194; RV32-NEXT: addi a0, sp, 81195; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1196; RV32-NEXT: vlse64.v v9, (a0), zero1197; RV32-NEXT: li a1, 321198; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1199; RV32-NEXT: vredmin.vs v9, v8, v9, v0.t1200; RV32-NEXT: vmv.x.s a0, v91201; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1202; RV32-NEXT: vsrl.vx v8, v9, a11203; RV32-NEXT: vmv.x.s a1, v81204; RV32-NEXT: addi sp, sp, 161205; RV32-NEXT: .cfi_def_cfa_offset 01206; RV32-NEXT: ret1207;1208; RV64-LABEL: vpreduce_smin_nxv1i64:1209; RV64: # %bb.0:1210; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1211; RV64-NEXT: vmv.s.x v9, a01212; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1213; RV64-NEXT: vredmin.vs v9, v8, v9, v0.t1214; RV64-NEXT: vmv.x.s a0, v91215; RV64-NEXT: ret1216 %r = call i64 @llvm.vp.reduce.smin.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1217 ret i64 %r1218}1219 1220define signext i64 @vpreduce_and_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1221; RV32-LABEL: vpreduce_and_nxv1i64:1222; RV32: # %bb.0:1223; RV32-NEXT: addi sp, sp, -161224; RV32-NEXT: .cfi_def_cfa_offset 161225; RV32-NEXT: sw a0, 8(sp)1226; RV32-NEXT: sw a1, 12(sp)1227; RV32-NEXT: addi a0, sp, 81228; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1229; RV32-NEXT: vlse64.v v9, (a0), zero1230; RV32-NEXT: li a1, 321231; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1232; RV32-NEXT: vredand.vs v9, v8, v9, v0.t1233; RV32-NEXT: vmv.x.s a0, v91234; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1235; RV32-NEXT: vsrl.vx v8, v9, a11236; RV32-NEXT: vmv.x.s a1, v81237; RV32-NEXT: addi sp, sp, 161238; RV32-NEXT: .cfi_def_cfa_offset 01239; RV32-NEXT: ret1240;1241; RV64-LABEL: vpreduce_and_nxv1i64:1242; RV64: # %bb.0:1243; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1244; RV64-NEXT: vmv.s.x v9, a01245; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1246; RV64-NEXT: vredand.vs v9, v8, v9, v0.t1247; RV64-NEXT: vmv.x.s a0, v91248; RV64-NEXT: ret1249 %r = call i64 @llvm.vp.reduce.and.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1250 ret i64 %r1251}1252 1253define signext i64 @vpreduce_or_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1254; RV32-LABEL: vpreduce_or_nxv1i64:1255; RV32: # %bb.0:1256; RV32-NEXT: addi sp, sp, -161257; RV32-NEXT: .cfi_def_cfa_offset 161258; RV32-NEXT: sw a0, 8(sp)1259; RV32-NEXT: sw a1, 12(sp)1260; RV32-NEXT: addi a0, sp, 81261; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1262; RV32-NEXT: vlse64.v v9, (a0), zero1263; RV32-NEXT: li a1, 321264; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1265; RV32-NEXT: vredor.vs v9, v8, v9, v0.t1266; RV32-NEXT: vmv.x.s a0, v91267; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1268; RV32-NEXT: vsrl.vx v8, v9, a11269; RV32-NEXT: vmv.x.s a1, v81270; RV32-NEXT: addi sp, sp, 161271; RV32-NEXT: .cfi_def_cfa_offset 01272; RV32-NEXT: ret1273;1274; RV64-LABEL: vpreduce_or_nxv1i64:1275; RV64: # %bb.0:1276; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1277; RV64-NEXT: vmv.s.x v9, a01278; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1279; RV64-NEXT: vredor.vs v9, v8, v9, v0.t1280; RV64-NEXT: vmv.x.s a0, v91281; RV64-NEXT: ret1282 %r = call i64 @llvm.vp.reduce.or.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1283 ret i64 %r1284}1285 1286define signext i64 @vpreduce_xor_nxv1i64(i64 signext %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {1287; RV32-LABEL: vpreduce_xor_nxv1i64:1288; RV32: # %bb.0:1289; RV32-NEXT: addi sp, sp, -161290; RV32-NEXT: .cfi_def_cfa_offset 161291; RV32-NEXT: sw a0, 8(sp)1292; RV32-NEXT: sw a1, 12(sp)1293; RV32-NEXT: addi a0, sp, 81294; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1295; RV32-NEXT: vlse64.v v9, (a0), zero1296; RV32-NEXT: li a1, 321297; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1298; RV32-NEXT: vredxor.vs v9, v8, v9, v0.t1299; RV32-NEXT: vmv.x.s a0, v91300; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1301; RV32-NEXT: vsrl.vx v8, v9, a11302; RV32-NEXT: vmv.x.s a1, v81303; RV32-NEXT: addi sp, sp, 161304; RV32-NEXT: .cfi_def_cfa_offset 01305; RV32-NEXT: ret1306;1307; RV64-LABEL: vpreduce_xor_nxv1i64:1308; RV64: # %bb.0:1309; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1310; RV64-NEXT: vmv.s.x v9, a01311; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1312; RV64-NEXT: vredxor.vs v9, v8, v9, v0.t1313; RV64-NEXT: vmv.x.s a0, v91314; RV64-NEXT: ret1315 %r = call i64 @llvm.vp.reduce.xor.nxv1i64(i64 %s, <vscale x 1 x i64> %v, <vscale x 1 x i1> %m, i32 %evl)1316 ret i64 %r1317}1318 1319define signext i64 @vpreduce_add_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1320; RV32-LABEL: vpreduce_add_nxv2i64:1321; RV32: # %bb.0:1322; RV32-NEXT: addi sp, sp, -161323; RV32-NEXT: .cfi_def_cfa_offset 161324; RV32-NEXT: sw a0, 8(sp)1325; RV32-NEXT: sw a1, 12(sp)1326; RV32-NEXT: addi a0, sp, 81327; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1328; RV32-NEXT: vlse64.v v10, (a0), zero1329; RV32-NEXT: li a1, 321330; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1331; RV32-NEXT: vredsum.vs v10, v8, v10, v0.t1332; RV32-NEXT: vmv.x.s a0, v101333; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1334; RV32-NEXT: vsrl.vx v8, v10, a11335; RV32-NEXT: vmv.x.s a1, v81336; RV32-NEXT: addi sp, sp, 161337; RV32-NEXT: .cfi_def_cfa_offset 01338; RV32-NEXT: ret1339;1340; RV64-LABEL: vpreduce_add_nxv2i64:1341; RV64: # %bb.0:1342; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1343; RV64-NEXT: vmv.s.x v10, a01344; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1345; RV64-NEXT: vredsum.vs v10, v8, v10, v0.t1346; RV64-NEXT: vmv.x.s a0, v101347; RV64-NEXT: ret1348 %r = call i64 @llvm.vp.reduce.add.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1349 ret i64 %r1350}1351 1352define signext i64 @vwpreduce_add_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1353; RV32-LABEL: vwpreduce_add_nxv2i32:1354; RV32: # %bb.0:1355; RV32-NEXT: addi sp, sp, -161356; RV32-NEXT: .cfi_def_cfa_offset 161357; RV32-NEXT: sw a0, 8(sp)1358; RV32-NEXT: sw a1, 12(sp)1359; RV32-NEXT: addi a0, sp, 81360; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1361; RV32-NEXT: vlse64.v v9, (a0), zero1362; RV32-NEXT: li a1, 321363; RV32-NEXT: vsetvli zero, a2, e32, m1, ta, ma1364; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t1365; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1366; RV32-NEXT: vmv.x.s a0, v91367; RV32-NEXT: vsrl.vx v8, v9, a11368; RV32-NEXT: vmv.x.s a1, v81369; RV32-NEXT: addi sp, sp, 161370; RV32-NEXT: .cfi_def_cfa_offset 01371; RV32-NEXT: ret1372;1373; RV64-LABEL: vwpreduce_add_nxv2i32:1374; RV64: # %bb.0:1375; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1376; RV64-NEXT: vmv.s.x v9, a01377; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma1378; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t1379; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1380; RV64-NEXT: vmv.x.s a0, v91381; RV64-NEXT: ret1382 %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>1383 %r = call i64 @llvm.vp.reduce.add.nxv2i64(i64 %s, <vscale x 2 x i64> %e, <vscale x 2 x i1> %m, i32 %evl)1384 ret i64 %r1385}1386 1387define signext i64 @vwpreduce_uadd_nxv2i32(i64 signext %s, <vscale x 2 x i32> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1388; RV32-LABEL: vwpreduce_uadd_nxv2i32:1389; RV32: # %bb.0:1390; RV32-NEXT: addi sp, sp, -161391; RV32-NEXT: .cfi_def_cfa_offset 161392; RV32-NEXT: sw a0, 8(sp)1393; RV32-NEXT: sw a1, 12(sp)1394; RV32-NEXT: addi a0, sp, 81395; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1396; RV32-NEXT: vlse64.v v9, (a0), zero1397; RV32-NEXT: li a1, 321398; RV32-NEXT: vsetvli zero, a2, e32, m1, ta, ma1399; RV32-NEXT: vwredsum.vs v9, v8, v9, v0.t1400; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1401; RV32-NEXT: vmv.x.s a0, v91402; RV32-NEXT: vsrl.vx v8, v9, a11403; RV32-NEXT: vmv.x.s a1, v81404; RV32-NEXT: addi sp, sp, 161405; RV32-NEXT: .cfi_def_cfa_offset 01406; RV32-NEXT: ret1407;1408; RV64-LABEL: vwpreduce_uadd_nxv2i32:1409; RV64: # %bb.0:1410; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1411; RV64-NEXT: vmv.s.x v9, a01412; RV64-NEXT: vsetvli zero, a1, e32, m1, ta, ma1413; RV64-NEXT: vwredsum.vs v9, v8, v9, v0.t1414; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1415; RV64-NEXT: vmv.x.s a0, v91416; RV64-NEXT: ret1417 %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>1418 %r = call i64 @llvm.vp.reduce.add.nxv2i64(i64 %s, <vscale x 2 x i64> %e, <vscale x 2 x i1> %m, i32 %evl)1419 ret i64 %r1420}1421 1422define signext i64 @vpreduce_umax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1423; RV32-LABEL: vpreduce_umax_nxv2i64:1424; RV32: # %bb.0:1425; RV32-NEXT: addi sp, sp, -161426; RV32-NEXT: .cfi_def_cfa_offset 161427; RV32-NEXT: sw a0, 8(sp)1428; RV32-NEXT: sw a1, 12(sp)1429; RV32-NEXT: addi a0, sp, 81430; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1431; RV32-NEXT: vlse64.v v10, (a0), zero1432; RV32-NEXT: li a1, 321433; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1434; RV32-NEXT: vredmaxu.vs v10, v8, v10, v0.t1435; RV32-NEXT: vmv.x.s a0, v101436; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1437; RV32-NEXT: vsrl.vx v8, v10, a11438; RV32-NEXT: vmv.x.s a1, v81439; RV32-NEXT: addi sp, sp, 161440; RV32-NEXT: .cfi_def_cfa_offset 01441; RV32-NEXT: ret1442;1443; RV64-LABEL: vpreduce_umax_nxv2i64:1444; RV64: # %bb.0:1445; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1446; RV64-NEXT: vmv.s.x v10, a01447; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1448; RV64-NEXT: vredmaxu.vs v10, v8, v10, v0.t1449; RV64-NEXT: vmv.x.s a0, v101450; RV64-NEXT: ret1451 %r = call i64 @llvm.vp.reduce.umax.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1452 ret i64 %r1453}1454 1455define signext i64 @vpreduce_smax_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1456; RV32-LABEL: vpreduce_smax_nxv2i64:1457; RV32: # %bb.0:1458; RV32-NEXT: addi sp, sp, -161459; RV32-NEXT: .cfi_def_cfa_offset 161460; RV32-NEXT: sw a0, 8(sp)1461; RV32-NEXT: sw a1, 12(sp)1462; RV32-NEXT: addi a0, sp, 81463; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1464; RV32-NEXT: vlse64.v v10, (a0), zero1465; RV32-NEXT: li a1, 321466; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1467; RV32-NEXT: vredmax.vs v10, v8, v10, v0.t1468; RV32-NEXT: vmv.x.s a0, v101469; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1470; RV32-NEXT: vsrl.vx v8, v10, a11471; RV32-NEXT: vmv.x.s a1, v81472; RV32-NEXT: addi sp, sp, 161473; RV32-NEXT: .cfi_def_cfa_offset 01474; RV32-NEXT: ret1475;1476; RV64-LABEL: vpreduce_smax_nxv2i64:1477; RV64: # %bb.0:1478; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1479; RV64-NEXT: vmv.s.x v10, a01480; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1481; RV64-NEXT: vredmax.vs v10, v8, v10, v0.t1482; RV64-NEXT: vmv.x.s a0, v101483; RV64-NEXT: ret1484 %r = call i64 @llvm.vp.reduce.smax.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1485 ret i64 %r1486}1487 1488define signext i64 @vpreduce_umin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1489; RV32-LABEL: vpreduce_umin_nxv2i64:1490; RV32: # %bb.0:1491; RV32-NEXT: addi sp, sp, -161492; RV32-NEXT: .cfi_def_cfa_offset 161493; RV32-NEXT: sw a0, 8(sp)1494; RV32-NEXT: sw a1, 12(sp)1495; RV32-NEXT: addi a0, sp, 81496; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1497; RV32-NEXT: vlse64.v v10, (a0), zero1498; RV32-NEXT: li a1, 321499; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1500; RV32-NEXT: vredminu.vs v10, v8, v10, v0.t1501; RV32-NEXT: vmv.x.s a0, v101502; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1503; RV32-NEXT: vsrl.vx v8, v10, a11504; RV32-NEXT: vmv.x.s a1, v81505; RV32-NEXT: addi sp, sp, 161506; RV32-NEXT: .cfi_def_cfa_offset 01507; RV32-NEXT: ret1508;1509; RV64-LABEL: vpreduce_umin_nxv2i64:1510; RV64: # %bb.0:1511; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1512; RV64-NEXT: vmv.s.x v10, a01513; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1514; RV64-NEXT: vredminu.vs v10, v8, v10, v0.t1515; RV64-NEXT: vmv.x.s a0, v101516; RV64-NEXT: ret1517 %r = call i64 @llvm.vp.reduce.umin.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1518 ret i64 %r1519}1520 1521define signext i64 @vpreduce_smin_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1522; RV32-LABEL: vpreduce_smin_nxv2i64:1523; RV32: # %bb.0:1524; RV32-NEXT: addi sp, sp, -161525; RV32-NEXT: .cfi_def_cfa_offset 161526; RV32-NEXT: sw a0, 8(sp)1527; RV32-NEXT: sw a1, 12(sp)1528; RV32-NEXT: addi a0, sp, 81529; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1530; RV32-NEXT: vlse64.v v10, (a0), zero1531; RV32-NEXT: li a1, 321532; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1533; RV32-NEXT: vredmin.vs v10, v8, v10, v0.t1534; RV32-NEXT: vmv.x.s a0, v101535; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1536; RV32-NEXT: vsrl.vx v8, v10, a11537; RV32-NEXT: vmv.x.s a1, v81538; RV32-NEXT: addi sp, sp, 161539; RV32-NEXT: .cfi_def_cfa_offset 01540; RV32-NEXT: ret1541;1542; RV64-LABEL: vpreduce_smin_nxv2i64:1543; RV64: # %bb.0:1544; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1545; RV64-NEXT: vmv.s.x v10, a01546; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1547; RV64-NEXT: vredmin.vs v10, v8, v10, v0.t1548; RV64-NEXT: vmv.x.s a0, v101549; RV64-NEXT: ret1550 %r = call i64 @llvm.vp.reduce.smin.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1551 ret i64 %r1552}1553 1554define signext i64 @vpreduce_and_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1555; RV32-LABEL: vpreduce_and_nxv2i64:1556; RV32: # %bb.0:1557; RV32-NEXT: addi sp, sp, -161558; RV32-NEXT: .cfi_def_cfa_offset 161559; RV32-NEXT: sw a0, 8(sp)1560; RV32-NEXT: sw a1, 12(sp)1561; RV32-NEXT: addi a0, sp, 81562; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1563; RV32-NEXT: vlse64.v v10, (a0), zero1564; RV32-NEXT: li a1, 321565; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1566; RV32-NEXT: vredand.vs v10, v8, v10, v0.t1567; RV32-NEXT: vmv.x.s a0, v101568; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1569; RV32-NEXT: vsrl.vx v8, v10, a11570; RV32-NEXT: vmv.x.s a1, v81571; RV32-NEXT: addi sp, sp, 161572; RV32-NEXT: .cfi_def_cfa_offset 01573; RV32-NEXT: ret1574;1575; RV64-LABEL: vpreduce_and_nxv2i64:1576; RV64: # %bb.0:1577; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1578; RV64-NEXT: vmv.s.x v10, a01579; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1580; RV64-NEXT: vredand.vs v10, v8, v10, v0.t1581; RV64-NEXT: vmv.x.s a0, v101582; RV64-NEXT: ret1583 %r = call i64 @llvm.vp.reduce.and.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1584 ret i64 %r1585}1586 1587define signext i64 @vpreduce_or_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1588; RV32-LABEL: vpreduce_or_nxv2i64:1589; RV32: # %bb.0:1590; RV32-NEXT: addi sp, sp, -161591; RV32-NEXT: .cfi_def_cfa_offset 161592; RV32-NEXT: sw a0, 8(sp)1593; RV32-NEXT: sw a1, 12(sp)1594; RV32-NEXT: addi a0, sp, 81595; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1596; RV32-NEXT: vlse64.v v10, (a0), zero1597; RV32-NEXT: li a1, 321598; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1599; RV32-NEXT: vredor.vs v10, v8, v10, v0.t1600; RV32-NEXT: vmv.x.s a0, v101601; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1602; RV32-NEXT: vsrl.vx v8, v10, a11603; RV32-NEXT: vmv.x.s a1, v81604; RV32-NEXT: addi sp, sp, 161605; RV32-NEXT: .cfi_def_cfa_offset 01606; RV32-NEXT: ret1607;1608; RV64-LABEL: vpreduce_or_nxv2i64:1609; RV64: # %bb.0:1610; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1611; RV64-NEXT: vmv.s.x v10, a01612; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1613; RV64-NEXT: vredor.vs v10, v8, v10, v0.t1614; RV64-NEXT: vmv.x.s a0, v101615; RV64-NEXT: ret1616 %r = call i64 @llvm.vp.reduce.or.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1617 ret i64 %r1618}1619 1620define signext i64 @vpreduce_xor_nxv2i64(i64 signext %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {1621; RV32-LABEL: vpreduce_xor_nxv2i64:1622; RV32: # %bb.0:1623; RV32-NEXT: addi sp, sp, -161624; RV32-NEXT: .cfi_def_cfa_offset 161625; RV32-NEXT: sw a0, 8(sp)1626; RV32-NEXT: sw a1, 12(sp)1627; RV32-NEXT: addi a0, sp, 81628; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1629; RV32-NEXT: vlse64.v v10, (a0), zero1630; RV32-NEXT: li a1, 321631; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1632; RV32-NEXT: vredxor.vs v10, v8, v10, v0.t1633; RV32-NEXT: vmv.x.s a0, v101634; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1635; RV32-NEXT: vsrl.vx v8, v10, a11636; RV32-NEXT: vmv.x.s a1, v81637; RV32-NEXT: addi sp, sp, 161638; RV32-NEXT: .cfi_def_cfa_offset 01639; RV32-NEXT: ret1640;1641; RV64-LABEL: vpreduce_xor_nxv2i64:1642; RV64: # %bb.0:1643; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1644; RV64-NEXT: vmv.s.x v10, a01645; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1646; RV64-NEXT: vredxor.vs v10, v8, v10, v0.t1647; RV64-NEXT: vmv.x.s a0, v101648; RV64-NEXT: ret1649 %r = call i64 @llvm.vp.reduce.xor.nxv2i64(i64 %s, <vscale x 2 x i64> %v, <vscale x 2 x i1> %m, i32 %evl)1650 ret i64 %r1651}1652 1653define signext i64 @vpreduce_add_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1654; RV32-LABEL: vpreduce_add_nxv4i64:1655; RV32: # %bb.0:1656; RV32-NEXT: addi sp, sp, -161657; RV32-NEXT: .cfi_def_cfa_offset 161658; RV32-NEXT: sw a0, 8(sp)1659; RV32-NEXT: sw a1, 12(sp)1660; RV32-NEXT: addi a0, sp, 81661; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1662; RV32-NEXT: vlse64.v v12, (a0), zero1663; RV32-NEXT: li a1, 321664; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1665; RV32-NEXT: vredsum.vs v12, v8, v12, v0.t1666; RV32-NEXT: vmv.x.s a0, v121667; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1668; RV32-NEXT: vsrl.vx v8, v12, a11669; RV32-NEXT: vmv.x.s a1, v81670; RV32-NEXT: addi sp, sp, 161671; RV32-NEXT: .cfi_def_cfa_offset 01672; RV32-NEXT: ret1673;1674; RV64-LABEL: vpreduce_add_nxv4i64:1675; RV64: # %bb.0:1676; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1677; RV64-NEXT: vmv.s.x v12, a01678; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1679; RV64-NEXT: vredsum.vs v12, v8, v12, v0.t1680; RV64-NEXT: vmv.x.s a0, v121681; RV64-NEXT: ret1682 %r = call i64 @llvm.vp.reduce.add.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1683 ret i64 %r1684}1685 1686define signext i64 @vpwreduce_add_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1687; RV32-LABEL: vpwreduce_add_nxv4i32:1688; RV32: # %bb.0:1689; RV32-NEXT: addi sp, sp, -161690; RV32-NEXT: .cfi_def_cfa_offset 161691; RV32-NEXT: sw a0, 8(sp)1692; RV32-NEXT: sw a1, 12(sp)1693; RV32-NEXT: addi a0, sp, 81694; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1695; RV32-NEXT: vlse64.v v10, (a0), zero1696; RV32-NEXT: li a1, 321697; RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma1698; RV32-NEXT: vwredsum.vs v10, v8, v10, v0.t1699; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1700; RV32-NEXT: vmv.x.s a0, v101701; RV32-NEXT: vsrl.vx v8, v10, a11702; RV32-NEXT: vmv.x.s a1, v81703; RV32-NEXT: addi sp, sp, 161704; RV32-NEXT: .cfi_def_cfa_offset 01705; RV32-NEXT: ret1706;1707; RV64-LABEL: vpwreduce_add_nxv4i32:1708; RV64: # %bb.0:1709; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1710; RV64-NEXT: vmv.s.x v10, a01711; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1712; RV64-NEXT: vwredsum.vs v10, v8, v10, v0.t1713; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1714; RV64-NEXT: vmv.x.s a0, v101715; RV64-NEXT: ret1716 %e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>1717 %r = call i64 @llvm.vp.reduce.add.nxv4i64(i64 %s, <vscale x 4 x i64> %e, <vscale x 4 x i1> %m, i32 %evl)1718 ret i64 %r1719}1720 1721define signext i64 @vpwreduce_uadd_nxv4i32(i64 signext %s, <vscale x 4 x i32> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1722; RV32-LABEL: vpwreduce_uadd_nxv4i32:1723; RV32: # %bb.0:1724; RV32-NEXT: addi sp, sp, -161725; RV32-NEXT: .cfi_def_cfa_offset 161726; RV32-NEXT: sw a0, 8(sp)1727; RV32-NEXT: sw a1, 12(sp)1728; RV32-NEXT: addi a0, sp, 81729; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1730; RV32-NEXT: vlse64.v v10, (a0), zero1731; RV32-NEXT: li a1, 321732; RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma1733; RV32-NEXT: vwredsumu.vs v10, v8, v10, v0.t1734; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1735; RV32-NEXT: vmv.x.s a0, v101736; RV32-NEXT: vsrl.vx v8, v10, a11737; RV32-NEXT: vmv.x.s a1, v81738; RV32-NEXT: addi sp, sp, 161739; RV32-NEXT: .cfi_def_cfa_offset 01740; RV32-NEXT: ret1741;1742; RV64-LABEL: vpwreduce_uadd_nxv4i32:1743; RV64: # %bb.0:1744; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1745; RV64-NEXT: vmv.s.x v10, a01746; RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma1747; RV64-NEXT: vwredsumu.vs v10, v8, v10, v0.t1748; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1749; RV64-NEXT: vmv.x.s a0, v101750; RV64-NEXT: ret1751 %e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>1752 %r = call i64 @llvm.vp.reduce.add.nxv4i64(i64 %s, <vscale x 4 x i64> %e, <vscale x 4 x i1> %m, i32 %evl)1753 ret i64 %r1754}1755 1756define signext i64 @vpreduce_umax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1757; RV32-LABEL: vpreduce_umax_nxv4i64:1758; RV32: # %bb.0:1759; RV32-NEXT: addi sp, sp, -161760; RV32-NEXT: .cfi_def_cfa_offset 161761; RV32-NEXT: sw a0, 8(sp)1762; RV32-NEXT: sw a1, 12(sp)1763; RV32-NEXT: addi a0, sp, 81764; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1765; RV32-NEXT: vlse64.v v12, (a0), zero1766; RV32-NEXT: li a1, 321767; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1768; RV32-NEXT: vredmaxu.vs v12, v8, v12, v0.t1769; RV32-NEXT: vmv.x.s a0, v121770; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1771; RV32-NEXT: vsrl.vx v8, v12, a11772; RV32-NEXT: vmv.x.s a1, v81773; RV32-NEXT: addi sp, sp, 161774; RV32-NEXT: .cfi_def_cfa_offset 01775; RV32-NEXT: ret1776;1777; RV64-LABEL: vpreduce_umax_nxv4i64:1778; RV64: # %bb.0:1779; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1780; RV64-NEXT: vmv.s.x v12, a01781; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1782; RV64-NEXT: vredmaxu.vs v12, v8, v12, v0.t1783; RV64-NEXT: vmv.x.s a0, v121784; RV64-NEXT: ret1785 %r = call i64 @llvm.vp.reduce.umax.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1786 ret i64 %r1787}1788 1789define signext i64 @vpreduce_smax_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1790; RV32-LABEL: vpreduce_smax_nxv4i64:1791; RV32: # %bb.0:1792; RV32-NEXT: addi sp, sp, -161793; RV32-NEXT: .cfi_def_cfa_offset 161794; RV32-NEXT: sw a0, 8(sp)1795; RV32-NEXT: sw a1, 12(sp)1796; RV32-NEXT: addi a0, sp, 81797; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1798; RV32-NEXT: vlse64.v v12, (a0), zero1799; RV32-NEXT: li a1, 321800; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1801; RV32-NEXT: vredmax.vs v12, v8, v12, v0.t1802; RV32-NEXT: vmv.x.s a0, v121803; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1804; RV32-NEXT: vsrl.vx v8, v12, a11805; RV32-NEXT: vmv.x.s a1, v81806; RV32-NEXT: addi sp, sp, 161807; RV32-NEXT: .cfi_def_cfa_offset 01808; RV32-NEXT: ret1809;1810; RV64-LABEL: vpreduce_smax_nxv4i64:1811; RV64: # %bb.0:1812; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1813; RV64-NEXT: vmv.s.x v12, a01814; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1815; RV64-NEXT: vredmax.vs v12, v8, v12, v0.t1816; RV64-NEXT: vmv.x.s a0, v121817; RV64-NEXT: ret1818 %r = call i64 @llvm.vp.reduce.smax.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1819 ret i64 %r1820}1821 1822define signext i64 @vpreduce_umin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1823; RV32-LABEL: vpreduce_umin_nxv4i64:1824; RV32: # %bb.0:1825; RV32-NEXT: addi sp, sp, -161826; RV32-NEXT: .cfi_def_cfa_offset 161827; RV32-NEXT: sw a0, 8(sp)1828; RV32-NEXT: sw a1, 12(sp)1829; RV32-NEXT: addi a0, sp, 81830; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1831; RV32-NEXT: vlse64.v v12, (a0), zero1832; RV32-NEXT: li a1, 321833; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1834; RV32-NEXT: vredminu.vs v12, v8, v12, v0.t1835; RV32-NEXT: vmv.x.s a0, v121836; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1837; RV32-NEXT: vsrl.vx v8, v12, a11838; RV32-NEXT: vmv.x.s a1, v81839; RV32-NEXT: addi sp, sp, 161840; RV32-NEXT: .cfi_def_cfa_offset 01841; RV32-NEXT: ret1842;1843; RV64-LABEL: vpreduce_umin_nxv4i64:1844; RV64: # %bb.0:1845; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1846; RV64-NEXT: vmv.s.x v12, a01847; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1848; RV64-NEXT: vredminu.vs v12, v8, v12, v0.t1849; RV64-NEXT: vmv.x.s a0, v121850; RV64-NEXT: ret1851 %r = call i64 @llvm.vp.reduce.umin.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1852 ret i64 %r1853}1854 1855define signext i64 @vpreduce_smin_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1856; RV32-LABEL: vpreduce_smin_nxv4i64:1857; RV32: # %bb.0:1858; RV32-NEXT: addi sp, sp, -161859; RV32-NEXT: .cfi_def_cfa_offset 161860; RV32-NEXT: sw a0, 8(sp)1861; RV32-NEXT: sw a1, 12(sp)1862; RV32-NEXT: addi a0, sp, 81863; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1864; RV32-NEXT: vlse64.v v12, (a0), zero1865; RV32-NEXT: li a1, 321866; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1867; RV32-NEXT: vredmin.vs v12, v8, v12, v0.t1868; RV32-NEXT: vmv.x.s a0, v121869; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1870; RV32-NEXT: vsrl.vx v8, v12, a11871; RV32-NEXT: vmv.x.s a1, v81872; RV32-NEXT: addi sp, sp, 161873; RV32-NEXT: .cfi_def_cfa_offset 01874; RV32-NEXT: ret1875;1876; RV64-LABEL: vpreduce_smin_nxv4i64:1877; RV64: # %bb.0:1878; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1879; RV64-NEXT: vmv.s.x v12, a01880; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1881; RV64-NEXT: vredmin.vs v12, v8, v12, v0.t1882; RV64-NEXT: vmv.x.s a0, v121883; RV64-NEXT: ret1884 %r = call i64 @llvm.vp.reduce.smin.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1885 ret i64 %r1886}1887 1888define signext i64 @vpreduce_and_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1889; RV32-LABEL: vpreduce_and_nxv4i64:1890; RV32: # %bb.0:1891; RV32-NEXT: addi sp, sp, -161892; RV32-NEXT: .cfi_def_cfa_offset 161893; RV32-NEXT: sw a0, 8(sp)1894; RV32-NEXT: sw a1, 12(sp)1895; RV32-NEXT: addi a0, sp, 81896; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1897; RV32-NEXT: vlse64.v v12, (a0), zero1898; RV32-NEXT: li a1, 321899; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1900; RV32-NEXT: vredand.vs v12, v8, v12, v0.t1901; RV32-NEXT: vmv.x.s a0, v121902; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1903; RV32-NEXT: vsrl.vx v8, v12, a11904; RV32-NEXT: vmv.x.s a1, v81905; RV32-NEXT: addi sp, sp, 161906; RV32-NEXT: .cfi_def_cfa_offset 01907; RV32-NEXT: ret1908;1909; RV64-LABEL: vpreduce_and_nxv4i64:1910; RV64: # %bb.0:1911; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1912; RV64-NEXT: vmv.s.x v12, a01913; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1914; RV64-NEXT: vredand.vs v12, v8, v12, v0.t1915; RV64-NEXT: vmv.x.s a0, v121916; RV64-NEXT: ret1917 %r = call i64 @llvm.vp.reduce.and.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1918 ret i64 %r1919}1920 1921define signext i64 @vpreduce_or_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1922; RV32-LABEL: vpreduce_or_nxv4i64:1923; RV32: # %bb.0:1924; RV32-NEXT: addi sp, sp, -161925; RV32-NEXT: .cfi_def_cfa_offset 161926; RV32-NEXT: sw a0, 8(sp)1927; RV32-NEXT: sw a1, 12(sp)1928; RV32-NEXT: addi a0, sp, 81929; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1930; RV32-NEXT: vlse64.v v12, (a0), zero1931; RV32-NEXT: li a1, 321932; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1933; RV32-NEXT: vredor.vs v12, v8, v12, v0.t1934; RV32-NEXT: vmv.x.s a0, v121935; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1936; RV32-NEXT: vsrl.vx v8, v12, a11937; RV32-NEXT: vmv.x.s a1, v81938; RV32-NEXT: addi sp, sp, 161939; RV32-NEXT: .cfi_def_cfa_offset 01940; RV32-NEXT: ret1941;1942; RV64-LABEL: vpreduce_or_nxv4i64:1943; RV64: # %bb.0:1944; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1945; RV64-NEXT: vmv.s.x v12, a01946; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1947; RV64-NEXT: vredor.vs v12, v8, v12, v0.t1948; RV64-NEXT: vmv.x.s a0, v121949; RV64-NEXT: ret1950 %r = call i64 @llvm.vp.reduce.or.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1951 ret i64 %r1952}1953 1954define signext i64 @vpreduce_xor_nxv4i64(i64 signext %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {1955; RV32-LABEL: vpreduce_xor_nxv4i64:1956; RV32: # %bb.0:1957; RV32-NEXT: addi sp, sp, -161958; RV32-NEXT: .cfi_def_cfa_offset 161959; RV32-NEXT: sw a0, 8(sp)1960; RV32-NEXT: sw a1, 12(sp)1961; RV32-NEXT: addi a0, sp, 81962; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1963; RV32-NEXT: vlse64.v v12, (a0), zero1964; RV32-NEXT: li a1, 321965; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1966; RV32-NEXT: vredxor.vs v12, v8, v12, v0.t1967; RV32-NEXT: vmv.x.s a0, v121968; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1969; RV32-NEXT: vsrl.vx v8, v12, a11970; RV32-NEXT: vmv.x.s a1, v81971; RV32-NEXT: addi sp, sp, 161972; RV32-NEXT: .cfi_def_cfa_offset 01973; RV32-NEXT: ret1974;1975; RV64-LABEL: vpreduce_xor_nxv4i64:1976; RV64: # %bb.0:1977; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma1978; RV64-NEXT: vmv.s.x v12, a01979; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1980; RV64-NEXT: vredxor.vs v12, v8, v12, v0.t1981; RV64-NEXT: vmv.x.s a0, v121982; RV64-NEXT: ret1983 %r = call i64 @llvm.vp.reduce.xor.nxv4i64(i64 %s, <vscale x 4 x i64> %v, <vscale x 4 x i1> %m, i32 %evl)1984 ret i64 %r1985}1986