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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define signext i8 @vreduce_add_nxv1i8(<vscale x 1 x i8> %v) {8; CHECK-LABEL: vreduce_add_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vmv.s.x v9, zero12; CHECK-NEXT: vredsum.vs v8, v8, v913; CHECK-NEXT: vmv.x.s a0, v814; CHECK-NEXT: ret15 %red = call i8 @llvm.vector.reduce.add.nxv1i8(<vscale x 1 x i8> %v)16 ret i8 %red17}18 19define signext i8 @vreduce_umax_nxv1i8(<vscale x 1 x i8> %v) {20; CHECK-LABEL: vreduce_umax_nxv1i8:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma23; CHECK-NEXT: vredmaxu.vs v8, v8, v824; CHECK-NEXT: vmv.x.s a0, v825; CHECK-NEXT: ret26 %red = call i8 @llvm.vector.reduce.umax.nxv1i8(<vscale x 1 x i8> %v)27 ret i8 %red28}29 30define signext i8 @vreduce_smax_nxv1i8(<vscale x 1 x i8> %v) {31; CHECK-LABEL: vreduce_smax_nxv1i8:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma34; CHECK-NEXT: vredmax.vs v8, v8, v835; CHECK-NEXT: vmv.x.s a0, v836; CHECK-NEXT: ret37 %red = call i8 @llvm.vector.reduce.smax.nxv1i8(<vscale x 1 x i8> %v)38 ret i8 %red39}40 41define signext i8 @vreduce_umin_nxv1i8(<vscale x 1 x i8> %v) {42; CHECK-LABEL: vreduce_umin_nxv1i8:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma45; CHECK-NEXT: vredminu.vs v8, v8, v846; CHECK-NEXT: vmv.x.s a0, v847; CHECK-NEXT: ret48 %red = call i8 @llvm.vector.reduce.umin.nxv1i8(<vscale x 1 x i8> %v)49 ret i8 %red50}51 52define signext i8 @vreduce_smin_nxv1i8(<vscale x 1 x i8> %v) {53; CHECK-LABEL: vreduce_smin_nxv1i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma56; CHECK-NEXT: vredmin.vs v8, v8, v857; CHECK-NEXT: vmv.x.s a0, v858; CHECK-NEXT: ret59 %red = call i8 @llvm.vector.reduce.smin.nxv1i8(<vscale x 1 x i8> %v)60 ret i8 %red61}62 63define signext i8 @vreduce_and_nxv1i8(<vscale x 1 x i8> %v) {64; CHECK-LABEL: vreduce_and_nxv1i8:65; CHECK: # %bb.0:66; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma67; CHECK-NEXT: vredand.vs v8, v8, v868; CHECK-NEXT: vmv.x.s a0, v869; CHECK-NEXT: ret70 %red = call i8 @llvm.vector.reduce.and.nxv1i8(<vscale x 1 x i8> %v)71 ret i8 %red72}73 74define signext i8 @vreduce_or_nxv1i8(<vscale x 1 x i8> %v) {75; CHECK-LABEL: vreduce_or_nxv1i8:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma78; CHECK-NEXT: vredor.vs v8, v8, v879; CHECK-NEXT: vmv.x.s a0, v880; CHECK-NEXT: ret81 %red = call i8 @llvm.vector.reduce.or.nxv1i8(<vscale x 1 x i8> %v)82 ret i8 %red83}84 85define signext i8 @vreduce_xor_nxv1i8(<vscale x 1 x i8> %v) {86; CHECK-LABEL: vreduce_xor_nxv1i8:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma89; CHECK-NEXT: vmv.s.x v9, zero90; CHECK-NEXT: vredxor.vs v8, v8, v991; CHECK-NEXT: vmv.x.s a0, v892; CHECK-NEXT: ret93 %red = call i8 @llvm.vector.reduce.xor.nxv1i8(<vscale x 1 x i8> %v)94 ret i8 %red95}96 97define signext i8 @vreduce_add_nxv2i8(<vscale x 2 x i8> %v) {98; CHECK-LABEL: vreduce_add_nxv2i8:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma101; CHECK-NEXT: vmv.s.x v9, zero102; CHECK-NEXT: vredsum.vs v8, v8, v9103; CHECK-NEXT: vmv.x.s a0, v8104; CHECK-NEXT: ret105 %red = call i8 @llvm.vector.reduce.add.nxv2i8(<vscale x 2 x i8> %v)106 ret i8 %red107}108 109define signext i8 @vreduce_umax_nxv2i8(<vscale x 2 x i8> %v) {110; CHECK-LABEL: vreduce_umax_nxv2i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma113; CHECK-NEXT: vredmaxu.vs v8, v8, v8114; CHECK-NEXT: vmv.x.s a0, v8115; CHECK-NEXT: ret116 %red = call i8 @llvm.vector.reduce.umax.nxv2i8(<vscale x 2 x i8> %v)117 ret i8 %red118}119 120define signext i8 @vreduce_smax_nxv2i8(<vscale x 2 x i8> %v) {121; CHECK-LABEL: vreduce_smax_nxv2i8:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma124; CHECK-NEXT: vredmax.vs v8, v8, v8125; CHECK-NEXT: vmv.x.s a0, v8126; CHECK-NEXT: ret127 %red = call i8 @llvm.vector.reduce.smax.nxv2i8(<vscale x 2 x i8> %v)128 ret i8 %red129}130 131define signext i8 @vreduce_umin_nxv2i8(<vscale x 2 x i8> %v) {132; CHECK-LABEL: vreduce_umin_nxv2i8:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma135; CHECK-NEXT: vredminu.vs v8, v8, v8136; CHECK-NEXT: vmv.x.s a0, v8137; CHECK-NEXT: ret138 %red = call i8 @llvm.vector.reduce.umin.nxv2i8(<vscale x 2 x i8> %v)139 ret i8 %red140}141 142define signext i8 @vreduce_smin_nxv2i8(<vscale x 2 x i8> %v) {143; CHECK-LABEL: vreduce_smin_nxv2i8:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma146; CHECK-NEXT: vredmin.vs v8, v8, v8147; CHECK-NEXT: vmv.x.s a0, v8148; CHECK-NEXT: ret149 %red = call i8 @llvm.vector.reduce.smin.nxv2i8(<vscale x 2 x i8> %v)150 ret i8 %red151}152 153define signext i8 @vreduce_and_nxv2i8(<vscale x 2 x i8> %v) {154; CHECK-LABEL: vreduce_and_nxv2i8:155; CHECK: # %bb.0:156; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma157; CHECK-NEXT: vredand.vs v8, v8, v8158; CHECK-NEXT: vmv.x.s a0, v8159; CHECK-NEXT: ret160 %red = call i8 @llvm.vector.reduce.and.nxv2i8(<vscale x 2 x i8> %v)161 ret i8 %red162}163 164define signext i8 @vreduce_or_nxv2i8(<vscale x 2 x i8> %v) {165; CHECK-LABEL: vreduce_or_nxv2i8:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma168; CHECK-NEXT: vredor.vs v8, v8, v8169; CHECK-NEXT: vmv.x.s a0, v8170; CHECK-NEXT: ret171 %red = call i8 @llvm.vector.reduce.or.nxv2i8(<vscale x 2 x i8> %v)172 ret i8 %red173}174 175define signext i8 @vreduce_xor_nxv2i8(<vscale x 2 x i8> %v) {176; CHECK-LABEL: vreduce_xor_nxv2i8:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma179; CHECK-NEXT: vmv.s.x v9, zero180; CHECK-NEXT: vredxor.vs v8, v8, v9181; CHECK-NEXT: vmv.x.s a0, v8182; CHECK-NEXT: ret183 %red = call i8 @llvm.vector.reduce.xor.nxv2i8(<vscale x 2 x i8> %v)184 ret i8 %red185}186 187define signext i8 @vreduce_add_nxv4i8(<vscale x 4 x i8> %v) {188; CHECK-LABEL: vreduce_add_nxv4i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma191; CHECK-NEXT: vmv.s.x v9, zero192; CHECK-NEXT: vredsum.vs v8, v8, v9193; CHECK-NEXT: vmv.x.s a0, v8194; CHECK-NEXT: ret195 %red = call i8 @llvm.vector.reduce.add.nxv4i8(<vscale x 4 x i8> %v)196 ret i8 %red197}198 199define signext i8 @vreduce_umax_nxv4i8(<vscale x 4 x i8> %v) {200; CHECK-LABEL: vreduce_umax_nxv4i8:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma203; CHECK-NEXT: vredmaxu.vs v8, v8, v8204; CHECK-NEXT: vmv.x.s a0, v8205; CHECK-NEXT: ret206 %red = call i8 @llvm.vector.reduce.umax.nxv4i8(<vscale x 4 x i8> %v)207 ret i8 %red208}209 210define signext i8 @vreduce_smax_nxv4i8(<vscale x 4 x i8> %v) {211; CHECK-LABEL: vreduce_smax_nxv4i8:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma214; CHECK-NEXT: vredmax.vs v8, v8, v8215; CHECK-NEXT: vmv.x.s a0, v8216; CHECK-NEXT: ret217 %red = call i8 @llvm.vector.reduce.smax.nxv4i8(<vscale x 4 x i8> %v)218 ret i8 %red219}220 221define signext i8 @vreduce_umin_nxv4i8(<vscale x 4 x i8> %v) {222; CHECK-LABEL: vreduce_umin_nxv4i8:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma225; CHECK-NEXT: vredminu.vs v8, v8, v8226; CHECK-NEXT: vmv.x.s a0, v8227; CHECK-NEXT: ret228 %red = call i8 @llvm.vector.reduce.umin.nxv4i8(<vscale x 4 x i8> %v)229 ret i8 %red230}231 232define signext i8 @vreduce_smin_nxv4i8(<vscale x 4 x i8> %v) {233; CHECK-LABEL: vreduce_smin_nxv4i8:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma236; CHECK-NEXT: vredmin.vs v8, v8, v8237; CHECK-NEXT: vmv.x.s a0, v8238; CHECK-NEXT: ret239 %red = call i8 @llvm.vector.reduce.smin.nxv4i8(<vscale x 4 x i8> %v)240 ret i8 %red241}242 243define signext i8 @vreduce_and_nxv4i8(<vscale x 4 x i8> %v) {244; CHECK-LABEL: vreduce_and_nxv4i8:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma247; CHECK-NEXT: vredand.vs v8, v8, v8248; CHECK-NEXT: vmv.x.s a0, v8249; CHECK-NEXT: ret250 %red = call i8 @llvm.vector.reduce.and.nxv4i8(<vscale x 4 x i8> %v)251 ret i8 %red252}253 254define signext i8 @vreduce_or_nxv4i8(<vscale x 4 x i8> %v) {255; CHECK-LABEL: vreduce_or_nxv4i8:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma258; CHECK-NEXT: vredor.vs v8, v8, v8259; CHECK-NEXT: vmv.x.s a0, v8260; CHECK-NEXT: ret261 %red = call i8 @llvm.vector.reduce.or.nxv4i8(<vscale x 4 x i8> %v)262 ret i8 %red263}264 265define signext i8 @vreduce_xor_nxv4i8(<vscale x 4 x i8> %v) {266; CHECK-LABEL: vreduce_xor_nxv4i8:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma269; CHECK-NEXT: vmv.s.x v9, zero270; CHECK-NEXT: vredxor.vs v8, v8, v9271; CHECK-NEXT: vmv.x.s a0, v8272; CHECK-NEXT: ret273 %red = call i8 @llvm.vector.reduce.xor.nxv4i8(<vscale x 4 x i8> %v)274 ret i8 %red275}276 277define signext i16 @vreduce_add_nxv1i16(<vscale x 1 x i16> %v) {278; CHECK-LABEL: vreduce_add_nxv1i16:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma281; CHECK-NEXT: vmv.s.x v9, zero282; CHECK-NEXT: vredsum.vs v8, v8, v9283; CHECK-NEXT: vmv.x.s a0, v8284; CHECK-NEXT: ret285 %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %v)286 ret i16 %red287}288 289define signext i16 @vwreduce_add_nxv1i8(<vscale x 1 x i8> %v) {290; CHECK-LABEL: vwreduce_add_nxv1i8:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma293; CHECK-NEXT: vmv.s.x v9, zero294; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma295; CHECK-NEXT: vwredsum.vs v8, v8, v9296; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma297; CHECK-NEXT: vmv.x.s a0, v8298; CHECK-NEXT: ret299 %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>300 %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %e)301 ret i16 %red302}303 304define signext i16 @vwreduce_uadd_nxv1i8(<vscale x 1 x i8> %v) {305; CHECK-LABEL: vwreduce_uadd_nxv1i8:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma308; CHECK-NEXT: vmv.s.x v9, zero309; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma310; CHECK-NEXT: vwredsum.vs v8, v8, v9311; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma312; CHECK-NEXT: vmv.x.s a0, v8313; CHECK-NEXT: ret314 %e = sext <vscale x 1 x i8> %v to <vscale x 1 x i16>315 %red = call i16 @llvm.vector.reduce.add.nxv1i16(<vscale x 1 x i16> %e)316 ret i16 %red317}318 319define signext i16 @vreduce_umax_nxv1i16(<vscale x 1 x i16> %v) {320; CHECK-LABEL: vreduce_umax_nxv1i16:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma323; CHECK-NEXT: vredmaxu.vs v8, v8, v8324; CHECK-NEXT: vmv.x.s a0, v8325; CHECK-NEXT: ret326 %red = call i16 @llvm.vector.reduce.umax.nxv1i16(<vscale x 1 x i16> %v)327 ret i16 %red328}329 330define signext i16 @vreduce_smax_nxv1i16(<vscale x 1 x i16> %v) {331; CHECK-LABEL: vreduce_smax_nxv1i16:332; CHECK: # %bb.0:333; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma334; CHECK-NEXT: vredmax.vs v8, v8, v8335; CHECK-NEXT: vmv.x.s a0, v8336; CHECK-NEXT: ret337 %red = call i16 @llvm.vector.reduce.smax.nxv1i16(<vscale x 1 x i16> %v)338 ret i16 %red339}340 341define signext i16 @vreduce_umin_nxv1i16(<vscale x 1 x i16> %v) {342; CHECK-LABEL: vreduce_umin_nxv1i16:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma345; CHECK-NEXT: vredminu.vs v8, v8, v8346; CHECK-NEXT: vmv.x.s a0, v8347; CHECK-NEXT: ret348 %red = call i16 @llvm.vector.reduce.umin.nxv1i16(<vscale x 1 x i16> %v)349 ret i16 %red350}351 352define signext i16 @vreduce_smin_nxv1i16(<vscale x 1 x i16> %v) {353; CHECK-LABEL: vreduce_smin_nxv1i16:354; CHECK: # %bb.0:355; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma356; CHECK-NEXT: vredmin.vs v8, v8, v8357; CHECK-NEXT: vmv.x.s a0, v8358; CHECK-NEXT: ret359 %red = call i16 @llvm.vector.reduce.smin.nxv1i16(<vscale x 1 x i16> %v)360 ret i16 %red361}362 363define signext i16 @vreduce_and_nxv1i16(<vscale x 1 x i16> %v) {364; CHECK-LABEL: vreduce_and_nxv1i16:365; CHECK: # %bb.0:366; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma367; CHECK-NEXT: vredand.vs v8, v8, v8368; CHECK-NEXT: vmv.x.s a0, v8369; CHECK-NEXT: ret370 %red = call i16 @llvm.vector.reduce.and.nxv1i16(<vscale x 1 x i16> %v)371 ret i16 %red372}373 374define signext i16 @vreduce_or_nxv1i16(<vscale x 1 x i16> %v) {375; CHECK-LABEL: vreduce_or_nxv1i16:376; CHECK: # %bb.0:377; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma378; CHECK-NEXT: vredor.vs v8, v8, v8379; CHECK-NEXT: vmv.x.s a0, v8380; CHECK-NEXT: ret381 %red = call i16 @llvm.vector.reduce.or.nxv1i16(<vscale x 1 x i16> %v)382 ret i16 %red383}384 385define signext i16 @vreduce_xor_nxv1i16(<vscale x 1 x i16> %v) {386; CHECK-LABEL: vreduce_xor_nxv1i16:387; CHECK: # %bb.0:388; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma389; CHECK-NEXT: vmv.s.x v9, zero390; CHECK-NEXT: vredxor.vs v8, v8, v9391; CHECK-NEXT: vmv.x.s a0, v8392; CHECK-NEXT: ret393 %red = call i16 @llvm.vector.reduce.xor.nxv1i16(<vscale x 1 x i16> %v)394 ret i16 %red395}396 397define signext i16 @vreduce_add_nxv2i16(<vscale x 2 x i16> %v) {398; CHECK-LABEL: vreduce_add_nxv2i16:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma401; CHECK-NEXT: vmv.s.x v9, zero402; CHECK-NEXT: vredsum.vs v8, v8, v9403; CHECK-NEXT: vmv.x.s a0, v8404; CHECK-NEXT: ret405 %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %v)406 ret i16 %red407}408 409define signext i16 @vwreduce_add_nxv2i8(<vscale x 2 x i8> %v) {410; CHECK-LABEL: vwreduce_add_nxv2i8:411; CHECK: # %bb.0:412; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma413; CHECK-NEXT: vmv.s.x v9, zero414; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma415; CHECK-NEXT: vwredsum.vs v8, v8, v9416; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma417; CHECK-NEXT: vmv.x.s a0, v8418; CHECK-NEXT: ret419 %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>420 %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %e)421 ret i16 %red422}423 424define signext i16 @vwreduce_uadd_nxv2i8(<vscale x 2 x i8> %v) {425; CHECK-LABEL: vwreduce_uadd_nxv2i8:426; CHECK: # %bb.0:427; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma428; CHECK-NEXT: vmv.s.x v9, zero429; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma430; CHECK-NEXT: vwredsum.vs v8, v8, v9431; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma432; CHECK-NEXT: vmv.x.s a0, v8433; CHECK-NEXT: ret434 %e = sext <vscale x 2 x i8> %v to <vscale x 2 x i16>435 %red = call i16 @llvm.vector.reduce.add.nxv2i16(<vscale x 2 x i16> %e)436 ret i16 %red437}438 439define signext i16 @vreduce_umax_nxv2i16(<vscale x 2 x i16> %v) {440; CHECK-LABEL: vreduce_umax_nxv2i16:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma443; CHECK-NEXT: vredmaxu.vs v8, v8, v8444; CHECK-NEXT: vmv.x.s a0, v8445; CHECK-NEXT: ret446 %red = call i16 @llvm.vector.reduce.umax.nxv2i16(<vscale x 2 x i16> %v)447 ret i16 %red448}449 450define signext i16 @vreduce_smax_nxv2i16(<vscale x 2 x i16> %v) {451; CHECK-LABEL: vreduce_smax_nxv2i16:452; CHECK: # %bb.0:453; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma454; CHECK-NEXT: vredmax.vs v8, v8, v8455; CHECK-NEXT: vmv.x.s a0, v8456; CHECK-NEXT: ret457 %red = call i16 @llvm.vector.reduce.smax.nxv2i16(<vscale x 2 x i16> %v)458 ret i16 %red459}460 461define signext i16 @vreduce_umin_nxv2i16(<vscale x 2 x i16> %v) {462; CHECK-LABEL: vreduce_umin_nxv2i16:463; CHECK: # %bb.0:464; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma465; CHECK-NEXT: vredminu.vs v8, v8, v8466; CHECK-NEXT: vmv.x.s a0, v8467; CHECK-NEXT: ret468 %red = call i16 @llvm.vector.reduce.umin.nxv2i16(<vscale x 2 x i16> %v)469 ret i16 %red470}471 472define signext i16 @vreduce_smin_nxv2i16(<vscale x 2 x i16> %v) {473; CHECK-LABEL: vreduce_smin_nxv2i16:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma476; CHECK-NEXT: vredmin.vs v8, v8, v8477; CHECK-NEXT: vmv.x.s a0, v8478; CHECK-NEXT: ret479 %red = call i16 @llvm.vector.reduce.smin.nxv2i16(<vscale x 2 x i16> %v)480 ret i16 %red481}482 483define signext i16 @vreduce_and_nxv2i16(<vscale x 2 x i16> %v) {484; CHECK-LABEL: vreduce_and_nxv2i16:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma487; CHECK-NEXT: vredand.vs v8, v8, v8488; CHECK-NEXT: vmv.x.s a0, v8489; CHECK-NEXT: ret490 %red = call i16 @llvm.vector.reduce.and.nxv2i16(<vscale x 2 x i16> %v)491 ret i16 %red492}493 494define signext i16 @vreduce_or_nxv2i16(<vscale x 2 x i16> %v) {495; CHECK-LABEL: vreduce_or_nxv2i16:496; CHECK: # %bb.0:497; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma498; CHECK-NEXT: vredor.vs v8, v8, v8499; CHECK-NEXT: vmv.x.s a0, v8500; CHECK-NEXT: ret501 %red = call i16 @llvm.vector.reduce.or.nxv2i16(<vscale x 2 x i16> %v)502 ret i16 %red503}504 505define signext i16 @vreduce_xor_nxv2i16(<vscale x 2 x i16> %v) {506; CHECK-LABEL: vreduce_xor_nxv2i16:507; CHECK: # %bb.0:508; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma509; CHECK-NEXT: vmv.s.x v9, zero510; CHECK-NEXT: vredxor.vs v8, v8, v9511; CHECK-NEXT: vmv.x.s a0, v8512; CHECK-NEXT: ret513 %red = call i16 @llvm.vector.reduce.xor.nxv2i16(<vscale x 2 x i16> %v)514 ret i16 %red515}516 517define signext i16 @vreduce_add_nxv4i16(<vscale x 4 x i16> %v) {518; CHECK-LABEL: vreduce_add_nxv4i16:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma521; CHECK-NEXT: vmv.s.x v9, zero522; CHECK-NEXT: vredsum.vs v8, v8, v9523; CHECK-NEXT: vmv.x.s a0, v8524; CHECK-NEXT: ret525 %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %v)526 ret i16 %red527}528 529define signext i16 @vwreduce_add_nxv4i8(<vscale x 4 x i8> %v) {530; CHECK-LABEL: vwreduce_add_nxv4i8:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma533; CHECK-NEXT: vmv.s.x v9, zero534; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma535; CHECK-NEXT: vwredsum.vs v8, v8, v9536; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma537; CHECK-NEXT: vmv.x.s a0, v8538; CHECK-NEXT: ret539 %e = sext <vscale x 4 x i8> %v to <vscale x 4 x i16>540 %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %e)541 ret i16 %red542}543 544define signext i16 @vwreduce_uadd_nxv4i8(<vscale x 4 x i8> %v) {545; CHECK-LABEL: vwreduce_uadd_nxv4i8:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma548; CHECK-NEXT: vmv.s.x v9, zero549; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma550; CHECK-NEXT: vwredsum.vs v8, v8, v9551; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma552; CHECK-NEXT: vmv.x.s a0, v8553; CHECK-NEXT: ret554 %e = sext <vscale x 4 x i8> %v to <vscale x 4 x i16>555 %red = call i16 @llvm.vector.reduce.add.nxv4i16(<vscale x 4 x i16> %e)556 ret i16 %red557}558 559define signext i16 @vreduce_umax_nxv4i16(<vscale x 4 x i16> %v) {560; CHECK-LABEL: vreduce_umax_nxv4i16:561; CHECK: # %bb.0:562; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma563; CHECK-NEXT: vredmaxu.vs v8, v8, v8564; CHECK-NEXT: vmv.x.s a0, v8565; CHECK-NEXT: ret566 %red = call i16 @llvm.vector.reduce.umax.nxv4i16(<vscale x 4 x i16> %v)567 ret i16 %red568}569 570define signext i16 @vreduce_smax_nxv4i16(<vscale x 4 x i16> %v) {571; CHECK-LABEL: vreduce_smax_nxv4i16:572; CHECK: # %bb.0:573; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma574; CHECK-NEXT: vredmax.vs v8, v8, v8575; CHECK-NEXT: vmv.x.s a0, v8576; CHECK-NEXT: ret577 %red = call i16 @llvm.vector.reduce.smax.nxv4i16(<vscale x 4 x i16> %v)578 ret i16 %red579}580 581define signext i16 @vreduce_umin_nxv4i16(<vscale x 4 x i16> %v) {582; CHECK-LABEL: vreduce_umin_nxv4i16:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma585; CHECK-NEXT: vredminu.vs v8, v8, v8586; CHECK-NEXT: vmv.x.s a0, v8587; CHECK-NEXT: ret588 %red = call i16 @llvm.vector.reduce.umin.nxv4i16(<vscale x 4 x i16> %v)589 ret i16 %red590}591 592define signext i16 @vreduce_smin_nxv4i16(<vscale x 4 x i16> %v) {593; CHECK-LABEL: vreduce_smin_nxv4i16:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma596; CHECK-NEXT: vredmin.vs v8, v8, v8597; CHECK-NEXT: vmv.x.s a0, v8598; CHECK-NEXT: ret599 %red = call i16 @llvm.vector.reduce.smin.nxv4i16(<vscale x 4 x i16> %v)600 ret i16 %red601}602 603define signext i16 @vreduce_and_nxv4i16(<vscale x 4 x i16> %v) {604; CHECK-LABEL: vreduce_and_nxv4i16:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma607; CHECK-NEXT: vredand.vs v8, v8, v8608; CHECK-NEXT: vmv.x.s a0, v8609; CHECK-NEXT: ret610 %red = call i16 @llvm.vector.reduce.and.nxv4i16(<vscale x 4 x i16> %v)611 ret i16 %red612}613 614define signext i16 @vreduce_or_nxv4i16(<vscale x 4 x i16> %v) {615; CHECK-LABEL: vreduce_or_nxv4i16:616; CHECK: # %bb.0:617; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma618; CHECK-NEXT: vredor.vs v8, v8, v8619; CHECK-NEXT: vmv.x.s a0, v8620; CHECK-NEXT: ret621 %red = call i16 @llvm.vector.reduce.or.nxv4i16(<vscale x 4 x i16> %v)622 ret i16 %red623}624 625define signext i16 @vreduce_xor_nxv4i16(<vscale x 4 x i16> %v) {626; CHECK-LABEL: vreduce_xor_nxv4i16:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma629; CHECK-NEXT: vmv.s.x v9, zero630; CHECK-NEXT: vredxor.vs v8, v8, v9631; CHECK-NEXT: vmv.x.s a0, v8632; CHECK-NEXT: ret633 %red = call i16 @llvm.vector.reduce.xor.nxv4i16(<vscale x 4 x i16> %v)634 ret i16 %red635}636 637define signext i32 @vreduce_add_nxv1i32(<vscale x 1 x i32> %v) {638; CHECK-LABEL: vreduce_add_nxv1i32:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma641; CHECK-NEXT: vmv.s.x v9, zero642; CHECK-NEXT: vredsum.vs v8, v8, v9643; CHECK-NEXT: vmv.x.s a0, v8644; CHECK-NEXT: ret645 %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %v)646 ret i32 %red647}648 649define signext i32 @vwreduce_add_nxv1i16(<vscale x 1 x i16> %v) {650; CHECK-LABEL: vwreduce_add_nxv1i16:651; CHECK: # %bb.0:652; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma653; CHECK-NEXT: vmv.s.x v9, zero654; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma655; CHECK-NEXT: vwredsum.vs v8, v8, v9656; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma657; CHECK-NEXT: vmv.x.s a0, v8658; CHECK-NEXT: ret659 %e = sext <vscale x 1 x i16> %v to <vscale x 1 x i32>660 %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %e)661 ret i32 %red662}663 664define signext i32 @vwreduce_uadd_nxv1i16(<vscale x 1 x i16> %v) {665; CHECK-LABEL: vwreduce_uadd_nxv1i16:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma668; CHECK-NEXT: vmv.s.x v9, zero669; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma670; CHECK-NEXT: vwredsumu.vs v8, v8, v9671; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma672; CHECK-NEXT: vmv.x.s a0, v8673; CHECK-NEXT: ret674 %e = zext <vscale x 1 x i16> %v to <vscale x 1 x i32>675 %red = call i32 @llvm.vector.reduce.add.nxv1i32(<vscale x 1 x i32> %e)676 ret i32 %red677}678 679define signext i32 @vreduce_umax_nxv1i32(<vscale x 1 x i32> %v) {680; CHECK-LABEL: vreduce_umax_nxv1i32:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma683; CHECK-NEXT: vredmaxu.vs v8, v8, v8684; CHECK-NEXT: vmv.x.s a0, v8685; CHECK-NEXT: ret686 %red = call i32 @llvm.vector.reduce.umax.nxv1i32(<vscale x 1 x i32> %v)687 ret i32 %red688}689 690define signext i32 @vreduce_smax_nxv1i32(<vscale x 1 x i32> %v) {691; CHECK-LABEL: vreduce_smax_nxv1i32:692; CHECK: # %bb.0:693; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma694; CHECK-NEXT: vredmax.vs v8, v8, v8695; CHECK-NEXT: vmv.x.s a0, v8696; CHECK-NEXT: ret697 %red = call i32 @llvm.vector.reduce.smax.nxv1i32(<vscale x 1 x i32> %v)698 ret i32 %red699}700 701define signext i32 @vreduce_umin_nxv1i32(<vscale x 1 x i32> %v) {702; CHECK-LABEL: vreduce_umin_nxv1i32:703; CHECK: # %bb.0:704; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma705; CHECK-NEXT: vredminu.vs v8, v8, v8706; CHECK-NEXT: vmv.x.s a0, v8707; CHECK-NEXT: ret708 %red = call i32 @llvm.vector.reduce.umin.nxv1i32(<vscale x 1 x i32> %v)709 ret i32 %red710}711 712define signext i32 @vreduce_smin_nxv1i32(<vscale x 1 x i32> %v) {713; CHECK-LABEL: vreduce_smin_nxv1i32:714; CHECK: # %bb.0:715; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma716; CHECK-NEXT: vredmin.vs v8, v8, v8717; CHECK-NEXT: vmv.x.s a0, v8718; CHECK-NEXT: ret719 %red = call i32 @llvm.vector.reduce.smin.nxv1i32(<vscale x 1 x i32> %v)720 ret i32 %red721}722 723define signext i32 @vreduce_and_nxv1i32(<vscale x 1 x i32> %v) {724; CHECK-LABEL: vreduce_and_nxv1i32:725; CHECK: # %bb.0:726; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma727; CHECK-NEXT: vredand.vs v8, v8, v8728; CHECK-NEXT: vmv.x.s a0, v8729; CHECK-NEXT: ret730 %red = call i32 @llvm.vector.reduce.and.nxv1i32(<vscale x 1 x i32> %v)731 ret i32 %red732}733 734define signext i32 @vreduce_or_nxv1i32(<vscale x 1 x i32> %v) {735; CHECK-LABEL: vreduce_or_nxv1i32:736; CHECK: # %bb.0:737; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma738; CHECK-NEXT: vredor.vs v8, v8, v8739; CHECK-NEXT: vmv.x.s a0, v8740; CHECK-NEXT: ret741 %red = call i32 @llvm.vector.reduce.or.nxv1i32(<vscale x 1 x i32> %v)742 ret i32 %red743}744 745define signext i32 @vreduce_xor_nxv1i32(<vscale x 1 x i32> %v) {746; CHECK-LABEL: vreduce_xor_nxv1i32:747; CHECK: # %bb.0:748; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma749; CHECK-NEXT: vmv.s.x v9, zero750; CHECK-NEXT: vredxor.vs v8, v8, v9751; CHECK-NEXT: vmv.x.s a0, v8752; CHECK-NEXT: ret753 %red = call i32 @llvm.vector.reduce.xor.nxv1i32(<vscale x 1 x i32> %v)754 ret i32 %red755}756 757define signext i32 @vreduce_add_nxv2i32(<vscale x 2 x i32> %v) {758; CHECK-LABEL: vreduce_add_nxv2i32:759; CHECK: # %bb.0:760; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma761; CHECK-NEXT: vmv.s.x v9, zero762; CHECK-NEXT: vredsum.vs v8, v8, v9763; CHECK-NEXT: vmv.x.s a0, v8764; CHECK-NEXT: ret765 %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %v)766 ret i32 %red767}768 769define signext i32 @vwreduce_add_nxv2i16(<vscale x 2 x i16> %v) {770; CHECK-LABEL: vwreduce_add_nxv2i16:771; CHECK: # %bb.0:772; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma773; CHECK-NEXT: vmv.s.x v9, zero774; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma775; CHECK-NEXT: vwredsum.vs v8, v8, v9776; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma777; CHECK-NEXT: vmv.x.s a0, v8778; CHECK-NEXT: ret779 %e = sext <vscale x 2 x i16> %v to <vscale x 2 x i32>780 %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %e)781 ret i32 %red782}783 784define signext i32 @vwreduce_uadd_nxv2i16(<vscale x 2 x i16> %v) {785; CHECK-LABEL: vwreduce_uadd_nxv2i16:786; CHECK: # %bb.0:787; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma788; CHECK-NEXT: vmv.s.x v9, zero789; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma790; CHECK-NEXT: vwredsumu.vs v8, v8, v9791; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma792; CHECK-NEXT: vmv.x.s a0, v8793; CHECK-NEXT: ret794 %e = zext <vscale x 2 x i16> %v to <vscale x 2 x i32>795 %red = call i32 @llvm.vector.reduce.add.nxv2i32(<vscale x 2 x i32> %e)796 ret i32 %red797}798 799define signext i32 @vreduce_umax_nxv2i32(<vscale x 2 x i32> %v) {800; CHECK-LABEL: vreduce_umax_nxv2i32:801; CHECK: # %bb.0:802; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma803; CHECK-NEXT: vredmaxu.vs v8, v8, v8804; CHECK-NEXT: vmv.x.s a0, v8805; CHECK-NEXT: ret806 %red = call i32 @llvm.vector.reduce.umax.nxv2i32(<vscale x 2 x i32> %v)807 ret i32 %red808}809 810define signext i32 @vreduce_smax_nxv2i32(<vscale x 2 x i32> %v) {811; CHECK-LABEL: vreduce_smax_nxv2i32:812; CHECK: # %bb.0:813; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma814; CHECK-NEXT: vredmax.vs v8, v8, v8815; CHECK-NEXT: vmv.x.s a0, v8816; CHECK-NEXT: ret817 %red = call i32 @llvm.vector.reduce.smax.nxv2i32(<vscale x 2 x i32> %v)818 ret i32 %red819}820 821define signext i32 @vreduce_umin_nxv2i32(<vscale x 2 x i32> %v) {822; CHECK-LABEL: vreduce_umin_nxv2i32:823; CHECK: # %bb.0:824; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma825; CHECK-NEXT: vredminu.vs v8, v8, v8826; CHECK-NEXT: vmv.x.s a0, v8827; CHECK-NEXT: ret828 %red = call i32 @llvm.vector.reduce.umin.nxv2i32(<vscale x 2 x i32> %v)829 ret i32 %red830}831 832define signext i32 @vreduce_smin_nxv2i32(<vscale x 2 x i32> %v) {833; CHECK-LABEL: vreduce_smin_nxv2i32:834; CHECK: # %bb.0:835; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma836; CHECK-NEXT: vredmin.vs v8, v8, v8837; CHECK-NEXT: vmv.x.s a0, v8838; CHECK-NEXT: ret839 %red = call i32 @llvm.vector.reduce.smin.nxv2i32(<vscale x 2 x i32> %v)840 ret i32 %red841}842 843define signext i32 @vreduce_and_nxv2i32(<vscale x 2 x i32> %v) {844; CHECK-LABEL: vreduce_and_nxv2i32:845; CHECK: # %bb.0:846; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma847; CHECK-NEXT: vredand.vs v8, v8, v8848; CHECK-NEXT: vmv.x.s a0, v8849; CHECK-NEXT: ret850 %red = call i32 @llvm.vector.reduce.and.nxv2i32(<vscale x 2 x i32> %v)851 ret i32 %red852}853 854define signext i32 @vreduce_or_nxv2i32(<vscale x 2 x i32> %v) {855; CHECK-LABEL: vreduce_or_nxv2i32:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma858; CHECK-NEXT: vredor.vs v8, v8, v8859; CHECK-NEXT: vmv.x.s a0, v8860; CHECK-NEXT: ret861 %red = call i32 @llvm.vector.reduce.or.nxv2i32(<vscale x 2 x i32> %v)862 ret i32 %red863}864 865define signext i32 @vreduce_xor_nxv2i32(<vscale x 2 x i32> %v) {866; CHECK-LABEL: vreduce_xor_nxv2i32:867; CHECK: # %bb.0:868; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma869; CHECK-NEXT: vmv.s.x v9, zero870; CHECK-NEXT: vredxor.vs v8, v8, v9871; CHECK-NEXT: vmv.x.s a0, v8872; CHECK-NEXT: ret873 %red = call i32 @llvm.vector.reduce.xor.nxv2i32(<vscale x 2 x i32> %v)874 ret i32 %red875}876 877define signext i32 @vreduce_add_nxv4i32(<vscale x 4 x i32> %v) {878; CHECK-LABEL: vreduce_add_nxv4i32:879; CHECK: # %bb.0:880; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma881; CHECK-NEXT: vmv.s.x v10, zero882; CHECK-NEXT: vredsum.vs v8, v8, v10883; CHECK-NEXT: vmv.x.s a0, v8884; CHECK-NEXT: ret885 %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %v)886 ret i32 %red887}888 889define signext i32 @vwreduce_add_nxv4i16(<vscale x 4 x i16> %v) {890; CHECK-LABEL: vwreduce_add_nxv4i16:891; CHECK: # %bb.0:892; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma893; CHECK-NEXT: vmv.s.x v9, zero894; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma895; CHECK-NEXT: vwredsum.vs v8, v8, v9896; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma897; CHECK-NEXT: vmv.x.s a0, v8898; CHECK-NEXT: ret899 %e = sext <vscale x 4 x i16> %v to <vscale x 4 x i32>900 %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %e)901 ret i32 %red902}903 904define signext i32 @vwreduce_uadd_nxv4i16(<vscale x 4 x i16> %v) {905; CHECK-LABEL: vwreduce_uadd_nxv4i16:906; CHECK: # %bb.0:907; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma908; CHECK-NEXT: vmv.s.x v9, zero909; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma910; CHECK-NEXT: vwredsumu.vs v8, v8, v9911; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma912; CHECK-NEXT: vmv.x.s a0, v8913; CHECK-NEXT: ret914 %e = zext <vscale x 4 x i16> %v to <vscale x 4 x i32>915 %red = call i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32> %e)916 ret i32 %red917}918 919define signext i32 @vreduce_umax_nxv4i32(<vscale x 4 x i32> %v) {920; CHECK-LABEL: vreduce_umax_nxv4i32:921; CHECK: # %bb.0:922; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma923; CHECK-NEXT: vredmaxu.vs v8, v8, v8924; CHECK-NEXT: vmv.x.s a0, v8925; CHECK-NEXT: ret926 %red = call i32 @llvm.vector.reduce.umax.nxv4i32(<vscale x 4 x i32> %v)927 ret i32 %red928}929 930define signext i32 @vreduce_smax_nxv4i32(<vscale x 4 x i32> %v) {931; CHECK-LABEL: vreduce_smax_nxv4i32:932; CHECK: # %bb.0:933; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma934; CHECK-NEXT: vredmax.vs v8, v8, v8935; CHECK-NEXT: vmv.x.s a0, v8936; CHECK-NEXT: ret937 %red = call i32 @llvm.vector.reduce.smax.nxv4i32(<vscale x 4 x i32> %v)938 ret i32 %red939}940 941define signext i32 @vreduce_umin_nxv4i32(<vscale x 4 x i32> %v) {942; CHECK-LABEL: vreduce_umin_nxv4i32:943; CHECK: # %bb.0:944; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma945; CHECK-NEXT: vredminu.vs v8, v8, v8946; CHECK-NEXT: vmv.x.s a0, v8947; CHECK-NEXT: ret948 %red = call i32 @llvm.vector.reduce.umin.nxv4i32(<vscale x 4 x i32> %v)949 ret i32 %red950}951 952define signext i32 @vreduce_smin_nxv4i32(<vscale x 4 x i32> %v) {953; CHECK-LABEL: vreduce_smin_nxv4i32:954; CHECK: # %bb.0:955; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma956; CHECK-NEXT: vredmin.vs v8, v8, v8957; CHECK-NEXT: vmv.x.s a0, v8958; CHECK-NEXT: ret959 %red = call i32 @llvm.vector.reduce.smin.nxv4i32(<vscale x 4 x i32> %v)960 ret i32 %red961}962 963define signext i32 @vreduce_and_nxv4i32(<vscale x 4 x i32> %v) {964; CHECK-LABEL: vreduce_and_nxv4i32:965; CHECK: # %bb.0:966; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma967; CHECK-NEXT: vredand.vs v8, v8, v8968; CHECK-NEXT: vmv.x.s a0, v8969; CHECK-NEXT: ret970 %red = call i32 @llvm.vector.reduce.and.nxv4i32(<vscale x 4 x i32> %v)971 ret i32 %red972}973 974define signext i32 @vreduce_or_nxv4i32(<vscale x 4 x i32> %v) {975; CHECK-LABEL: vreduce_or_nxv4i32:976; CHECK: # %bb.0:977; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma978; CHECK-NEXT: vredor.vs v8, v8, v8979; CHECK-NEXT: vmv.x.s a0, v8980; CHECK-NEXT: ret981 %red = call i32 @llvm.vector.reduce.or.nxv4i32(<vscale x 4 x i32> %v)982 ret i32 %red983}984 985define signext i32 @vreduce_xor_nxv4i32(<vscale x 4 x i32> %v) {986; CHECK-LABEL: vreduce_xor_nxv4i32:987; CHECK: # %bb.0:988; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma989; CHECK-NEXT: vmv.s.x v10, zero990; CHECK-NEXT: vredxor.vs v8, v8, v10991; CHECK-NEXT: vmv.x.s a0, v8992; CHECK-NEXT: ret993 %red = call i32 @llvm.vector.reduce.xor.nxv4i32(<vscale x 4 x i32> %v)994 ret i32 %red995}996 997define i64 @vreduce_add_nxv1i64(<vscale x 1 x i64> %v) {998; RV32-LABEL: vreduce_add_nxv1i64:999; RV32: # %bb.0:1000; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1001; RV32-NEXT: vmv.s.x v9, zero1002; RV32-NEXT: li a1, 321003; RV32-NEXT: vredsum.vs v8, v8, v91004; RV32-NEXT: vmv.x.s a0, v81005; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1006; RV32-NEXT: vsrl.vx v8, v8, a11007; RV32-NEXT: vmv.x.s a1, v81008; RV32-NEXT: ret1009;1010; RV64-LABEL: vreduce_add_nxv1i64:1011; RV64: # %bb.0:1012; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1013; RV64-NEXT: vmv.s.x v9, zero1014; RV64-NEXT: vredsum.vs v8, v8, v91015; RV64-NEXT: vmv.x.s a0, v81016; RV64-NEXT: ret1017 %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)1018 ret i64 %red1019}1020 1021define i64 @vwreduce_add_nxv1i32(<vscale x 1 x i32> %v) {1022; RV32-LABEL: vwreduce_add_nxv1i32:1023; RV32: # %bb.0:1024; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1025; RV32-NEXT: vmv.s.x v9, zero1026; RV32-NEXT: li a1, 321027; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1028; RV32-NEXT: vwredsum.vs v8, v8, v91029; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1030; RV32-NEXT: vmv.x.s a0, v81031; RV32-NEXT: vsrl.vx v8, v8, a11032; RV32-NEXT: vmv.x.s a1, v81033; RV32-NEXT: ret1034;1035; RV64-LABEL: vwreduce_add_nxv1i32:1036; RV64: # %bb.0:1037; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1038; RV64-NEXT: vmv.s.x v9, zero1039; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1040; RV64-NEXT: vwredsum.vs v8, v8, v91041; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma1042; RV64-NEXT: vmv.x.s a0, v81043; RV64-NEXT: ret1044 %e = sext <vscale x 1 x i32> %v to <vscale x 1 x i64>1045 %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %e)1046 ret i64 %red1047}1048 1049define i64 @vwreduce_uadd_nxv1i32(<vscale x 1 x i32> %v) {1050; RV32-LABEL: vwreduce_uadd_nxv1i32:1051; RV32: # %bb.0:1052; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1053; RV32-NEXT: vmv.s.x v9, zero1054; RV32-NEXT: li a1, 321055; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1056; RV32-NEXT: vwredsumu.vs v8, v8, v91057; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1058; RV32-NEXT: vmv.x.s a0, v81059; RV32-NEXT: vsrl.vx v8, v8, a11060; RV32-NEXT: vmv.x.s a1, v81061; RV32-NEXT: ret1062;1063; RV64-LABEL: vwreduce_uadd_nxv1i32:1064; RV64: # %bb.0:1065; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1066; RV64-NEXT: vmv.s.x v9, zero1067; RV64-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1068; RV64-NEXT: vwredsumu.vs v8, v8, v91069; RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma1070; RV64-NEXT: vmv.x.s a0, v81071; RV64-NEXT: ret1072 %e = zext <vscale x 1 x i32> %v to <vscale x 1 x i64>1073 %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %e)1074 ret i64 %red1075}1076 1077define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {1078; RV32-LABEL: vreduce_umax_nxv1i64:1079; RV32: # %bb.0:1080; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1081; RV32-NEXT: vredmaxu.vs v8, v8, v81082; RV32-NEXT: li a0, 321083; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1084; RV32-NEXT: vsrl.vx v9, v8, a01085; RV32-NEXT: vmv.x.s a1, v91086; RV32-NEXT: vmv.x.s a0, v81087; RV32-NEXT: ret1088;1089; RV64-LABEL: vreduce_umax_nxv1i64:1090; RV64: # %bb.0:1091; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1092; RV64-NEXT: vredmaxu.vs v8, v8, v81093; RV64-NEXT: vmv.x.s a0, v81094; RV64-NEXT: ret1095 %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)1096 ret i64 %red1097}1098 1099define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {1100; RV32-LABEL: vreduce_smax_nxv1i64:1101; RV32: # %bb.0:1102; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1103; RV32-NEXT: vredmax.vs v8, v8, v81104; RV32-NEXT: li a0, 321105; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1106; RV32-NEXT: vsrl.vx v9, v8, a01107; RV32-NEXT: vmv.x.s a1, v91108; RV32-NEXT: vmv.x.s a0, v81109; RV32-NEXT: ret1110;1111; RV64-LABEL: vreduce_smax_nxv1i64:1112; RV64: # %bb.0:1113; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1114; RV64-NEXT: vredmax.vs v8, v8, v81115; RV64-NEXT: vmv.x.s a0, v81116; RV64-NEXT: ret1117 %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)1118 ret i64 %red1119}1120 1121define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {1122; RV32-LABEL: vreduce_umin_nxv1i64:1123; RV32: # %bb.0:1124; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1125; RV32-NEXT: vredminu.vs v8, v8, v81126; RV32-NEXT: li a0, 321127; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1128; RV32-NEXT: vsrl.vx v9, v8, a01129; RV32-NEXT: vmv.x.s a1, v91130; RV32-NEXT: vmv.x.s a0, v81131; RV32-NEXT: ret1132;1133; RV64-LABEL: vreduce_umin_nxv1i64:1134; RV64: # %bb.0:1135; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1136; RV64-NEXT: vredminu.vs v8, v8, v81137; RV64-NEXT: vmv.x.s a0, v81138; RV64-NEXT: ret1139 %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)1140 ret i64 %red1141}1142 1143define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {1144; RV32-LABEL: vreduce_smin_nxv1i64:1145; RV32: # %bb.0:1146; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1147; RV32-NEXT: vredmin.vs v8, v8, v81148; RV32-NEXT: li a0, 321149; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1150; RV32-NEXT: vsrl.vx v9, v8, a01151; RV32-NEXT: vmv.x.s a1, v91152; RV32-NEXT: vmv.x.s a0, v81153; RV32-NEXT: ret1154;1155; RV64-LABEL: vreduce_smin_nxv1i64:1156; RV64: # %bb.0:1157; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1158; RV64-NEXT: vredmin.vs v8, v8, v81159; RV64-NEXT: vmv.x.s a0, v81160; RV64-NEXT: ret1161 %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)1162 ret i64 %red1163}1164 1165define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {1166; RV32-LABEL: vreduce_and_nxv1i64:1167; RV32: # %bb.0:1168; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1169; RV32-NEXT: vredand.vs v8, v8, v81170; RV32-NEXT: li a0, 321171; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1172; RV32-NEXT: vsrl.vx v9, v8, a01173; RV32-NEXT: vmv.x.s a1, v91174; RV32-NEXT: vmv.x.s a0, v81175; RV32-NEXT: ret1176;1177; RV64-LABEL: vreduce_and_nxv1i64:1178; RV64: # %bb.0:1179; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1180; RV64-NEXT: vredand.vs v8, v8, v81181; RV64-NEXT: vmv.x.s a0, v81182; RV64-NEXT: ret1183 %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)1184 ret i64 %red1185}1186 1187define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {1188; RV32-LABEL: vreduce_or_nxv1i64:1189; RV32: # %bb.0:1190; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1191; RV32-NEXT: vredor.vs v8, v8, v81192; RV32-NEXT: li a0, 321193; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1194; RV32-NEXT: vsrl.vx v9, v8, a01195; RV32-NEXT: vmv.x.s a1, v91196; RV32-NEXT: vmv.x.s a0, v81197; RV32-NEXT: ret1198;1199; RV64-LABEL: vreduce_or_nxv1i64:1200; RV64: # %bb.0:1201; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1202; RV64-NEXT: vredor.vs v8, v8, v81203; RV64-NEXT: vmv.x.s a0, v81204; RV64-NEXT: ret1205 %red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)1206 ret i64 %red1207}1208 1209define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {1210; RV32-LABEL: vreduce_xor_nxv1i64:1211; RV32: # %bb.0:1212; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma1213; RV32-NEXT: vmv.s.x v9, zero1214; RV32-NEXT: li a1, 321215; RV32-NEXT: vredxor.vs v8, v8, v91216; RV32-NEXT: vmv.x.s a0, v81217; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1218; RV32-NEXT: vsrl.vx v8, v8, a11219; RV32-NEXT: vmv.x.s a1, v81220; RV32-NEXT: ret1221;1222; RV64-LABEL: vreduce_xor_nxv1i64:1223; RV64: # %bb.0:1224; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1225; RV64-NEXT: vmv.s.x v9, zero1226; RV64-NEXT: vredxor.vs v8, v8, v91227; RV64-NEXT: vmv.x.s a0, v81228; RV64-NEXT: ret1229 %red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)1230 ret i64 %red1231}1232 1233define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {1234; RV32-LABEL: vreduce_add_nxv2i64:1235; RV32: # %bb.0:1236; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1237; RV32-NEXT: vmv.s.x v10, zero1238; RV32-NEXT: li a1, 321239; RV32-NEXT: vredsum.vs v8, v8, v101240; RV32-NEXT: vmv.x.s a0, v81241; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1242; RV32-NEXT: vsrl.vx v8, v8, a11243; RV32-NEXT: vmv.x.s a1, v81244; RV32-NEXT: ret1245;1246; RV64-LABEL: vreduce_add_nxv2i64:1247; RV64: # %bb.0:1248; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1249; RV64-NEXT: vmv.s.x v10, zero1250; RV64-NEXT: vredsum.vs v8, v8, v101251; RV64-NEXT: vmv.x.s a0, v81252; RV64-NEXT: ret1253 %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)1254 ret i64 %red1255}1256 1257define i64 @vwreduce_add_nxv2i32(<vscale x 2 x i32> %v) {1258; RV32-LABEL: vwreduce_add_nxv2i32:1259; RV32: # %bb.0:1260; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1261; RV32-NEXT: vmv.s.x v9, zero1262; RV32-NEXT: li a1, 321263; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma1264; RV32-NEXT: vwredsum.vs v8, v8, v91265; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1266; RV32-NEXT: vmv.x.s a0, v81267; RV32-NEXT: vsrl.vx v8, v8, a11268; RV32-NEXT: vmv.x.s a1, v81269; RV32-NEXT: ret1270;1271; RV64-LABEL: vwreduce_add_nxv2i32:1272; RV64: # %bb.0:1273; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1274; RV64-NEXT: vmv.s.x v9, zero1275; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma1276; RV64-NEXT: vwredsum.vs v8, v8, v91277; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1278; RV64-NEXT: vmv.x.s a0, v81279; RV64-NEXT: ret1280 %e = sext <vscale x 2 x i32> %v to <vscale x 2 x i64>1281 %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %e)1282 ret i64 %red1283}1284 1285define i64 @vwreduce_uadd_nxv2i32(<vscale x 2 x i32> %v) {1286; RV32-LABEL: vwreduce_uadd_nxv2i32:1287; RV32: # %bb.0:1288; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1289; RV32-NEXT: vmv.s.x v9, zero1290; RV32-NEXT: li a1, 321291; RV32-NEXT: vsetvli a0, zero, e32, m1, ta, ma1292; RV32-NEXT: vwredsumu.vs v8, v8, v91293; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1294; RV32-NEXT: vmv.x.s a0, v81295; RV32-NEXT: vsrl.vx v8, v8, a11296; RV32-NEXT: vmv.x.s a1, v81297; RV32-NEXT: ret1298;1299; RV64-LABEL: vwreduce_uadd_nxv2i32:1300; RV64: # %bb.0:1301; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1302; RV64-NEXT: vmv.s.x v9, zero1303; RV64-NEXT: vsetvli a0, zero, e32, m1, ta, ma1304; RV64-NEXT: vwredsumu.vs v8, v8, v91305; RV64-NEXT: vsetvli zero, zero, e64, m2, ta, ma1306; RV64-NEXT: vmv.x.s a0, v81307; RV64-NEXT: ret1308 %e = zext <vscale x 2 x i32> %v to <vscale x 2 x i64>1309 %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %e)1310 ret i64 %red1311}1312 1313define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {1314; RV32-LABEL: vreduce_umax_nxv2i64:1315; RV32: # %bb.0:1316; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1317; RV32-NEXT: vredmaxu.vs v8, v8, v81318; RV32-NEXT: li a1, 321319; RV32-NEXT: vmv.x.s a0, v81320; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1321; RV32-NEXT: vsrl.vx v8, v8, a11322; RV32-NEXT: vmv.x.s a1, v81323; RV32-NEXT: ret1324;1325; RV64-LABEL: vreduce_umax_nxv2i64:1326; RV64: # %bb.0:1327; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1328; RV64-NEXT: vredmaxu.vs v8, v8, v81329; RV64-NEXT: vmv.x.s a0, v81330; RV64-NEXT: ret1331 %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)1332 ret i64 %red1333}1334 1335define i64 @vreduce_smax_nxv2i64(<vscale x 2 x i64> %v) {1336; RV32-LABEL: vreduce_smax_nxv2i64:1337; RV32: # %bb.0:1338; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1339; RV32-NEXT: vredmax.vs v8, v8, v81340; RV32-NEXT: li a1, 321341; RV32-NEXT: vmv.x.s a0, v81342; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1343; RV32-NEXT: vsrl.vx v8, v8, a11344; RV32-NEXT: vmv.x.s a1, v81345; RV32-NEXT: ret1346;1347; RV64-LABEL: vreduce_smax_nxv2i64:1348; RV64: # %bb.0:1349; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1350; RV64-NEXT: vredmax.vs v8, v8, v81351; RV64-NEXT: vmv.x.s a0, v81352; RV64-NEXT: ret1353 %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)1354 ret i64 %red1355}1356 1357define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {1358; RV32-LABEL: vreduce_umin_nxv2i64:1359; RV32: # %bb.0:1360; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1361; RV32-NEXT: vredminu.vs v8, v8, v81362; RV32-NEXT: li a1, 321363; RV32-NEXT: vmv.x.s a0, v81364; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1365; RV32-NEXT: vsrl.vx v8, v8, a11366; RV32-NEXT: vmv.x.s a1, v81367; RV32-NEXT: ret1368;1369; RV64-LABEL: vreduce_umin_nxv2i64:1370; RV64: # %bb.0:1371; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1372; RV64-NEXT: vredminu.vs v8, v8, v81373; RV64-NEXT: vmv.x.s a0, v81374; RV64-NEXT: ret1375 %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)1376 ret i64 %red1377}1378 1379define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {1380; RV32-LABEL: vreduce_smin_nxv2i64:1381; RV32: # %bb.0:1382; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1383; RV32-NEXT: vredmin.vs v8, v8, v81384; RV32-NEXT: li a1, 321385; RV32-NEXT: vmv.x.s a0, v81386; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1387; RV32-NEXT: vsrl.vx v8, v8, a11388; RV32-NEXT: vmv.x.s a1, v81389; RV32-NEXT: ret1390;1391; RV64-LABEL: vreduce_smin_nxv2i64:1392; RV64: # %bb.0:1393; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1394; RV64-NEXT: vredmin.vs v8, v8, v81395; RV64-NEXT: vmv.x.s a0, v81396; RV64-NEXT: ret1397 %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)1398 ret i64 %red1399}1400 1401define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {1402; RV32-LABEL: vreduce_and_nxv2i64:1403; RV32: # %bb.0:1404; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1405; RV32-NEXT: vredand.vs v8, v8, v81406; RV32-NEXT: li a1, 321407; RV32-NEXT: vmv.x.s a0, v81408; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1409; RV32-NEXT: vsrl.vx v8, v8, a11410; RV32-NEXT: vmv.x.s a1, v81411; RV32-NEXT: ret1412;1413; RV64-LABEL: vreduce_and_nxv2i64:1414; RV64: # %bb.0:1415; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1416; RV64-NEXT: vredand.vs v8, v8, v81417; RV64-NEXT: vmv.x.s a0, v81418; RV64-NEXT: ret1419 %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)1420 ret i64 %red1421}1422 1423define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {1424; RV32-LABEL: vreduce_or_nxv2i64:1425; RV32: # %bb.0:1426; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1427; RV32-NEXT: vredor.vs v8, v8, v81428; RV32-NEXT: li a1, 321429; RV32-NEXT: vmv.x.s a0, v81430; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1431; RV32-NEXT: vsrl.vx v8, v8, a11432; RV32-NEXT: vmv.x.s a1, v81433; RV32-NEXT: ret1434;1435; RV64-LABEL: vreduce_or_nxv2i64:1436; RV64: # %bb.0:1437; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1438; RV64-NEXT: vredor.vs v8, v8, v81439; RV64-NEXT: vmv.x.s a0, v81440; RV64-NEXT: ret1441 %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)1442 ret i64 %red1443}1444 1445define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {1446; RV32-LABEL: vreduce_xor_nxv2i64:1447; RV32: # %bb.0:1448; RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma1449; RV32-NEXT: vmv.s.x v10, zero1450; RV32-NEXT: li a1, 321451; RV32-NEXT: vredxor.vs v8, v8, v101452; RV32-NEXT: vmv.x.s a0, v81453; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1454; RV32-NEXT: vsrl.vx v8, v8, a11455; RV32-NEXT: vmv.x.s a1, v81456; RV32-NEXT: ret1457;1458; RV64-LABEL: vreduce_xor_nxv2i64:1459; RV64: # %bb.0:1460; RV64-NEXT: vsetvli a0, zero, e64, m2, ta, ma1461; RV64-NEXT: vmv.s.x v10, zero1462; RV64-NEXT: vredxor.vs v8, v8, v101463; RV64-NEXT: vmv.x.s a0, v81464; RV64-NEXT: ret1465 %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)1466 ret i64 %red1467}1468 1469define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {1470; RV32-LABEL: vreduce_add_nxv4i64:1471; RV32: # %bb.0:1472; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1473; RV32-NEXT: vmv.s.x v12, zero1474; RV32-NEXT: li a1, 321475; RV32-NEXT: vredsum.vs v8, v8, v121476; RV32-NEXT: vmv.x.s a0, v81477; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1478; RV32-NEXT: vsrl.vx v8, v8, a11479; RV32-NEXT: vmv.x.s a1, v81480; RV32-NEXT: ret1481;1482; RV64-LABEL: vreduce_add_nxv4i64:1483; RV64: # %bb.0:1484; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1485; RV64-NEXT: vmv.s.x v12, zero1486; RV64-NEXT: vredsum.vs v8, v8, v121487; RV64-NEXT: vmv.x.s a0, v81488; RV64-NEXT: ret1489 %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)1490 ret i64 %red1491}1492 1493define i64 @vwreduce_add_nxv4i32(<vscale x 4 x i32> %v) {1494; RV32-LABEL: vwreduce_add_nxv4i32:1495; RV32: # %bb.0:1496; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1497; RV32-NEXT: vmv.s.x v10, zero1498; RV32-NEXT: li a1, 321499; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma1500; RV32-NEXT: vwredsum.vs v8, v8, v101501; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1502; RV32-NEXT: vmv.x.s a0, v81503; RV32-NEXT: vsrl.vx v8, v8, a11504; RV32-NEXT: vmv.x.s a1, v81505; RV32-NEXT: ret1506;1507; RV64-LABEL: vwreduce_add_nxv4i32:1508; RV64: # %bb.0:1509; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1510; RV64-NEXT: vmv.s.x v10, zero1511; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1512; RV64-NEXT: vwredsum.vs v8, v8, v101513; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1514; RV64-NEXT: vmv.x.s a0, v81515; RV64-NEXT: ret1516 %e = sext <vscale x 4 x i32> %v to <vscale x 4 x i64>1517 %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %e)1518 ret i64 %red1519}1520 1521define i64 @vwreduce_uadd_nxv4i32(<vscale x 4 x i32> %v) {1522; RV32-LABEL: vwreduce_uadd_nxv4i32:1523; RV32: # %bb.0:1524; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1525; RV32-NEXT: vmv.s.x v10, zero1526; RV32-NEXT: li a1, 321527; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma1528; RV32-NEXT: vwredsumu.vs v8, v8, v101529; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1530; RV32-NEXT: vmv.x.s a0, v81531; RV32-NEXT: vsrl.vx v8, v8, a11532; RV32-NEXT: vmv.x.s a1, v81533; RV32-NEXT: ret1534;1535; RV64-LABEL: vwreduce_uadd_nxv4i32:1536; RV64: # %bb.0:1537; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma1538; RV64-NEXT: vmv.s.x v10, zero1539; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma1540; RV64-NEXT: vwredsumu.vs v8, v8, v101541; RV64-NEXT: vsetvli zero, zero, e64, m4, ta, ma1542; RV64-NEXT: vmv.x.s a0, v81543; RV64-NEXT: ret1544 %e = zext <vscale x 4 x i32> %v to <vscale x 4 x i64>1545 %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %e)1546 ret i64 %red1547}1548 1549define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {1550; RV32-LABEL: vreduce_umax_nxv4i64:1551; RV32: # %bb.0:1552; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1553; RV32-NEXT: vredmaxu.vs v8, v8, v81554; RV32-NEXT: li a1, 321555; RV32-NEXT: vmv.x.s a0, v81556; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1557; RV32-NEXT: vsrl.vx v8, v8, a11558; RV32-NEXT: vmv.x.s a1, v81559; RV32-NEXT: ret1560;1561; RV64-LABEL: vreduce_umax_nxv4i64:1562; RV64: # %bb.0:1563; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1564; RV64-NEXT: vredmaxu.vs v8, v8, v81565; RV64-NEXT: vmv.x.s a0, v81566; RV64-NEXT: ret1567 %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)1568 ret i64 %red1569}1570 1571define i64 @vreduce_smax_nxv4i64(<vscale x 4 x i64> %v) {1572; RV32-LABEL: vreduce_smax_nxv4i64:1573; RV32: # %bb.0:1574; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1575; RV32-NEXT: vredmax.vs v8, v8, v81576; RV32-NEXT: li a1, 321577; RV32-NEXT: vmv.x.s a0, v81578; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1579; RV32-NEXT: vsrl.vx v8, v8, a11580; RV32-NEXT: vmv.x.s a1, v81581; RV32-NEXT: ret1582;1583; RV64-LABEL: vreduce_smax_nxv4i64:1584; RV64: # %bb.0:1585; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1586; RV64-NEXT: vredmax.vs v8, v8, v81587; RV64-NEXT: vmv.x.s a0, v81588; RV64-NEXT: ret1589 %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)1590 ret i64 %red1591}1592 1593define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {1594; RV32-LABEL: vreduce_umin_nxv4i64:1595; RV32: # %bb.0:1596; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1597; RV32-NEXT: vredminu.vs v8, v8, v81598; RV32-NEXT: li a1, 321599; RV32-NEXT: vmv.x.s a0, v81600; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1601; RV32-NEXT: vsrl.vx v8, v8, a11602; RV32-NEXT: vmv.x.s a1, v81603; RV32-NEXT: ret1604;1605; RV64-LABEL: vreduce_umin_nxv4i64:1606; RV64: # %bb.0:1607; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1608; RV64-NEXT: vredminu.vs v8, v8, v81609; RV64-NEXT: vmv.x.s a0, v81610; RV64-NEXT: ret1611 %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)1612 ret i64 %red1613}1614 1615define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {1616; RV32-LABEL: vreduce_smin_nxv4i64:1617; RV32: # %bb.0:1618; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1619; RV32-NEXT: vredmin.vs v8, v8, v81620; RV32-NEXT: li a1, 321621; RV32-NEXT: vmv.x.s a0, v81622; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1623; RV32-NEXT: vsrl.vx v8, v8, a11624; RV32-NEXT: vmv.x.s a1, v81625; RV32-NEXT: ret1626;1627; RV64-LABEL: vreduce_smin_nxv4i64:1628; RV64: # %bb.0:1629; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1630; RV64-NEXT: vredmin.vs v8, v8, v81631; RV64-NEXT: vmv.x.s a0, v81632; RV64-NEXT: ret1633 %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)1634 ret i64 %red1635}1636 1637define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {1638; RV32-LABEL: vreduce_and_nxv4i64:1639; RV32: # %bb.0:1640; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1641; RV32-NEXT: vredand.vs v8, v8, v81642; RV32-NEXT: li a1, 321643; RV32-NEXT: vmv.x.s a0, v81644; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1645; RV32-NEXT: vsrl.vx v8, v8, a11646; RV32-NEXT: vmv.x.s a1, v81647; RV32-NEXT: ret1648;1649; RV64-LABEL: vreduce_and_nxv4i64:1650; RV64: # %bb.0:1651; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1652; RV64-NEXT: vredand.vs v8, v8, v81653; RV64-NEXT: vmv.x.s a0, v81654; RV64-NEXT: ret1655 %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)1656 ret i64 %red1657}1658 1659define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {1660; RV32-LABEL: vreduce_or_nxv4i64:1661; RV32: # %bb.0:1662; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1663; RV32-NEXT: vredor.vs v8, v8, v81664; RV32-NEXT: li a1, 321665; RV32-NEXT: vmv.x.s a0, v81666; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1667; RV32-NEXT: vsrl.vx v8, v8, a11668; RV32-NEXT: vmv.x.s a1, v81669; RV32-NEXT: ret1670;1671; RV64-LABEL: vreduce_or_nxv4i64:1672; RV64: # %bb.0:1673; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1674; RV64-NEXT: vredor.vs v8, v8, v81675; RV64-NEXT: vmv.x.s a0, v81676; RV64-NEXT: ret1677 %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)1678 ret i64 %red1679}1680 1681define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {1682; RV32-LABEL: vreduce_xor_nxv4i64:1683; RV32: # %bb.0:1684; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma1685; RV32-NEXT: vmv.s.x v12, zero1686; RV32-NEXT: li a1, 321687; RV32-NEXT: vredxor.vs v8, v8, v121688; RV32-NEXT: vmv.x.s a0, v81689; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma1690; RV32-NEXT: vsrl.vx v8, v8, a11691; RV32-NEXT: vmv.x.s a1, v81692; RV32-NEXT: ret1693;1694; RV64-LABEL: vreduce_xor_nxv4i64:1695; RV64: # %bb.0:1696; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma1697; RV64-NEXT: vmv.s.x v12, zero1698; RV64-NEXT: vredxor.vs v8, v8, v121699; RV64-NEXT: vmv.x.s a0, v81700; RV64-NEXT: ret1701 %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)1702 ret i64 %red1703}1704