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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define zeroext i1 @vpreduce_and_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {6; CHECK-LABEL: vpreduce_and_nxv1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma9; CHECK-NEXT: vmnot.m v9, v010; CHECK-NEXT: vmv1r.v v0, v811; CHECK-NEXT: vcpop.m a1, v9, v0.t12; CHECK-NEXT: seqz a1, a113; CHECK-NEXT: and a0, a1, a014; CHECK-NEXT: ret15 %r = call i1 @llvm.vp.reduce.and.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)16 ret i1 %r17}18 19define zeroext i1 @vpreduce_or_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {20; CHECK-LABEL: vpreduce_or_nxv1i1:21; CHECK: # %bb.0:22; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma23; CHECK-NEXT: vmv1r.v v9, v024; CHECK-NEXT: vmv1r.v v0, v825; CHECK-NEXT: vcpop.m a1, v9, v0.t26; CHECK-NEXT: snez a1, a127; CHECK-NEXT: or a0, a1, a028; CHECK-NEXT: ret29 %r = call i1 @llvm.vp.reduce.or.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)30 ret i1 %r31}32 33define zeroext i1 @vpreduce_xor_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {34; CHECK-LABEL: vpreduce_xor_nxv1i1:35; CHECK: # %bb.0:36; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma37; CHECK-NEXT: vmv1r.v v9, v038; CHECK-NEXT: vmv1r.v v0, v839; CHECK-NEXT: vcpop.m a1, v9, v0.t40; CHECK-NEXT: andi a1, a1, 141; CHECK-NEXT: xor a0, a1, a042; CHECK-NEXT: ret43 %r = call i1 @llvm.vp.reduce.xor.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)44 ret i1 %r45}46 47define zeroext i1 @vpreduce_and_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {48; CHECK-LABEL: vpreduce_and_nxv2i1:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma51; CHECK-NEXT: vmnot.m v9, v052; CHECK-NEXT: vmv1r.v v0, v853; CHECK-NEXT: vcpop.m a1, v9, v0.t54; CHECK-NEXT: seqz a1, a155; CHECK-NEXT: and a0, a1, a056; CHECK-NEXT: ret57 %r = call i1 @llvm.vp.reduce.and.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)58 ret i1 %r59}60 61define zeroext i1 @vpreduce_or_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {62; CHECK-LABEL: vpreduce_or_nxv2i1:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma65; CHECK-NEXT: vmv1r.v v9, v066; CHECK-NEXT: vmv1r.v v0, v867; CHECK-NEXT: vcpop.m a1, v9, v0.t68; CHECK-NEXT: snez a1, a169; CHECK-NEXT: or a0, a1, a070; CHECK-NEXT: ret71 %r = call i1 @llvm.vp.reduce.or.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)72 ret i1 %r73}74 75define zeroext i1 @vpreduce_xor_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {76; CHECK-LABEL: vpreduce_xor_nxv2i1:77; CHECK: # %bb.0:78; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma79; CHECK-NEXT: vmv1r.v v9, v080; CHECK-NEXT: vmv1r.v v0, v881; CHECK-NEXT: vcpop.m a1, v9, v0.t82; CHECK-NEXT: andi a1, a1, 183; CHECK-NEXT: xor a0, a1, a084; CHECK-NEXT: ret85 %r = call i1 @llvm.vp.reduce.xor.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)86 ret i1 %r87}88 89define zeroext i1 @vpreduce_and_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {90; CHECK-LABEL: vpreduce_and_nxv4i1:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma93; CHECK-NEXT: vmnot.m v9, v094; CHECK-NEXT: vmv1r.v v0, v895; CHECK-NEXT: vcpop.m a1, v9, v0.t96; CHECK-NEXT: seqz a1, a197; CHECK-NEXT: and a0, a1, a098; CHECK-NEXT: ret99 %r = call i1 @llvm.vp.reduce.and.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)100 ret i1 %r101}102 103define zeroext i1 @vpreduce_or_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {104; CHECK-LABEL: vpreduce_or_nxv4i1:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma107; CHECK-NEXT: vmv1r.v v9, v0108; CHECK-NEXT: vmv1r.v v0, v8109; CHECK-NEXT: vcpop.m a1, v9, v0.t110; CHECK-NEXT: snez a1, a1111; CHECK-NEXT: or a0, a1, a0112; CHECK-NEXT: ret113 %r = call i1 @llvm.vp.reduce.or.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)114 ret i1 %r115}116 117define zeroext i1 @vpreduce_xor_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {118; CHECK-LABEL: vpreduce_xor_nxv4i1:119; CHECK: # %bb.0:120; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma121; CHECK-NEXT: vmv1r.v v9, v0122; CHECK-NEXT: vmv1r.v v0, v8123; CHECK-NEXT: vcpop.m a1, v9, v0.t124; CHECK-NEXT: andi a1, a1, 1125; CHECK-NEXT: xor a0, a1, a0126; CHECK-NEXT: ret127 %r = call i1 @llvm.vp.reduce.xor.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)128 ret i1 %r129}130 131define zeroext i1 @vpreduce_and_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {132; CHECK-LABEL: vpreduce_and_nxv8i1:133; CHECK: # %bb.0:134; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma135; CHECK-NEXT: vmnot.m v9, v0136; CHECK-NEXT: vmv1r.v v0, v8137; CHECK-NEXT: vcpop.m a1, v9, v0.t138; CHECK-NEXT: seqz a1, a1139; CHECK-NEXT: and a0, a1, a0140; CHECK-NEXT: ret141 %r = call i1 @llvm.vp.reduce.and.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)142 ret i1 %r143}144 145define zeroext i1 @vpreduce_or_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {146; CHECK-LABEL: vpreduce_or_nxv8i1:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma149; CHECK-NEXT: vmv1r.v v9, v0150; CHECK-NEXT: vmv1r.v v0, v8151; CHECK-NEXT: vcpop.m a1, v9, v0.t152; CHECK-NEXT: snez a1, a1153; CHECK-NEXT: or a0, a1, a0154; CHECK-NEXT: ret155 %r = call i1 @llvm.vp.reduce.or.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)156 ret i1 %r157}158 159define zeroext i1 @vpreduce_xor_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {160; CHECK-LABEL: vpreduce_xor_nxv8i1:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma163; CHECK-NEXT: vmv1r.v v9, v0164; CHECK-NEXT: vmv1r.v v0, v8165; CHECK-NEXT: vcpop.m a1, v9, v0.t166; CHECK-NEXT: andi a1, a1, 1167; CHECK-NEXT: xor a0, a1, a0168; CHECK-NEXT: ret169 %r = call i1 @llvm.vp.reduce.xor.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)170 ret i1 %r171}172 173define zeroext i1 @vpreduce_and_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {174; CHECK-LABEL: vpreduce_and_nxv16i1:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma177; CHECK-NEXT: vmnot.m v9, v0178; CHECK-NEXT: vmv1r.v v0, v8179; CHECK-NEXT: vcpop.m a1, v9, v0.t180; CHECK-NEXT: seqz a1, a1181; CHECK-NEXT: and a0, a1, a0182; CHECK-NEXT: ret183 %r = call i1 @llvm.vp.reduce.and.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)184 ret i1 %r185}186 187define zeroext i1 @vpreduce_or_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {188; CHECK-LABEL: vpreduce_or_nxv16i1:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma191; CHECK-NEXT: vmv1r.v v9, v0192; CHECK-NEXT: vmv1r.v v0, v8193; CHECK-NEXT: vcpop.m a1, v9, v0.t194; CHECK-NEXT: snez a1, a1195; CHECK-NEXT: or a0, a1, a0196; CHECK-NEXT: ret197 %r = call i1 @llvm.vp.reduce.or.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)198 ret i1 %r199}200 201define zeroext i1 @vpreduce_xor_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {202; CHECK-LABEL: vpreduce_xor_nxv16i1:203; CHECK: # %bb.0:204; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma205; CHECK-NEXT: vmv1r.v v9, v0206; CHECK-NEXT: vmv1r.v v0, v8207; CHECK-NEXT: vcpop.m a1, v9, v0.t208; CHECK-NEXT: andi a1, a1, 1209; CHECK-NEXT: xor a0, a1, a0210; CHECK-NEXT: ret211 %r = call i1 @llvm.vp.reduce.xor.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)212 ret i1 %r213}214 215define zeroext i1 @vpreduce_and_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {216; CHECK-LABEL: vpreduce_and_nxv32i1:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma219; CHECK-NEXT: vmnot.m v9, v0220; CHECK-NEXT: vmv1r.v v0, v8221; CHECK-NEXT: vcpop.m a1, v9, v0.t222; CHECK-NEXT: seqz a1, a1223; CHECK-NEXT: and a0, a1, a0224; CHECK-NEXT: ret225 %r = call i1 @llvm.vp.reduce.and.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)226 ret i1 %r227}228 229define zeroext i1 @vpreduce_or_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {230; CHECK-LABEL: vpreduce_or_nxv32i1:231; CHECK: # %bb.0:232; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma233; CHECK-NEXT: vmv1r.v v9, v0234; CHECK-NEXT: vmv1r.v v0, v8235; CHECK-NEXT: vcpop.m a1, v9, v0.t236; CHECK-NEXT: snez a1, a1237; CHECK-NEXT: or a0, a1, a0238; CHECK-NEXT: ret239 %r = call i1 @llvm.vp.reduce.or.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)240 ret i1 %r241}242 243define zeroext i1 @vpreduce_xor_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {244; CHECK-LABEL: vpreduce_xor_nxv32i1:245; CHECK: # %bb.0:246; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma247; CHECK-NEXT: vmv1r.v v9, v0248; CHECK-NEXT: vmv1r.v v0, v8249; CHECK-NEXT: vcpop.m a1, v9, v0.t250; CHECK-NEXT: andi a1, a1, 1251; CHECK-NEXT: xor a0, a1, a0252; CHECK-NEXT: ret253 %r = call i1 @llvm.vp.reduce.xor.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)254 ret i1 %r255}256 257define zeroext i1 @vpreduce_or_nxv40i1(i1 zeroext %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 zeroext %evl) {258; CHECK-LABEL: vpreduce_or_nxv40i1:259; CHECK: # %bb.0:260; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma261; CHECK-NEXT: vmv1r.v v9, v0262; CHECK-NEXT: vmv1r.v v0, v8263; CHECK-NEXT: vcpop.m a1, v9, v0.t264; CHECK-NEXT: snez a1, a1265; CHECK-NEXT: or a0, a1, a0266; CHECK-NEXT: ret267 %r = call i1 @llvm.vp.reduce.or.nxv40i1(i1 %s, <vscale x 40 x i1> %v, <vscale x 40 x i1> %m, i32 %evl)268 ret i1 %r269}270 271define zeroext i1 @vpreduce_and_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {272; CHECK-LABEL: vpreduce_and_nxv64i1:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma275; CHECK-NEXT: vmnot.m v9, v0276; CHECK-NEXT: vmv1r.v v0, v8277; CHECK-NEXT: vcpop.m a1, v9, v0.t278; CHECK-NEXT: seqz a1, a1279; CHECK-NEXT: and a0, a1, a0280; CHECK-NEXT: ret281 %r = call i1 @llvm.vp.reduce.and.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)282 ret i1 %r283}284 285define zeroext i1 @vpreduce_or_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {286; CHECK-LABEL: vpreduce_or_nxv64i1:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma289; CHECK-NEXT: vmv1r.v v9, v0290; CHECK-NEXT: vmv1r.v v0, v8291; CHECK-NEXT: vcpop.m a1, v9, v0.t292; CHECK-NEXT: snez a1, a1293; CHECK-NEXT: or a0, a1, a0294; CHECK-NEXT: ret295 %r = call i1 @llvm.vp.reduce.or.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)296 ret i1 %r297}298 299define zeroext i1 @vpreduce_xor_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {300; CHECK-LABEL: vpreduce_xor_nxv64i1:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma303; CHECK-NEXT: vmv1r.v v9, v0304; CHECK-NEXT: vmv1r.v v0, v8305; CHECK-NEXT: vcpop.m a1, v9, v0.t306; CHECK-NEXT: andi a1, a1, 1307; CHECK-NEXT: xor a0, a1, a0308; CHECK-NEXT: ret309 %r = call i1 @llvm.vp.reduce.xor.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)310 ret i1 %r311}312 313define zeroext i1 @vpreduce_or_nxv128i1(i1 zeroext %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 zeroext %evl) {314; CHECK-LABEL: vpreduce_or_nxv128i1:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma317; CHECK-NEXT: vmv1r.v v11, v0318; CHECK-NEXT: csrr a2, vlenb319; CHECK-NEXT: slli a2, a2, 3320; CHECK-NEXT: sub a3, a1, a2321; CHECK-NEXT: sltu a4, a1, a3322; CHECK-NEXT: addi a4, a4, -1323; CHECK-NEXT: and a3, a4, a3324; CHECK-NEXT: vmv1r.v v0, v10325; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma326; CHECK-NEXT: vcpop.m a3, v8, v0.t327; CHECK-NEXT: snez a3, a3328; CHECK-NEXT: bltu a1, a2, .LBB22_2329; CHECK-NEXT: # %bb.1:330; CHECK-NEXT: mv a1, a2331; CHECK-NEXT: .LBB22_2:332; CHECK-NEXT: vmv1r.v v0, v9333; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma334; CHECK-NEXT: vcpop.m a1, v11, v0.t335; CHECK-NEXT: snez a1, a1336; CHECK-NEXT: or a0, a1, a0337; CHECK-NEXT: or a0, a3, a0338; CHECK-NEXT: ret339 %r = call i1 @llvm.vp.reduce.or.nxv128i1(i1 %s, <vscale x 128 x i1> %v, <vscale x 128 x i1> %m, i32 %evl)340 ret i1 %r341}342 343define zeroext i1 @vpreduce_add_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {344; CHECK-LABEL: vpreduce_add_nxv1i1:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma347; CHECK-NEXT: vmv1r.v v9, v0348; CHECK-NEXT: vmv1r.v v0, v8349; CHECK-NEXT: vcpop.m a1, v9, v0.t350; CHECK-NEXT: andi a1, a1, 1351; CHECK-NEXT: xor a0, a1, a0352; CHECK-NEXT: ret353 %r = call i1 @llvm.vp.reduce.add.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)354 ret i1 %r355}356 357define zeroext i1 @vpreduce_add_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {358; CHECK-LABEL: vpreduce_add_nxv2i1:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma361; CHECK-NEXT: vmv1r.v v9, v0362; CHECK-NEXT: vmv1r.v v0, v8363; CHECK-NEXT: vcpop.m a1, v9, v0.t364; CHECK-NEXT: andi a1, a1, 1365; CHECK-NEXT: xor a0, a1, a0366; CHECK-NEXT: ret367 %r = call i1 @llvm.vp.reduce.add.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)368 ret i1 %r369}370 371define zeroext i1 @vpreduce_add_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {372; CHECK-LABEL: vpreduce_add_nxv4i1:373; CHECK: # %bb.0:374; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma375; CHECK-NEXT: vmv1r.v v9, v0376; CHECK-NEXT: vmv1r.v v0, v8377; CHECK-NEXT: vcpop.m a1, v9, v0.t378; CHECK-NEXT: andi a1, a1, 1379; CHECK-NEXT: xor a0, a1, a0380; CHECK-NEXT: ret381 %r = call i1 @llvm.vp.reduce.add.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)382 ret i1 %r383}384 385define zeroext i1 @vpreduce_add_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {386; CHECK-LABEL: vpreduce_add_nxv8i1:387; CHECK: # %bb.0:388; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma389; CHECK-NEXT: vmv1r.v v9, v0390; CHECK-NEXT: vmv1r.v v0, v8391; CHECK-NEXT: vcpop.m a1, v9, v0.t392; CHECK-NEXT: andi a1, a1, 1393; CHECK-NEXT: xor a0, a1, a0394; CHECK-NEXT: ret395 %r = call i1 @llvm.vp.reduce.add.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)396 ret i1 %r397}398 399define zeroext i1 @vpreduce_add_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {400; CHECK-LABEL: vpreduce_add_nxv16i1:401; CHECK: # %bb.0:402; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma403; CHECK-NEXT: vmv1r.v v9, v0404; CHECK-NEXT: vmv1r.v v0, v8405; CHECK-NEXT: vcpop.m a1, v9, v0.t406; CHECK-NEXT: andi a1, a1, 1407; CHECK-NEXT: xor a0, a1, a0408; CHECK-NEXT: ret409 %r = call i1 @llvm.vp.reduce.add.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)410 ret i1 %r411}412 413define zeroext i1 @vpreduce_add_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {414; CHECK-LABEL: vpreduce_add_nxv32i1:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma417; CHECK-NEXT: vmv1r.v v9, v0418; CHECK-NEXT: vmv1r.v v0, v8419; CHECK-NEXT: vcpop.m a1, v9, v0.t420; CHECK-NEXT: andi a1, a1, 1421; CHECK-NEXT: xor a0, a1, a0422; CHECK-NEXT: ret423 %r = call i1 @llvm.vp.reduce.add.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)424 ret i1 %r425}426 427define zeroext i1 @vpreduce_add_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {428; CHECK-LABEL: vpreduce_add_nxv64i1:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma431; CHECK-NEXT: vmv1r.v v9, v0432; CHECK-NEXT: vmv1r.v v0, v8433; CHECK-NEXT: vcpop.m a1, v9, v0.t434; CHECK-NEXT: andi a1, a1, 1435; CHECK-NEXT: xor a0, a1, a0436; CHECK-NEXT: ret437 %r = call i1 @llvm.vp.reduce.add.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)438 ret i1 %r439}440 441define zeroext i1 @vpreduce_smax_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {442; CHECK-LABEL: vpreduce_smax_nxv1i1:443; CHECK: # %bb.0:444; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma445; CHECK-NEXT: vmnot.m v9, v0446; CHECK-NEXT: vmv1r.v v0, v8447; CHECK-NEXT: vcpop.m a1, v9, v0.t448; CHECK-NEXT: seqz a1, a1449; CHECK-NEXT: and a0, a1, a0450; CHECK-NEXT: ret451 %r = call i1 @llvm.vp.reduce.smax.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)452 ret i1 %r453}454 455define zeroext i1 @vpreduce_smax_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {456; CHECK-LABEL: vpreduce_smax_nxv2i1:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma459; CHECK-NEXT: vmnot.m v9, v0460; CHECK-NEXT: vmv1r.v v0, v8461; CHECK-NEXT: vcpop.m a1, v9, v0.t462; CHECK-NEXT: seqz a1, a1463; CHECK-NEXT: and a0, a1, a0464; CHECK-NEXT: ret465 %r = call i1 @llvm.vp.reduce.smax.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)466 ret i1 %r467}468 469define zeroext i1 @vpreduce_smax_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {470; CHECK-LABEL: vpreduce_smax_nxv4i1:471; CHECK: # %bb.0:472; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma473; CHECK-NEXT: vmnot.m v9, v0474; CHECK-NEXT: vmv1r.v v0, v8475; CHECK-NEXT: vcpop.m a1, v9, v0.t476; CHECK-NEXT: seqz a1, a1477; CHECK-NEXT: and a0, a1, a0478; CHECK-NEXT: ret479 %r = call i1 @llvm.vp.reduce.smax.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)480 ret i1 %r481}482 483define zeroext i1 @vpreduce_smax_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {484; CHECK-LABEL: vpreduce_smax_nxv8i1:485; CHECK: # %bb.0:486; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma487; CHECK-NEXT: vmnot.m v9, v0488; CHECK-NEXT: vmv1r.v v0, v8489; CHECK-NEXT: vcpop.m a1, v9, v0.t490; CHECK-NEXT: seqz a1, a1491; CHECK-NEXT: and a0, a1, a0492; CHECK-NEXT: ret493 %r = call i1 @llvm.vp.reduce.smax.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)494 ret i1 %r495}496 497define zeroext i1 @vpreduce_smax_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {498; CHECK-LABEL: vpreduce_smax_nxv16i1:499; CHECK: # %bb.0:500; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma501; CHECK-NEXT: vmnot.m v9, v0502; CHECK-NEXT: vmv1r.v v0, v8503; CHECK-NEXT: vcpop.m a1, v9, v0.t504; CHECK-NEXT: seqz a1, a1505; CHECK-NEXT: and a0, a1, a0506; CHECK-NEXT: ret507 %r = call i1 @llvm.vp.reduce.smax.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)508 ret i1 %r509}510 511define zeroext i1 @vpreduce_smax_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {512; CHECK-LABEL: vpreduce_smax_nxv32i1:513; CHECK: # %bb.0:514; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma515; CHECK-NEXT: vmnot.m v9, v0516; CHECK-NEXT: vmv1r.v v0, v8517; CHECK-NEXT: vcpop.m a1, v9, v0.t518; CHECK-NEXT: seqz a1, a1519; CHECK-NEXT: and a0, a1, a0520; CHECK-NEXT: ret521 %r = call i1 @llvm.vp.reduce.smax.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)522 ret i1 %r523}524 525define zeroext i1 @vpreduce_smax_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {526; CHECK-LABEL: vpreduce_smax_nxv64i1:527; CHECK: # %bb.0:528; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma529; CHECK-NEXT: vmnot.m v9, v0530; CHECK-NEXT: vmv1r.v v0, v8531; CHECK-NEXT: vcpop.m a1, v9, v0.t532; CHECK-NEXT: seqz a1, a1533; CHECK-NEXT: and a0, a1, a0534; CHECK-NEXT: ret535 %r = call i1 @llvm.vp.reduce.smax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)536 ret i1 %r537}538 539define zeroext i1 @vpreduce_smin_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {540; CHECK-LABEL: vpreduce_smin_nxv1i1:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma543; CHECK-NEXT: vmv1r.v v9, v0544; CHECK-NEXT: vmv1r.v v0, v8545; CHECK-NEXT: vcpop.m a1, v9, v0.t546; CHECK-NEXT: snez a1, a1547; CHECK-NEXT: or a0, a1, a0548; CHECK-NEXT: ret549 %r = call i1 @llvm.vp.reduce.smin.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)550 ret i1 %r551}552 553define zeroext i1 @vpreduce_smin_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {554; CHECK-LABEL: vpreduce_smin_nxv2i1:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma557; CHECK-NEXT: vmv1r.v v9, v0558; CHECK-NEXT: vmv1r.v v0, v8559; CHECK-NEXT: vcpop.m a1, v9, v0.t560; CHECK-NEXT: snez a1, a1561; CHECK-NEXT: or a0, a1, a0562; CHECK-NEXT: ret563 %r = call i1 @llvm.vp.reduce.smin.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)564 ret i1 %r565}566 567define zeroext i1 @vpreduce_smin_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {568; CHECK-LABEL: vpreduce_smin_nxv4i1:569; CHECK: # %bb.0:570; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma571; CHECK-NEXT: vmv1r.v v9, v0572; CHECK-NEXT: vmv1r.v v0, v8573; CHECK-NEXT: vcpop.m a1, v9, v0.t574; CHECK-NEXT: snez a1, a1575; CHECK-NEXT: or a0, a1, a0576; CHECK-NEXT: ret577 %r = call i1 @llvm.vp.reduce.smin.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)578 ret i1 %r579}580 581define zeroext i1 @vpreduce_smin_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {582; CHECK-LABEL: vpreduce_smin_nxv8i1:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma585; CHECK-NEXT: vmv1r.v v9, v0586; CHECK-NEXT: vmv1r.v v0, v8587; CHECK-NEXT: vcpop.m a1, v9, v0.t588; CHECK-NEXT: snez a1, a1589; CHECK-NEXT: or a0, a1, a0590; CHECK-NEXT: ret591 %r = call i1 @llvm.vp.reduce.smin.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)592 ret i1 %r593}594 595define zeroext i1 @vpreduce_smin_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {596; CHECK-LABEL: vpreduce_smin_nxv16i1:597; CHECK: # %bb.0:598; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma599; CHECK-NEXT: vmv1r.v v9, v0600; CHECK-NEXT: vmv1r.v v0, v8601; CHECK-NEXT: vcpop.m a1, v9, v0.t602; CHECK-NEXT: snez a1, a1603; CHECK-NEXT: or a0, a1, a0604; CHECK-NEXT: ret605 %r = call i1 @llvm.vp.reduce.smin.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)606 ret i1 %r607}608 609define zeroext i1 @vpreduce_smin_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {610; CHECK-LABEL: vpreduce_smin_nxv32i1:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma613; CHECK-NEXT: vmv1r.v v9, v0614; CHECK-NEXT: vmv1r.v v0, v8615; CHECK-NEXT: vcpop.m a1, v9, v0.t616; CHECK-NEXT: snez a1, a1617; CHECK-NEXT: or a0, a1, a0618; CHECK-NEXT: ret619 %r = call i1 @llvm.vp.reduce.smin.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)620 ret i1 %r621}622 623define zeroext i1 @vpreduce_smin_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {624; CHECK-LABEL: vpreduce_smin_nxv64i1:625; CHECK: # %bb.0:626; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma627; CHECK-NEXT: vmv1r.v v9, v0628; CHECK-NEXT: vmv1r.v v0, v8629; CHECK-NEXT: vcpop.m a1, v9, v0.t630; CHECK-NEXT: snez a1, a1631; CHECK-NEXT: or a0, a1, a0632; CHECK-NEXT: ret633 %r = call i1 @llvm.vp.reduce.smin.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)634 ret i1 %r635}636 637define zeroext i1 @vpreduce_umax_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {638; CHECK-LABEL: vpreduce_umax_nxv1i1:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma641; CHECK-NEXT: vmv1r.v v9, v0642; CHECK-NEXT: vmv1r.v v0, v8643; CHECK-NEXT: vcpop.m a1, v9, v0.t644; CHECK-NEXT: snez a1, a1645; CHECK-NEXT: or a0, a1, a0646; CHECK-NEXT: ret647 %r = call i1 @llvm.vp.reduce.umax.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)648 ret i1 %r649}650 651define zeroext i1 @vpreduce_umax_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {652; CHECK-LABEL: vpreduce_umax_nxv2i1:653; CHECK: # %bb.0:654; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma655; CHECK-NEXT: vmv1r.v v9, v0656; CHECK-NEXT: vmv1r.v v0, v8657; CHECK-NEXT: vcpop.m a1, v9, v0.t658; CHECK-NEXT: snez a1, a1659; CHECK-NEXT: or a0, a1, a0660; CHECK-NEXT: ret661 %r = call i1 @llvm.vp.reduce.umax.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)662 ret i1 %r663}664 665define zeroext i1 @vpreduce_umax_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {666; CHECK-LABEL: vpreduce_umax_nxv4i1:667; CHECK: # %bb.0:668; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma669; CHECK-NEXT: vmv1r.v v9, v0670; CHECK-NEXT: vmv1r.v v0, v8671; CHECK-NEXT: vcpop.m a1, v9, v0.t672; CHECK-NEXT: snez a1, a1673; CHECK-NEXT: or a0, a1, a0674; CHECK-NEXT: ret675 %r = call i1 @llvm.vp.reduce.umax.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)676 ret i1 %r677}678 679define zeroext i1 @vpreduce_umax_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {680; CHECK-LABEL: vpreduce_umax_nxv8i1:681; CHECK: # %bb.0:682; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma683; CHECK-NEXT: vmv1r.v v9, v0684; CHECK-NEXT: vmv1r.v v0, v8685; CHECK-NEXT: vcpop.m a1, v9, v0.t686; CHECK-NEXT: snez a1, a1687; CHECK-NEXT: or a0, a1, a0688; CHECK-NEXT: ret689 %r = call i1 @llvm.vp.reduce.umax.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)690 ret i1 %r691}692 693define zeroext i1 @vpreduce_umax_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {694; CHECK-LABEL: vpreduce_umax_nxv16i1:695; CHECK: # %bb.0:696; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma697; CHECK-NEXT: vmv1r.v v9, v0698; CHECK-NEXT: vmv1r.v v0, v8699; CHECK-NEXT: vcpop.m a1, v9, v0.t700; CHECK-NEXT: snez a1, a1701; CHECK-NEXT: or a0, a1, a0702; CHECK-NEXT: ret703 %r = call i1 @llvm.vp.reduce.umax.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)704 ret i1 %r705}706 707define zeroext i1 @vpreduce_umax_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {708; CHECK-LABEL: vpreduce_umax_nxv32i1:709; CHECK: # %bb.0:710; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma711; CHECK-NEXT: vmv1r.v v9, v0712; CHECK-NEXT: vmv1r.v v0, v8713; CHECK-NEXT: vcpop.m a1, v9, v0.t714; CHECK-NEXT: snez a1, a1715; CHECK-NEXT: or a0, a1, a0716; CHECK-NEXT: ret717 %r = call i1 @llvm.vp.reduce.umax.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)718 ret i1 %r719}720 721define zeroext i1 @vpreduce_umax_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {722; CHECK-LABEL: vpreduce_umax_nxv64i1:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma725; CHECK-NEXT: vmv1r.v v9, v0726; CHECK-NEXT: vmv1r.v v0, v8727; CHECK-NEXT: vcpop.m a1, v9, v0.t728; CHECK-NEXT: snez a1, a1729; CHECK-NEXT: or a0, a1, a0730; CHECK-NEXT: ret731 %r = call i1 @llvm.vp.reduce.umax.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)732 ret i1 %r733}734 735define zeroext i1 @vpreduce_umin_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {736; CHECK-LABEL: vpreduce_umin_nxv1i1:737; CHECK: # %bb.0:738; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma739; CHECK-NEXT: vmnot.m v9, v0740; CHECK-NEXT: vmv1r.v v0, v8741; CHECK-NEXT: vcpop.m a1, v9, v0.t742; CHECK-NEXT: seqz a1, a1743; CHECK-NEXT: and a0, a1, a0744; CHECK-NEXT: ret745 %r = call i1 @llvm.vp.reduce.umin.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)746 ret i1 %r747}748 749define zeroext i1 @vpreduce_umin_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {750; CHECK-LABEL: vpreduce_umin_nxv2i1:751; CHECK: # %bb.0:752; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma753; CHECK-NEXT: vmnot.m v9, v0754; CHECK-NEXT: vmv1r.v v0, v8755; CHECK-NEXT: vcpop.m a1, v9, v0.t756; CHECK-NEXT: seqz a1, a1757; CHECK-NEXT: and a0, a1, a0758; CHECK-NEXT: ret759 %r = call i1 @llvm.vp.reduce.umin.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)760 ret i1 %r761}762 763define zeroext i1 @vpreduce_umin_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {764; CHECK-LABEL: vpreduce_umin_nxv4i1:765; CHECK: # %bb.0:766; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma767; CHECK-NEXT: vmnot.m v9, v0768; CHECK-NEXT: vmv1r.v v0, v8769; CHECK-NEXT: vcpop.m a1, v9, v0.t770; CHECK-NEXT: seqz a1, a1771; CHECK-NEXT: and a0, a1, a0772; CHECK-NEXT: ret773 %r = call i1 @llvm.vp.reduce.umin.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)774 ret i1 %r775}776 777define zeroext i1 @vpreduce_umin_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {778; CHECK-LABEL: vpreduce_umin_nxv8i1:779; CHECK: # %bb.0:780; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma781; CHECK-NEXT: vmnot.m v9, v0782; CHECK-NEXT: vmv1r.v v0, v8783; CHECK-NEXT: vcpop.m a1, v9, v0.t784; CHECK-NEXT: seqz a1, a1785; CHECK-NEXT: and a0, a1, a0786; CHECK-NEXT: ret787 %r = call i1 @llvm.vp.reduce.umin.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)788 ret i1 %r789}790 791define zeroext i1 @vpreduce_umin_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {792; CHECK-LABEL: vpreduce_umin_nxv16i1:793; CHECK: # %bb.0:794; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma795; CHECK-NEXT: vmnot.m v9, v0796; CHECK-NEXT: vmv1r.v v0, v8797; CHECK-NEXT: vcpop.m a1, v9, v0.t798; CHECK-NEXT: seqz a1, a1799; CHECK-NEXT: and a0, a1, a0800; CHECK-NEXT: ret801 %r = call i1 @llvm.vp.reduce.umin.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)802 ret i1 %r803}804 805define zeroext i1 @vpreduce_umin_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {806; CHECK-LABEL: vpreduce_umin_nxv32i1:807; CHECK: # %bb.0:808; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma809; CHECK-NEXT: vmnot.m v9, v0810; CHECK-NEXT: vmv1r.v v0, v8811; CHECK-NEXT: vcpop.m a1, v9, v0.t812; CHECK-NEXT: seqz a1, a1813; CHECK-NEXT: and a0, a1, a0814; CHECK-NEXT: ret815 %r = call i1 @llvm.vp.reduce.umin.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)816 ret i1 %r817}818 819define zeroext i1 @vpreduce_umin_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {820; CHECK-LABEL: vpreduce_umin_nxv64i1:821; CHECK: # %bb.0:822; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma823; CHECK-NEXT: vmnot.m v9, v0824; CHECK-NEXT: vmv1r.v v0, v8825; CHECK-NEXT: vcpop.m a1, v9, v0.t826; CHECK-NEXT: seqz a1, a1827; CHECK-NEXT: and a0, a1, a0828; CHECK-NEXT: ret829 %r = call i1 @llvm.vp.reduce.umin.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)830 ret i1 %r831}832 833define zeroext i1 @vpreduce_mul_nxv1i1(i1 zeroext %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 zeroext %evl) {834; CHECK-LABEL: vpreduce_mul_nxv1i1:835; CHECK: # %bb.0:836; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma837; CHECK-NEXT: vmnot.m v9, v0838; CHECK-NEXT: vmv1r.v v0, v8839; CHECK-NEXT: vcpop.m a1, v9, v0.t840; CHECK-NEXT: seqz a1, a1841; CHECK-NEXT: and a0, a1, a0842; CHECK-NEXT: ret843 %r = call i1 @llvm.vp.reduce.mul.nxv1i1(i1 %s, <vscale x 1 x i1> %v, <vscale x 1 x i1> %m, i32 %evl)844 ret i1 %r845}846 847define zeroext i1 @vpreduce_mul_nxv2i1(i1 zeroext %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 zeroext %evl) {848; CHECK-LABEL: vpreduce_mul_nxv2i1:849; CHECK: # %bb.0:850; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma851; CHECK-NEXT: vmnot.m v9, v0852; CHECK-NEXT: vmv1r.v v0, v8853; CHECK-NEXT: vcpop.m a1, v9, v0.t854; CHECK-NEXT: seqz a1, a1855; CHECK-NEXT: and a0, a1, a0856; CHECK-NEXT: ret857 %r = call i1 @llvm.vp.reduce.mul.nxv2i1(i1 %s, <vscale x 2 x i1> %v, <vscale x 2 x i1> %m, i32 %evl)858 ret i1 %r859}860 861define zeroext i1 @vpreduce_mul_nxv4i1(i1 zeroext %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 zeroext %evl) {862; CHECK-LABEL: vpreduce_mul_nxv4i1:863; CHECK: # %bb.0:864; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma865; CHECK-NEXT: vmnot.m v9, v0866; CHECK-NEXT: vmv1r.v v0, v8867; CHECK-NEXT: vcpop.m a1, v9, v0.t868; CHECK-NEXT: seqz a1, a1869; CHECK-NEXT: and a0, a1, a0870; CHECK-NEXT: ret871 %r = call i1 @llvm.vp.reduce.mul.nxv4i1(i1 %s, <vscale x 4 x i1> %v, <vscale x 4 x i1> %m, i32 %evl)872 ret i1 %r873}874 875define zeroext i1 @vpreduce_mul_nxv8i1(i1 zeroext %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 zeroext %evl) {876; CHECK-LABEL: vpreduce_mul_nxv8i1:877; CHECK: # %bb.0:878; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma879; CHECK-NEXT: vmnot.m v9, v0880; CHECK-NEXT: vmv1r.v v0, v8881; CHECK-NEXT: vcpop.m a1, v9, v0.t882; CHECK-NEXT: seqz a1, a1883; CHECK-NEXT: and a0, a1, a0884; CHECK-NEXT: ret885 %r = call i1 @llvm.vp.reduce.mul.nxv8i1(i1 %s, <vscale x 8 x i1> %v, <vscale x 8 x i1> %m, i32 %evl)886 ret i1 %r887}888 889define zeroext i1 @vpreduce_mul_nxv16i1(i1 zeroext %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 zeroext %evl) {890; CHECK-LABEL: vpreduce_mul_nxv16i1:891; CHECK: # %bb.0:892; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma893; CHECK-NEXT: vmnot.m v9, v0894; CHECK-NEXT: vmv1r.v v0, v8895; CHECK-NEXT: vcpop.m a1, v9, v0.t896; CHECK-NEXT: seqz a1, a1897; CHECK-NEXT: and a0, a1, a0898; CHECK-NEXT: ret899 %r = call i1 @llvm.vp.reduce.mul.nxv16i1(i1 %s, <vscale x 16 x i1> %v, <vscale x 16 x i1> %m, i32 %evl)900 ret i1 %r901}902 903define zeroext i1 @vpreduce_mul_nxv32i1(i1 zeroext %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {904; CHECK-LABEL: vpreduce_mul_nxv32i1:905; CHECK: # %bb.0:906; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma907; CHECK-NEXT: vmnot.m v9, v0908; CHECK-NEXT: vmv1r.v v0, v8909; CHECK-NEXT: vcpop.m a1, v9, v0.t910; CHECK-NEXT: seqz a1, a1911; CHECK-NEXT: and a0, a1, a0912; CHECK-NEXT: ret913 %r = call i1 @llvm.vp.reduce.mul.nxv32i1(i1 %s, <vscale x 32 x i1> %v, <vscale x 32 x i1> %m, i32 %evl)914 ret i1 %r915}916 917define zeroext i1 @vpreduce_mul_nxv64i1(i1 zeroext %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {918; CHECK-LABEL: vpreduce_mul_nxv64i1:919; CHECK: # %bb.0:920; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma921; CHECK-NEXT: vmnot.m v9, v0922; CHECK-NEXT: vmv1r.v v0, v8923; CHECK-NEXT: vcpop.m a1, v9, v0.t924; CHECK-NEXT: seqz a1, a1925; CHECK-NEXT: and a0, a1, a0926; CHECK-NEXT: ret927 %r = call i1 @llvm.vp.reduce.mul.nxv64i1(i1 %s, <vscale x 64 x i1> %v, <vscale x 64 x i1> %m, i32 %evl)928 ret i1 %r929}930