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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s4 5define zeroext i1 @vreduce_or_nxv1i1(<vscale x 1 x i1> %v) {6; CHECK-LABEL: vreduce_or_nxv1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vcpop.m a0, v010; CHECK-NEXT: snez a0, a011; CHECK-NEXT: ret12 %red = call i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1> %v)13 ret i1 %red14}15 16define zeroext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {17; CHECK-LABEL: vreduce_xor_nxv1i1:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma20; CHECK-NEXT: vcpop.m a0, v021; CHECK-NEXT: andi a0, a0, 122; CHECK-NEXT: ret23 %red = call i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1> %v)24 ret i1 %red25}26 27define zeroext i1 @vreduce_and_nxv1i1(<vscale x 1 x i1> %v) {28; CHECK-LABEL: vreduce_and_nxv1i1:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma31; CHECK-NEXT: vmnot.m v8, v032; CHECK-NEXT: vcpop.m a0, v833; CHECK-NEXT: seqz a0, a034; CHECK-NEXT: ret35 %red = call i1 @llvm.vector.reduce.and.nxv1i1(<vscale x 1 x i1> %v)36 ret i1 %red37}38 39define zeroext i1 @vreduce_umax_nxv1i1(<vscale x 1 x i1> %v) {40; CHECK-LABEL: vreduce_umax_nxv1i1:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma43; CHECK-NEXT: vcpop.m a0, v044; CHECK-NEXT: snez a0, a045; CHECK-NEXT: ret46 %red = call i1 @llvm.vector.reduce.umax.nxv1i1(<vscale x 1 x i1> %v)47 ret i1 %red48}49 50define zeroext i1 @vreduce_smax_nxv1i1(<vscale x 1 x i1> %v) {51; CHECK-LABEL: vreduce_smax_nxv1i1:52; CHECK: # %bb.0:53; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma54; CHECK-NEXT: vmnot.m v8, v055; CHECK-NEXT: vcpop.m a0, v856; CHECK-NEXT: seqz a0, a057; CHECK-NEXT: ret58 %red = call i1 @llvm.vector.reduce.smax.nxv1i1(<vscale x 1 x i1> %v)59 ret i1 %red60}61 62define zeroext i1 @vreduce_umin_nxv1i1(<vscale x 1 x i1> %v) {63; CHECK-LABEL: vreduce_umin_nxv1i1:64; CHECK: # %bb.0:65; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma66; CHECK-NEXT: vmnot.m v8, v067; CHECK-NEXT: vcpop.m a0, v868; CHECK-NEXT: seqz a0, a069; CHECK-NEXT: ret70 %red = call i1 @llvm.vector.reduce.umin.nxv1i1(<vscale x 1 x i1> %v)71 ret i1 %red72}73 74define zeroext i1 @vreduce_smin_nxv1i1(<vscale x 1 x i1> %v) {75; CHECK-LABEL: vreduce_smin_nxv1i1:76; CHECK: # %bb.0:77; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma78; CHECK-NEXT: vcpop.m a0, v079; CHECK-NEXT: snez a0, a080; CHECK-NEXT: ret81 %red = call i1 @llvm.vector.reduce.smin.nxv1i1(<vscale x 1 x i1> %v)82 ret i1 %red83}84 85define zeroext i1 @vreduce_or_nxv2i1(<vscale x 2 x i1> %v) {86; CHECK-LABEL: vreduce_or_nxv2i1:87; CHECK: # %bb.0:88; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma89; CHECK-NEXT: vcpop.m a0, v090; CHECK-NEXT: snez a0, a091; CHECK-NEXT: ret92 %red = call i1 @llvm.vector.reduce.or.nxv2i1(<vscale x 2 x i1> %v)93 ret i1 %red94}95 96define zeroext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {97; CHECK-LABEL: vreduce_xor_nxv2i1:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma100; CHECK-NEXT: vcpop.m a0, v0101; CHECK-NEXT: andi a0, a0, 1102; CHECK-NEXT: ret103 %red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %v)104 ret i1 %red105}106 107define zeroext i1 @vreduce_and_nxv2i1(<vscale x 2 x i1> %v) {108; CHECK-LABEL: vreduce_and_nxv2i1:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma111; CHECK-NEXT: vmnot.m v8, v0112; CHECK-NEXT: vcpop.m a0, v8113; CHECK-NEXT: seqz a0, a0114; CHECK-NEXT: ret115 %red = call i1 @llvm.vector.reduce.and.nxv2i1(<vscale x 2 x i1> %v)116 ret i1 %red117}118 119define zeroext i1 @vreduce_umax_nxv2i1(<vscale x 2 x i1> %v) {120; CHECK-LABEL: vreduce_umax_nxv2i1:121; CHECK: # %bb.0:122; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma123; CHECK-NEXT: vcpop.m a0, v0124; CHECK-NEXT: snez a0, a0125; CHECK-NEXT: ret126 %red = call i1 @llvm.vector.reduce.umax.nxv2i1(<vscale x 2 x i1> %v)127 ret i1 %red128}129 130define zeroext i1 @vreduce_smax_nxv2i1(<vscale x 2 x i1> %v) {131; CHECK-LABEL: vreduce_smax_nxv2i1:132; CHECK: # %bb.0:133; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma134; CHECK-NEXT: vmnot.m v8, v0135; CHECK-NEXT: vcpop.m a0, v8136; CHECK-NEXT: seqz a0, a0137; CHECK-NEXT: ret138 %red = call i1 @llvm.vector.reduce.smax.nxv2i1(<vscale x 2 x i1> %v)139 ret i1 %red140}141 142define zeroext i1 @vreduce_umin_nxv2i1(<vscale x 2 x i1> %v) {143; CHECK-LABEL: vreduce_umin_nxv2i1:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma146; CHECK-NEXT: vmnot.m v8, v0147; CHECK-NEXT: vcpop.m a0, v8148; CHECK-NEXT: seqz a0, a0149; CHECK-NEXT: ret150 %red = call i1 @llvm.vector.reduce.umin.nxv2i1(<vscale x 2 x i1> %v)151 ret i1 %red152}153 154define zeroext i1 @vreduce_smin_nxv2i1(<vscale x 2 x i1> %v) {155; CHECK-LABEL: vreduce_smin_nxv2i1:156; CHECK: # %bb.0:157; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma158; CHECK-NEXT: vcpop.m a0, v0159; CHECK-NEXT: snez a0, a0160; CHECK-NEXT: ret161 %red = call i1 @llvm.vector.reduce.smin.nxv2i1(<vscale x 2 x i1> %v)162 ret i1 %red163}164 165define zeroext i1 @vreduce_or_nxv4i1(<vscale x 4 x i1> %v) {166; CHECK-LABEL: vreduce_or_nxv4i1:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma169; CHECK-NEXT: vcpop.m a0, v0170; CHECK-NEXT: snez a0, a0171; CHECK-NEXT: ret172 %red = call i1 @llvm.vector.reduce.or.nxv4i1(<vscale x 4 x i1> %v)173 ret i1 %red174}175 176define zeroext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {177; CHECK-LABEL: vreduce_xor_nxv4i1:178; CHECK: # %bb.0:179; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma180; CHECK-NEXT: vcpop.m a0, v0181; CHECK-NEXT: andi a0, a0, 1182; CHECK-NEXT: ret183 %red = call i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1> %v)184 ret i1 %red185}186 187define zeroext i1 @vreduce_and_nxv4i1(<vscale x 4 x i1> %v) {188; CHECK-LABEL: vreduce_and_nxv4i1:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma191; CHECK-NEXT: vmnot.m v8, v0192; CHECK-NEXT: vcpop.m a0, v8193; CHECK-NEXT: seqz a0, a0194; CHECK-NEXT: ret195 %red = call i1 @llvm.vector.reduce.and.nxv4i1(<vscale x 4 x i1> %v)196 ret i1 %red197}198 199define zeroext i1 @vreduce_umax_nxv4i1(<vscale x 4 x i1> %v) {200; CHECK-LABEL: vreduce_umax_nxv4i1:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma203; CHECK-NEXT: vcpop.m a0, v0204; CHECK-NEXT: snez a0, a0205; CHECK-NEXT: ret206 %red = call i1 @llvm.vector.reduce.umax.nxv4i1(<vscale x 4 x i1> %v)207 ret i1 %red208}209 210define zeroext i1 @vreduce_smax_nxv4i1(<vscale x 4 x i1> %v) {211; CHECK-LABEL: vreduce_smax_nxv4i1:212; CHECK: # %bb.0:213; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma214; CHECK-NEXT: vmnot.m v8, v0215; CHECK-NEXT: vcpop.m a0, v8216; CHECK-NEXT: seqz a0, a0217; CHECK-NEXT: ret218 %red = call i1 @llvm.vector.reduce.smax.nxv4i1(<vscale x 4 x i1> %v)219 ret i1 %red220}221 222define zeroext i1 @vreduce_umin_nxv4i1(<vscale x 4 x i1> %v) {223; CHECK-LABEL: vreduce_umin_nxv4i1:224; CHECK: # %bb.0:225; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma226; CHECK-NEXT: vmnot.m v8, v0227; CHECK-NEXT: vcpop.m a0, v8228; CHECK-NEXT: seqz a0, a0229; CHECK-NEXT: ret230 %red = call i1 @llvm.vector.reduce.umin.nxv4i1(<vscale x 4 x i1> %v)231 ret i1 %red232}233 234define zeroext i1 @vreduce_smin_nxv4i1(<vscale x 4 x i1> %v) {235; CHECK-LABEL: vreduce_smin_nxv4i1:236; CHECK: # %bb.0:237; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma238; CHECK-NEXT: vcpop.m a0, v0239; CHECK-NEXT: snez a0, a0240; CHECK-NEXT: ret241 %red = call i1 @llvm.vector.reduce.smin.nxv4i1(<vscale x 4 x i1> %v)242 ret i1 %red243}244 245define zeroext i1 @vreduce_or_nxv8i1(<vscale x 8 x i1> %v) {246; CHECK-LABEL: vreduce_or_nxv8i1:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma249; CHECK-NEXT: vcpop.m a0, v0250; CHECK-NEXT: snez a0, a0251; CHECK-NEXT: ret252 %red = call i1 @llvm.vector.reduce.or.nxv8i1(<vscale x 8 x i1> %v)253 ret i1 %red254}255 256define zeroext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {257; CHECK-LABEL: vreduce_xor_nxv8i1:258; CHECK: # %bb.0:259; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma260; CHECK-NEXT: vcpop.m a0, v0261; CHECK-NEXT: andi a0, a0, 1262; CHECK-NEXT: ret263 %red = call i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1> %v)264 ret i1 %red265}266 267define zeroext i1 @vreduce_and_nxv8i1(<vscale x 8 x i1> %v) {268; CHECK-LABEL: vreduce_and_nxv8i1:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma271; CHECK-NEXT: vmnot.m v8, v0272; CHECK-NEXT: vcpop.m a0, v8273; CHECK-NEXT: seqz a0, a0274; CHECK-NEXT: ret275 %red = call i1 @llvm.vector.reduce.and.nxv8i1(<vscale x 8 x i1> %v)276 ret i1 %red277}278 279define zeroext i1 @vreduce_umax_nxv8i1(<vscale x 8 x i1> %v) {280; CHECK-LABEL: vreduce_umax_nxv8i1:281; CHECK: # %bb.0:282; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma283; CHECK-NEXT: vcpop.m a0, v0284; CHECK-NEXT: snez a0, a0285; CHECK-NEXT: ret286 %red = call i1 @llvm.vector.reduce.umax.nxv8i1(<vscale x 8 x i1> %v)287 ret i1 %red288}289 290define zeroext i1 @vreduce_smax_nxv8i1(<vscale x 8 x i1> %v) {291; CHECK-LABEL: vreduce_smax_nxv8i1:292; CHECK: # %bb.0:293; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma294; CHECK-NEXT: vmnot.m v8, v0295; CHECK-NEXT: vcpop.m a0, v8296; CHECK-NEXT: seqz a0, a0297; CHECK-NEXT: ret298 %red = call i1 @llvm.vector.reduce.smax.nxv8i1(<vscale x 8 x i1> %v)299 ret i1 %red300}301 302define zeroext i1 @vreduce_umin_nxv8i1(<vscale x 8 x i1> %v) {303; CHECK-LABEL: vreduce_umin_nxv8i1:304; CHECK: # %bb.0:305; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma306; CHECK-NEXT: vmnot.m v8, v0307; CHECK-NEXT: vcpop.m a0, v8308; CHECK-NEXT: seqz a0, a0309; CHECK-NEXT: ret310 %red = call i1 @llvm.vector.reduce.umin.nxv8i1(<vscale x 8 x i1> %v)311 ret i1 %red312}313 314define zeroext i1 @vreduce_smin_nxv8i1(<vscale x 8 x i1> %v) {315; CHECK-LABEL: vreduce_smin_nxv8i1:316; CHECK: # %bb.0:317; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma318; CHECK-NEXT: vcpop.m a0, v0319; CHECK-NEXT: snez a0, a0320; CHECK-NEXT: ret321 %red = call i1 @llvm.vector.reduce.smin.nxv8i1(<vscale x 8 x i1> %v)322 ret i1 %red323}324 325define zeroext i1 @vreduce_or_nxv16i1(<vscale x 16 x i1> %v) {326; CHECK-LABEL: vreduce_or_nxv16i1:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma329; CHECK-NEXT: vcpop.m a0, v0330; CHECK-NEXT: snez a0, a0331; CHECK-NEXT: ret332 %red = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %v)333 ret i1 %red334}335 336define zeroext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {337; CHECK-LABEL: vreduce_xor_nxv16i1:338; CHECK: # %bb.0:339; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma340; CHECK-NEXT: vcpop.m a0, v0341; CHECK-NEXT: andi a0, a0, 1342; CHECK-NEXT: ret343 %red = call i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1> %v)344 ret i1 %red345}346 347define zeroext i1 @vreduce_and_nxv16i1(<vscale x 16 x i1> %v) {348; CHECK-LABEL: vreduce_and_nxv16i1:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma351; CHECK-NEXT: vmnot.m v8, v0352; CHECK-NEXT: vcpop.m a0, v8353; CHECK-NEXT: seqz a0, a0354; CHECK-NEXT: ret355 %red = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %v)356 ret i1 %red357}358 359define zeroext i1 @vreduce_umax_nxv16i1(<vscale x 16 x i1> %v) {360; CHECK-LABEL: vreduce_umax_nxv16i1:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma363; CHECK-NEXT: vcpop.m a0, v0364; CHECK-NEXT: snez a0, a0365; CHECK-NEXT: ret366 %red = call i1 @llvm.vector.reduce.umax.nxv16i1(<vscale x 16 x i1> %v)367 ret i1 %red368}369 370define zeroext i1 @vreduce_smax_nxv16i1(<vscale x 16 x i1> %v) {371; CHECK-LABEL: vreduce_smax_nxv16i1:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma374; CHECK-NEXT: vmnot.m v8, v0375; CHECK-NEXT: vcpop.m a0, v8376; CHECK-NEXT: seqz a0, a0377; CHECK-NEXT: ret378 %red = call i1 @llvm.vector.reduce.smax.nxv16i1(<vscale x 16 x i1> %v)379 ret i1 %red380}381 382define zeroext i1 @vreduce_umin_nxv16i1(<vscale x 16 x i1> %v) {383; CHECK-LABEL: vreduce_umin_nxv16i1:384; CHECK: # %bb.0:385; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma386; CHECK-NEXT: vmnot.m v8, v0387; CHECK-NEXT: vcpop.m a0, v8388; CHECK-NEXT: seqz a0, a0389; CHECK-NEXT: ret390 %red = call i1 @llvm.vector.reduce.umin.nxv16i1(<vscale x 16 x i1> %v)391 ret i1 %red392}393 394define zeroext i1 @vreduce_smin_nxv16i1(<vscale x 16 x i1> %v) {395; CHECK-LABEL: vreduce_smin_nxv16i1:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma398; CHECK-NEXT: vcpop.m a0, v0399; CHECK-NEXT: snez a0, a0400; CHECK-NEXT: ret401 %red = call i1 @llvm.vector.reduce.smin.nxv16i1(<vscale x 16 x i1> %v)402 ret i1 %red403}404 405define zeroext i1 @vreduce_or_nxv32i1(<vscale x 32 x i1> %v) {406; CHECK-LABEL: vreduce_or_nxv32i1:407; CHECK: # %bb.0:408; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma409; CHECK-NEXT: vcpop.m a0, v0410; CHECK-NEXT: snez a0, a0411; CHECK-NEXT: ret412 %red = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %v)413 ret i1 %red414}415 416define zeroext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {417; CHECK-LABEL: vreduce_xor_nxv32i1:418; CHECK: # %bb.0:419; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma420; CHECK-NEXT: vcpop.m a0, v0421; CHECK-NEXT: andi a0, a0, 1422; CHECK-NEXT: ret423 %red = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %v)424 ret i1 %red425}426 427define zeroext i1 @vreduce_and_nxv32i1(<vscale x 32 x i1> %v) {428; CHECK-LABEL: vreduce_and_nxv32i1:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma431; CHECK-NEXT: vmnot.m v8, v0432; CHECK-NEXT: vcpop.m a0, v8433; CHECK-NEXT: seqz a0, a0434; CHECK-NEXT: ret435 %red = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %v)436 ret i1 %red437}438 439define zeroext i1 @vreduce_umax_nxv32i1(<vscale x 32 x i1> %v) {440; CHECK-LABEL: vreduce_umax_nxv32i1:441; CHECK: # %bb.0:442; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma443; CHECK-NEXT: vcpop.m a0, v0444; CHECK-NEXT: snez a0, a0445; CHECK-NEXT: ret446 %red = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %v)447 ret i1 %red448}449 450define zeroext i1 @vreduce_smax_nxv32i1(<vscale x 32 x i1> %v) {451; CHECK-LABEL: vreduce_smax_nxv32i1:452; CHECK: # %bb.0:453; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma454; CHECK-NEXT: vmnot.m v8, v0455; CHECK-NEXT: vcpop.m a0, v8456; CHECK-NEXT: seqz a0, a0457; CHECK-NEXT: ret458 %red = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %v)459 ret i1 %red460}461 462define zeroext i1 @vreduce_umin_nxv32i1(<vscale x 32 x i1> %v) {463; CHECK-LABEL: vreduce_umin_nxv32i1:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma466; CHECK-NEXT: vmnot.m v8, v0467; CHECK-NEXT: vcpop.m a0, v8468; CHECK-NEXT: seqz a0, a0469; CHECK-NEXT: ret470 %red = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %v)471 ret i1 %red472}473 474define zeroext i1 @vreduce_smin_nxv32i1(<vscale x 32 x i1> %v) {475; CHECK-LABEL: vreduce_smin_nxv32i1:476; CHECK: # %bb.0:477; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma478; CHECK-NEXT: vcpop.m a0, v0479; CHECK-NEXT: snez a0, a0480; CHECK-NEXT: ret481 %red = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %v)482 ret i1 %red483}484 485define zeroext i1 @vreduce_or_nxv64i1(<vscale x 64 x i1> %v) {486; CHECK-LABEL: vreduce_or_nxv64i1:487; CHECK: # %bb.0:488; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma489; CHECK-NEXT: vcpop.m a0, v0490; CHECK-NEXT: snez a0, a0491; CHECK-NEXT: ret492 %red = call i1 @llvm.vector.reduce.or.nxv64i1(<vscale x 64 x i1> %v)493 ret i1 %red494}495 496define zeroext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {497; CHECK-LABEL: vreduce_xor_nxv64i1:498; CHECK: # %bb.0:499; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma500; CHECK-NEXT: vcpop.m a0, v0501; CHECK-NEXT: andi a0, a0, 1502; CHECK-NEXT: ret503 %red = call i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1> %v)504 ret i1 %red505}506 507define zeroext i1 @vreduce_and_nxv64i1(<vscale x 64 x i1> %v) {508; CHECK-LABEL: vreduce_and_nxv64i1:509; CHECK: # %bb.0:510; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma511; CHECK-NEXT: vmnot.m v8, v0512; CHECK-NEXT: vcpop.m a0, v8513; CHECK-NEXT: seqz a0, a0514; CHECK-NEXT: ret515 %red = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %v)516 ret i1 %red517}518 519define zeroext i1 @vreduce_umax_nxv64i1(<vscale x 64 x i1> %v) {520; CHECK-LABEL: vreduce_umax_nxv64i1:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma523; CHECK-NEXT: vcpop.m a0, v0524; CHECK-NEXT: snez a0, a0525; CHECK-NEXT: ret526 %red = call i1 @llvm.vector.reduce.umax.nxv64i1(<vscale x 64 x i1> %v)527 ret i1 %red528}529 530define zeroext i1 @vreduce_smax_nxv64i1(<vscale x 64 x i1> %v) {531; CHECK-LABEL: vreduce_smax_nxv64i1:532; CHECK: # %bb.0:533; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma534; CHECK-NEXT: vmnot.m v8, v0535; CHECK-NEXT: vcpop.m a0, v8536; CHECK-NEXT: seqz a0, a0537; CHECK-NEXT: ret538 %red = call i1 @llvm.vector.reduce.smax.nxv64i1(<vscale x 64 x i1> %v)539 ret i1 %red540}541 542define zeroext i1 @vreduce_umin_nxv64i1(<vscale x 64 x i1> %v) {543; CHECK-LABEL: vreduce_umin_nxv64i1:544; CHECK: # %bb.0:545; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma546; CHECK-NEXT: vmnot.m v8, v0547; CHECK-NEXT: vcpop.m a0, v8548; CHECK-NEXT: seqz a0, a0549; CHECK-NEXT: ret550 %red = call i1 @llvm.vector.reduce.umin.nxv64i1(<vscale x 64 x i1> %v)551 ret i1 %red552}553 554define zeroext i1 @vreduce_smin_nxv64i1(<vscale x 64 x i1> %v) {555; CHECK-LABEL: vreduce_smin_nxv64i1:556; CHECK: # %bb.0:557; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma558; CHECK-NEXT: vcpop.m a0, v0559; CHECK-NEXT: snez a0, a0560; CHECK-NEXT: ret561 %red = call i1 @llvm.vector.reduce.smin.nxv64i1(<vscale x 64 x i1> %v)562 ret i1 %red563}564 565define zeroext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {566; CHECK-LABEL: vreduce_add_nxv1i1:567; CHECK: # %bb.0:568; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma569; CHECK-NEXT: vcpop.m a0, v0570; CHECK-NEXT: andi a0, a0, 1571; CHECK-NEXT: ret572 %red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)573 ret i1 %red574}575 576define zeroext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {577; CHECK-LABEL: vreduce_add_nxv2i1:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma580; CHECK-NEXT: vcpop.m a0, v0581; CHECK-NEXT: andi a0, a0, 1582; CHECK-NEXT: ret583 %red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)584 ret i1 %red585}586 587define zeroext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {588; CHECK-LABEL: vreduce_add_nxv4i1:589; CHECK: # %bb.0:590; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma591; CHECK-NEXT: vcpop.m a0, v0592; CHECK-NEXT: andi a0, a0, 1593; CHECK-NEXT: ret594 %red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)595 ret i1 %red596}597 598define zeroext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {599; CHECK-LABEL: vreduce_add_nxv8i1:600; CHECK: # %bb.0:601; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma602; CHECK-NEXT: vcpop.m a0, v0603; CHECK-NEXT: andi a0, a0, 1604; CHECK-NEXT: ret605 %red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)606 ret i1 %red607}608 609define zeroext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {610; CHECK-LABEL: vreduce_add_nxv16i1:611; CHECK: # %bb.0:612; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma613; CHECK-NEXT: vcpop.m a0, v0614; CHECK-NEXT: andi a0, a0, 1615; CHECK-NEXT: ret616 %red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)617 ret i1 %red618}619 620define zeroext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {621; CHECK-LABEL: vreduce_add_nxv32i1:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma624; CHECK-NEXT: vcpop.m a0, v0625; CHECK-NEXT: andi a0, a0, 1626; CHECK-NEXT: ret627 %red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)628 ret i1 %red629}630 631define zeroext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {632; CHECK-LABEL: vreduce_add_nxv64i1:633; CHECK: # %bb.0:634; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma635; CHECK-NEXT: vcpop.m a0, v0636; CHECK-NEXT: andi a0, a0, 1637; CHECK-NEXT: ret638 %red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)639 ret i1 %red640}641 642define zeroext i1 @vreduce_or_nxv128i1(<vscale x 128 x i1> %v) {643; CHECK-LABEL: vreduce_or_nxv128i1:644; CHECK: # %bb.0:645; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma646; CHECK-NEXT: vmor.mm v8, v0, v8647; CHECK-NEXT: vcpop.m a0, v8648; CHECK-NEXT: snez a0, a0649; CHECK-NEXT: ret650 %red = call i1 @llvm.vector.reduce.or.nxv128i1(<vscale x 128 x i1> %v)651 ret i1 %red652}653 654define zeroext i1 @vreduce_xor_nxv128i1(<vscale x 128 x i1> %v) {655; CHECK-LABEL: vreduce_xor_nxv128i1:656; CHECK: # %bb.0:657; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma658; CHECK-NEXT: vmxor.mm v8, v0, v8659; CHECK-NEXT: vcpop.m a0, v8660; CHECK-NEXT: andi a0, a0, 1661; CHECK-NEXT: ret662 %red = call i1 @llvm.vector.reduce.xor.nxv128i1(<vscale x 128 x i1> %v)663 ret i1 %red664}665 666define zeroext i1 @vreduce_and_nxv128i1(<vscale x 128 x i1> %v) {667; CHECK-LABEL: vreduce_and_nxv128i1:668; CHECK: # %bb.0:669; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma670; CHECK-NEXT: vmnand.mm v8, v0, v8671; CHECK-NEXT: vcpop.m a0, v8672; CHECK-NEXT: seqz a0, a0673; CHECK-NEXT: ret674 %red = call i1 @llvm.vector.reduce.and.nxv128i1(<vscale x 128 x i1> %v)675 ret i1 %red676}677 678define zeroext i1 @vreduce_umax_nxv128i1(<vscale x 128 x i1> %v) {679; CHECK-LABEL: vreduce_umax_nxv128i1:680; CHECK: # %bb.0:681; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma682; CHECK-NEXT: vmor.mm v8, v0, v8683; CHECK-NEXT: vcpop.m a0, v8684; CHECK-NEXT: snez a0, a0685; CHECK-NEXT: ret686 %red = call i1 @llvm.vector.reduce.umax.nxv128i1(<vscale x 128 x i1> %v)687 ret i1 %red688}689 690define zeroext i1 @vreduce_smax_nxv128i1(<vscale x 128 x i1> %v) {691; CHECK-LABEL: vreduce_smax_nxv128i1:692; CHECK: # %bb.0:693; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma694; CHECK-NEXT: vmnand.mm v8, v0, v8695; CHECK-NEXT: vcpop.m a0, v8696; CHECK-NEXT: seqz a0, a0697; CHECK-NEXT: ret698 %red = call i1 @llvm.vector.reduce.smax.nxv128i1(<vscale x 128 x i1> %v)699 ret i1 %red700}701 702define zeroext i1 @vreduce_umin_nxv128i1(<vscale x 128 x i1> %v) {703; CHECK-LABEL: vreduce_umin_nxv128i1:704; CHECK: # %bb.0:705; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma706; CHECK-NEXT: vmnand.mm v8, v0, v8707; CHECK-NEXT: vcpop.m a0, v8708; CHECK-NEXT: seqz a0, a0709; CHECK-NEXT: ret710 %red = call i1 @llvm.vector.reduce.umin.nxv128i1(<vscale x 128 x i1> %v)711 ret i1 %red712}713 714define zeroext i1 @vreduce_smin_nxv128i1(<vscale x 128 x i1> %v) {715; CHECK-LABEL: vreduce_smin_nxv128i1:716; CHECK: # %bb.0:717; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma718; CHECK-NEXT: vmor.mm v8, v0, v8719; CHECK-NEXT: vcpop.m a0, v8720; CHECK-NEXT: snez a0, a0721; CHECK-NEXT: ret722 %red = call i1 @llvm.vector.reduce.smin.nxv128i1(<vscale x 128 x i1> %v)723 ret i1 %red724}725 726define zeroext i1 @vreduce_or_nxv256i1(<vscale x 256 x i1> %v) {727; CHECK-LABEL: vreduce_or_nxv256i1:728; CHECK: # %bb.0:729; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma730; CHECK-NEXT: vmor.mm v8, v8, v10731; CHECK-NEXT: vmor.mm v9, v0, v9732; CHECK-NEXT: vmor.mm v8, v9, v8733; CHECK-NEXT: vcpop.m a0, v8734; CHECK-NEXT: snez a0, a0735; CHECK-NEXT: ret736 %red = call i1 @llvm.vector.reduce.or.nxv256i1(<vscale x 256 x i1> %v)737 ret i1 %red738}739 740define zeroext i1 @vreduce_xor_nxv256i1(<vscale x 256 x i1> %v) {741; CHECK-LABEL: vreduce_xor_nxv256i1:742; CHECK: # %bb.0:743; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma744; CHECK-NEXT: vmxor.mm v8, v8, v10745; CHECK-NEXT: vmxor.mm v9, v0, v9746; CHECK-NEXT: vmxor.mm v8, v9, v8747; CHECK-NEXT: vcpop.m a0, v8748; CHECK-NEXT: andi a0, a0, 1749; CHECK-NEXT: ret750 %red = call i1 @llvm.vector.reduce.xor.nxv256i1(<vscale x 256 x i1> %v)751 ret i1 %red752}753 754define zeroext i1 @vreduce_and_nxv256i1(<vscale x 256 x i1> %v) {755; CHECK-LABEL: vreduce_and_nxv256i1:756; CHECK: # %bb.0:757; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma758; CHECK-NEXT: vmand.mm v8, v8, v10759; CHECK-NEXT: vmand.mm v9, v0, v9760; CHECK-NEXT: vmnand.mm v8, v9, v8761; CHECK-NEXT: vcpop.m a0, v8762; CHECK-NEXT: seqz a0, a0763; CHECK-NEXT: ret764 %red = call i1 @llvm.vector.reduce.and.nxv256i1(<vscale x 256 x i1> %v)765 ret i1 %red766}767 768define zeroext i1 @vreduce_umax_nxv256i1(<vscale x 256 x i1> %v) {769; CHECK-LABEL: vreduce_umax_nxv256i1:770; CHECK: # %bb.0:771; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma772; CHECK-NEXT: vmor.mm v8, v8, v10773; CHECK-NEXT: vmor.mm v9, v0, v9774; CHECK-NEXT: vmor.mm v8, v9, v8775; CHECK-NEXT: vcpop.m a0, v8776; CHECK-NEXT: snez a0, a0777; CHECK-NEXT: ret778 %red = call i1 @llvm.vector.reduce.umax.nxv256i1(<vscale x 256 x i1> %v)779 ret i1 %red780}781 782define zeroext i1 @vreduce_smax_nxv256i1(<vscale x 256 x i1> %v) {783; CHECK-LABEL: vreduce_smax_nxv256i1:784; CHECK: # %bb.0:785; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma786; CHECK-NEXT: vmand.mm v8, v8, v10787; CHECK-NEXT: vmand.mm v9, v0, v9788; CHECK-NEXT: vmnand.mm v8, v9, v8789; CHECK-NEXT: vcpop.m a0, v8790; CHECK-NEXT: seqz a0, a0791; CHECK-NEXT: ret792 %red = call i1 @llvm.vector.reduce.smax.nxv256i1(<vscale x 256 x i1> %v)793 ret i1 %red794}795 796define zeroext i1 @vreduce_umin_nxv256i1(<vscale x 256 x i1> %v) {797; CHECK-LABEL: vreduce_umin_nxv256i1:798; CHECK: # %bb.0:799; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma800; CHECK-NEXT: vmand.mm v8, v8, v10801; CHECK-NEXT: vmand.mm v9, v0, v9802; CHECK-NEXT: vmnand.mm v8, v9, v8803; CHECK-NEXT: vcpop.m a0, v8804; CHECK-NEXT: seqz a0, a0805; CHECK-NEXT: ret806 %red = call i1 @llvm.vector.reduce.umin.nxv256i1(<vscale x 256 x i1> %v)807 ret i1 %red808}809 810define zeroext i1 @vreduce_smin_nxv256i1(<vscale x 256 x i1> %v) {811; CHECK-LABEL: vreduce_smin_nxv256i1:812; CHECK: # %bb.0:813; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma814; CHECK-NEXT: vmor.mm v8, v8, v10815; CHECK-NEXT: vmor.mm v9, v0, v9816; CHECK-NEXT: vmor.mm v8, v9, v8817; CHECK-NEXT: vcpop.m a0, v8818; CHECK-NEXT: snez a0, a0819; CHECK-NEXT: ret820 %red = call i1 @llvm.vector.reduce.smin.nxv256i1(<vscale x 256 x i1> %v)821 ret i1 %red822}823 824define zeroext i1 @vreduce_or_nxv512i1(<vscale x 512 x i1> %v) {825; CHECK-LABEL: vreduce_or_nxv512i1:826; CHECK: # %bb.0:827; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma828; CHECK-NEXT: vmor.mm v10, v10, v14829; CHECK-NEXT: vmor.mm v8, v8, v12830; CHECK-NEXT: vmor.mm v9, v9, v13831; CHECK-NEXT: vmor.mm v11, v0, v11832; CHECK-NEXT: vmor.mm v8, v8, v10833; CHECK-NEXT: vmor.mm v9, v11, v9834; CHECK-NEXT: vmor.mm v8, v9, v8835; CHECK-NEXT: vcpop.m a0, v8836; CHECK-NEXT: snez a0, a0837; CHECK-NEXT: ret838 %red = call i1 @llvm.vector.reduce.or.nxv512i1(<vscale x 512 x i1> %v)839 ret i1 %red840}841 842define zeroext i1 @vreduce_xor_nxv512i1(<vscale x 512 x i1> %v) {843; CHECK-LABEL: vreduce_xor_nxv512i1:844; CHECK: # %bb.0:845; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma846; CHECK-NEXT: vmxor.mm v10, v10, v14847; CHECK-NEXT: vmxor.mm v8, v8, v12848; CHECK-NEXT: vmxor.mm v9, v9, v13849; CHECK-NEXT: vmxor.mm v11, v0, v11850; CHECK-NEXT: vmxor.mm v8, v8, v10851; CHECK-NEXT: vmxor.mm v9, v11, v9852; CHECK-NEXT: vmxor.mm v8, v9, v8853; CHECK-NEXT: vcpop.m a0, v8854; CHECK-NEXT: andi a0, a0, 1855; CHECK-NEXT: ret856 %red = call i1 @llvm.vector.reduce.xor.nxv512i1(<vscale x 512 x i1> %v)857 ret i1 %red858}859 860define zeroext i1 @vreduce_and_nxv512i1(<vscale x 512 x i1> %v) {861; CHECK-LABEL: vreduce_and_nxv512i1:862; CHECK: # %bb.0:863; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma864; CHECK-NEXT: vmand.mm v10, v10, v14865; CHECK-NEXT: vmand.mm v8, v8, v12866; CHECK-NEXT: vmand.mm v9, v9, v13867; CHECK-NEXT: vmand.mm v11, v0, v11868; CHECK-NEXT: vmand.mm v8, v8, v10869; CHECK-NEXT: vmand.mm v9, v11, v9870; CHECK-NEXT: vmnand.mm v8, v9, v8871; CHECK-NEXT: vcpop.m a0, v8872; CHECK-NEXT: seqz a0, a0873; CHECK-NEXT: ret874 %red = call i1 @llvm.vector.reduce.and.nxv512i1(<vscale x 512 x i1> %v)875 ret i1 %red876}877 878define zeroext i1 @vreduce_umax_nxv512i1(<vscale x 512 x i1> %v) {879; CHECK-LABEL: vreduce_umax_nxv512i1:880; CHECK: # %bb.0:881; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma882; CHECK-NEXT: vmor.mm v10, v10, v14883; CHECK-NEXT: vmor.mm v8, v8, v12884; CHECK-NEXT: vmor.mm v9, v9, v13885; CHECK-NEXT: vmor.mm v11, v0, v11886; CHECK-NEXT: vmor.mm v8, v8, v10887; CHECK-NEXT: vmor.mm v9, v11, v9888; CHECK-NEXT: vmor.mm v8, v9, v8889; CHECK-NEXT: vcpop.m a0, v8890; CHECK-NEXT: snez a0, a0891; CHECK-NEXT: ret892 %red = call i1 @llvm.vector.reduce.umax.nxv512i1(<vscale x 512 x i1> %v)893 ret i1 %red894}895 896define zeroext i1 @vreduce_smax_nxv512i1(<vscale x 512 x i1> %v) {897; CHECK-LABEL: vreduce_smax_nxv512i1:898; CHECK: # %bb.0:899; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma900; CHECK-NEXT: vmand.mm v10, v10, v14901; CHECK-NEXT: vmand.mm v8, v8, v12902; CHECK-NEXT: vmand.mm v9, v9, v13903; CHECK-NEXT: vmand.mm v11, v0, v11904; CHECK-NEXT: vmand.mm v8, v8, v10905; CHECK-NEXT: vmand.mm v9, v11, v9906; CHECK-NEXT: vmnand.mm v8, v9, v8907; CHECK-NEXT: vcpop.m a0, v8908; CHECK-NEXT: seqz a0, a0909; CHECK-NEXT: ret910 %red = call i1 @llvm.vector.reduce.smax.nxv512i1(<vscale x 512 x i1> %v)911 ret i1 %red912}913 914define zeroext i1 @vreduce_umin_nxv512i1(<vscale x 512 x i1> %v) {915; CHECK-LABEL: vreduce_umin_nxv512i1:916; CHECK: # %bb.0:917; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma918; CHECK-NEXT: vmand.mm v10, v10, v14919; CHECK-NEXT: vmand.mm v8, v8, v12920; CHECK-NEXT: vmand.mm v9, v9, v13921; CHECK-NEXT: vmand.mm v11, v0, v11922; CHECK-NEXT: vmand.mm v8, v8, v10923; CHECK-NEXT: vmand.mm v9, v11, v9924; CHECK-NEXT: vmnand.mm v8, v9, v8925; CHECK-NEXT: vcpop.m a0, v8926; CHECK-NEXT: seqz a0, a0927; CHECK-NEXT: ret928 %red = call i1 @llvm.vector.reduce.umin.nxv512i1(<vscale x 512 x i1> %v)929 ret i1 %red930}931 932define zeroext i1 @vreduce_smin_nxv512i1(<vscale x 512 x i1> %v) {933; CHECK-LABEL: vreduce_smin_nxv512i1:934; CHECK: # %bb.0:935; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma936; CHECK-NEXT: vmor.mm v10, v10, v14937; CHECK-NEXT: vmor.mm v8, v8, v12938; CHECK-NEXT: vmor.mm v9, v9, v13939; CHECK-NEXT: vmor.mm v11, v0, v11940; CHECK-NEXT: vmor.mm v8, v8, v10941; CHECK-NEXT: vmor.mm v9, v11, v9942; CHECK-NEXT: vmor.mm v8, v9, v8943; CHECK-NEXT: vcpop.m a0, v8944; CHECK-NEXT: snez a0, a0945; CHECK-NEXT: ret946 %red = call i1 @llvm.vector.reduce.smin.nxv512i1(<vscale x 512 x i1> %v)947 ret i1 %red948}949 950define zeroext i1 @vreduce_or_nxv1024i1(<vscale x 1024 x i1> %v) {951; CHECK-LABEL: vreduce_or_nxv1024i1:952; CHECK: # %bb.0:953; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma954; CHECK-NEXT: vmor.mm v14, v14, v22955; CHECK-NEXT: vmor.mm v10, v10, v18956; CHECK-NEXT: vmor.mm v12, v12, v20957; CHECK-NEXT: vmor.mm v8, v8, v16958; CHECK-NEXT: vmor.mm v13, v13, v21959; CHECK-NEXT: vmor.mm v9, v9, v17960; CHECK-NEXT: vmor.mm v11, v11, v19961; CHECK-NEXT: vmor.mm v15, v0, v15962; CHECK-NEXT: vmor.mm v10, v10, v14963; CHECK-NEXT: vmor.mm v8, v8, v12964; CHECK-NEXT: vmor.mm v9, v9, v13965; CHECK-NEXT: vmor.mm v11, v15, v11966; CHECK-NEXT: vmor.mm v8, v8, v10967; CHECK-NEXT: vmor.mm v9, v11, v9968; CHECK-NEXT: vmor.mm v8, v9, v8969; CHECK-NEXT: vcpop.m a0, v8970; CHECK-NEXT: snez a0, a0971; CHECK-NEXT: ret972 %red = call i1 @llvm.vector.reduce.or.nxv1024i1(<vscale x 1024 x i1> %v)973 ret i1 %red974}975 976define zeroext i1 @vreduce_xor_nxv1024i1(<vscale x 1024 x i1> %v) {977; CHECK-LABEL: vreduce_xor_nxv1024i1:978; CHECK: # %bb.0:979; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma980; CHECK-NEXT: vmxor.mm v14, v14, v22981; CHECK-NEXT: vmxor.mm v10, v10, v18982; CHECK-NEXT: vmxor.mm v12, v12, v20983; CHECK-NEXT: vmxor.mm v8, v8, v16984; CHECK-NEXT: vmxor.mm v13, v13, v21985; CHECK-NEXT: vmxor.mm v9, v9, v17986; CHECK-NEXT: vmxor.mm v11, v11, v19987; CHECK-NEXT: vmxor.mm v15, v0, v15988; CHECK-NEXT: vmxor.mm v10, v10, v14989; CHECK-NEXT: vmxor.mm v8, v8, v12990; CHECK-NEXT: vmxor.mm v9, v9, v13991; CHECK-NEXT: vmxor.mm v11, v15, v11992; CHECK-NEXT: vmxor.mm v8, v8, v10993; CHECK-NEXT: vmxor.mm v9, v11, v9994; CHECK-NEXT: vmxor.mm v8, v9, v8995; CHECK-NEXT: vcpop.m a0, v8996; CHECK-NEXT: andi a0, a0, 1997; CHECK-NEXT: ret998 %red = call i1 @llvm.vector.reduce.xor.nxv1024i1(<vscale x 1024 x i1> %v)999 ret i1 %red1000}1001 1002define zeroext i1 @vreduce_and_nxv1024i1(<vscale x 1024 x i1> %v) {1003; CHECK-LABEL: vreduce_and_nxv1024i1:1004; CHECK: # %bb.0:1005; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma1006; CHECK-NEXT: vmand.mm v14, v14, v221007; CHECK-NEXT: vmand.mm v10, v10, v181008; CHECK-NEXT: vmand.mm v12, v12, v201009; CHECK-NEXT: vmand.mm v8, v8, v161010; CHECK-NEXT: vmand.mm v13, v13, v211011; CHECK-NEXT: vmand.mm v9, v9, v171012; CHECK-NEXT: vmand.mm v11, v11, v191013; CHECK-NEXT: vmand.mm v15, v0, v151014; CHECK-NEXT: vmand.mm v10, v10, v141015; CHECK-NEXT: vmand.mm v8, v8, v121016; CHECK-NEXT: vmand.mm v9, v9, v131017; CHECK-NEXT: vmand.mm v11, v15, v111018; CHECK-NEXT: vmand.mm v8, v8, v101019; CHECK-NEXT: vmand.mm v9, v11, v91020; CHECK-NEXT: vmnand.mm v8, v9, v81021; CHECK-NEXT: vcpop.m a0, v81022; CHECK-NEXT: seqz a0, a01023; CHECK-NEXT: ret1024 %red = call i1 @llvm.vector.reduce.and.nxv1024i1(<vscale x 1024 x i1> %v)1025 ret i1 %red1026}1027 1028define zeroext i1 @vreduce_umax_nxv1024i1(<vscale x 1024 x i1> %v) {1029; CHECK-LABEL: vreduce_umax_nxv1024i1:1030; CHECK: # %bb.0:1031; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma1032; CHECK-NEXT: vmor.mm v14, v14, v221033; CHECK-NEXT: vmor.mm v10, v10, v181034; CHECK-NEXT: vmor.mm v12, v12, v201035; CHECK-NEXT: vmor.mm v8, v8, v161036; CHECK-NEXT: vmor.mm v13, v13, v211037; CHECK-NEXT: vmor.mm v9, v9, v171038; CHECK-NEXT: vmor.mm v11, v11, v191039; CHECK-NEXT: vmor.mm v15, v0, v151040; CHECK-NEXT: vmor.mm v10, v10, v141041; CHECK-NEXT: vmor.mm v8, v8, v121042; CHECK-NEXT: vmor.mm v9, v9, v131043; CHECK-NEXT: vmor.mm v11, v15, v111044; CHECK-NEXT: vmor.mm v8, v8, v101045; CHECK-NEXT: vmor.mm v9, v11, v91046; CHECK-NEXT: vmor.mm v8, v9, v81047; CHECK-NEXT: vcpop.m a0, v81048; CHECK-NEXT: snez a0, a01049; CHECK-NEXT: ret1050 %red = call i1 @llvm.vector.reduce.umax.nxv1024i1(<vscale x 1024 x i1> %v)1051 ret i1 %red1052}1053 1054define zeroext i1 @vreduce_smax_nxv1024i1(<vscale x 1024 x i1> %v) {1055; CHECK-LABEL: vreduce_smax_nxv1024i1:1056; CHECK: # %bb.0:1057; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma1058; CHECK-NEXT: vmand.mm v14, v14, v221059; CHECK-NEXT: vmand.mm v10, v10, v181060; CHECK-NEXT: vmand.mm v12, v12, v201061; CHECK-NEXT: vmand.mm v8, v8, v161062; CHECK-NEXT: vmand.mm v13, v13, v211063; CHECK-NEXT: vmand.mm v9, v9, v171064; CHECK-NEXT: vmand.mm v11, v11, v191065; CHECK-NEXT: vmand.mm v15, v0, v151066; CHECK-NEXT: vmand.mm v10, v10, v141067; CHECK-NEXT: vmand.mm v8, v8, v121068; CHECK-NEXT: vmand.mm v9, v9, v131069; CHECK-NEXT: vmand.mm v11, v15, v111070; CHECK-NEXT: vmand.mm v8, v8, v101071; CHECK-NEXT: vmand.mm v9, v11, v91072; CHECK-NEXT: vmnand.mm v8, v9, v81073; CHECK-NEXT: vcpop.m a0, v81074; CHECK-NEXT: seqz a0, a01075; CHECK-NEXT: ret1076 %red = call i1 @llvm.vector.reduce.smax.nxv1024i1(<vscale x 1024 x i1> %v)1077 ret i1 %red1078}1079 1080define zeroext i1 @vreduce_umin_nxv1024i1(<vscale x 1024 x i1> %v) {1081; CHECK-LABEL: vreduce_umin_nxv1024i1:1082; CHECK: # %bb.0:1083; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma1084; CHECK-NEXT: vmand.mm v14, v14, v221085; CHECK-NEXT: vmand.mm v10, v10, v181086; CHECK-NEXT: vmand.mm v12, v12, v201087; CHECK-NEXT: vmand.mm v8, v8, v161088; CHECK-NEXT: vmand.mm v13, v13, v211089; CHECK-NEXT: vmand.mm v9, v9, v171090; CHECK-NEXT: vmand.mm v11, v11, v191091; CHECK-NEXT: vmand.mm v15, v0, v151092; CHECK-NEXT: vmand.mm v10, v10, v141093; CHECK-NEXT: vmand.mm v8, v8, v121094; CHECK-NEXT: vmand.mm v9, v9, v131095; CHECK-NEXT: vmand.mm v11, v15, v111096; CHECK-NEXT: vmand.mm v8, v8, v101097; CHECK-NEXT: vmand.mm v9, v11, v91098; CHECK-NEXT: vmnand.mm v8, v9, v81099; CHECK-NEXT: vcpop.m a0, v81100; CHECK-NEXT: seqz a0, a01101; CHECK-NEXT: ret1102 %red = call i1 @llvm.vector.reduce.umin.nxv1024i1(<vscale x 1024 x i1> %v)1103 ret i1 %red1104}1105 1106define zeroext i1 @vreduce_smin_nxv1024i1(<vscale x 1024 x i1> %v) {1107; CHECK-LABEL: vreduce_smin_nxv1024i1:1108; CHECK: # %bb.0:1109; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma1110; CHECK-NEXT: vmor.mm v14, v14, v221111; CHECK-NEXT: vmor.mm v10, v10, v181112; CHECK-NEXT: vmor.mm v12, v12, v201113; CHECK-NEXT: vmor.mm v8, v8, v161114; CHECK-NEXT: vmor.mm v13, v13, v211115; CHECK-NEXT: vmor.mm v9, v9, v171116; CHECK-NEXT: vmor.mm v11, v11, v191117; CHECK-NEXT: vmor.mm v15, v0, v151118; CHECK-NEXT: vmor.mm v10, v10, v141119; CHECK-NEXT: vmor.mm v8, v8, v121120; CHECK-NEXT: vmor.mm v9, v9, v131121; CHECK-NEXT: vmor.mm v11, v15, v111122; CHECK-NEXT: vmor.mm v8, v8, v101123; CHECK-NEXT: vmor.mm v9, v11, v91124; CHECK-NEXT: vmor.mm v8, v9, v81125; CHECK-NEXT: vcpop.m a0, v81126; CHECK-NEXT: snez a0, a01127; CHECK-NEXT: ret1128 %red = call i1 @llvm.vector.reduce.smin.nxv1024i1(<vscale x 1024 x i1> %v)1129 ret i1 %red1130}1131