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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X6 7define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {8; CHECK-LABEL: vrem_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vrem.vv v8, v8, v912; CHECK-NEXT: ret13 %vc = srem <vscale x 1 x i8> %va, %vb14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vrem_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {18; CHECK-LABEL: vrem_vx_nxv1i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vrem.vx v8, v8, a022; CHECK-NEXT: ret23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %vc = srem <vscale x 1 x i8> %va, %splat26 ret <vscale x 1 x i8> %vc27}28 29define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {30; CHECK-LABEL: vrem_vi_nxv1i8_0:31; CHECK: # %bb.0:32; CHECK-NEXT: li a0, 10933; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vmulh.vx v9, v8, a035; CHECK-NEXT: vsub.vv v9, v9, v836; CHECK-NEXT: vsra.vi v9, v9, 237; CHECK-NEXT: vsrl.vi v10, v9, 738; CHECK-NEXT: vadd.vv v9, v9, v1039; CHECK-NEXT: li a0, -740; CHECK-NEXT: vnmsac.vx v8, a0, v941; CHECK-NEXT: ret42 %vc = srem <vscale x 1 x i8> %va, splat (i8 -7)43 ret <vscale x 1 x i8> %vc44}45 46define <vscale x 1 x i8> @vrem_vv_nxv1i8_sext_twice(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {47; CHECK-LABEL: vrem_vv_nxv1i8_sext_twice:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma50; CHECK-NEXT: vrem.vv v8, v8, v951; CHECK-NEXT: ret52 %sext_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>53 %sext_vb = sext <vscale x 1 x i8> %vb to <vscale x 1 x i16>54 %vc_ext = srem <vscale x 1 x i16> %sext_va, %sext_vb55 %vc = trunc <vscale x 1 x i16> %vc_ext to <vscale x 1 x i8>56 ret <vscale x 1 x i8> %vc57}58 59define <vscale x 2 x i8> @vrem_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {60; CHECK-LABEL: vrem_vv_nxv2i8:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma63; CHECK-NEXT: vrem.vv v8, v8, v964; CHECK-NEXT: ret65 %vc = srem <vscale x 2 x i8> %va, %vb66 ret <vscale x 2 x i8> %vc67}68 69define <vscale x 2 x i8> @vrem_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {70; CHECK-LABEL: vrem_vx_nxv2i8:71; CHECK: # %bb.0:72; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma73; CHECK-NEXT: vrem.vx v8, v8, a074; CHECK-NEXT: ret75 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 076 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer77 %vc = srem <vscale x 2 x i8> %va, %splat78 ret <vscale x 2 x i8> %vc79}80 81define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {82; CHECK-LABEL: vrem_vi_nxv2i8_0:83; CHECK: # %bb.0:84; CHECK-NEXT: li a0, 10985; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma86; CHECK-NEXT: vmulh.vx v9, v8, a087; CHECK-NEXT: vsub.vv v9, v9, v888; CHECK-NEXT: vsra.vi v9, v9, 289; CHECK-NEXT: vsrl.vi v10, v9, 790; CHECK-NEXT: vadd.vv v9, v9, v1091; CHECK-NEXT: li a0, -792; CHECK-NEXT: vnmsac.vx v8, a0, v993; CHECK-NEXT: ret94 %vc = srem <vscale x 2 x i8> %va, splat (i8 -7)95 ret <vscale x 2 x i8> %vc96}97 98define <vscale x 2 x i8> @vrem_vv_nxv2i8_sext_twice(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {99; CHECK-LABEL: vrem_vv_nxv2i8_sext_twice:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma102; CHECK-NEXT: vrem.vv v8, v8, v9103; CHECK-NEXT: ret104 %sext_va = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>105 %sext_vb = sext <vscale x 2 x i8> %vb to <vscale x 2 x i16>106 %vc_ext = srem <vscale x 2 x i16> %sext_va, %sext_vb107 %vc = trunc <vscale x 2 x i16> %vc_ext to <vscale x 2 x i8>108 ret <vscale x 2 x i8> %vc109}110 111define <vscale x 4 x i8> @vrem_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {112; CHECK-LABEL: vrem_vv_nxv4i8:113; CHECK: # %bb.0:114; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma115; CHECK-NEXT: vrem.vv v8, v8, v9116; CHECK-NEXT: ret117 %vc = srem <vscale x 4 x i8> %va, %vb118 ret <vscale x 4 x i8> %vc119}120 121define <vscale x 4 x i8> @vrem_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {122; CHECK-LABEL: vrem_vx_nxv4i8:123; CHECK: # %bb.0:124; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma125; CHECK-NEXT: vrem.vx v8, v8, a0126; CHECK-NEXT: ret127 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0128 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer129 %vc = srem <vscale x 4 x i8> %va, %splat130 ret <vscale x 4 x i8> %vc131}132 133define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {134; CHECK-LABEL: vrem_vi_nxv4i8_0:135; CHECK: # %bb.0:136; CHECK-NEXT: li a0, 109137; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma138; CHECK-NEXT: vmulh.vx v9, v8, a0139; CHECK-NEXT: vsub.vv v9, v9, v8140; CHECK-NEXT: vsra.vi v9, v9, 2141; CHECK-NEXT: vsrl.vi v10, v9, 7142; CHECK-NEXT: vadd.vv v9, v9, v10143; CHECK-NEXT: li a0, -7144; CHECK-NEXT: vnmsac.vx v8, a0, v9145; CHECK-NEXT: ret146 %vc = srem <vscale x 4 x i8> %va, splat (i8 -7)147 ret <vscale x 4 x i8> %vc148}149 150define <vscale x 4 x i8> @vrem_vv_nxv4i8_sext_twice(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {151; CHECK-LABEL: vrem_vv_nxv4i8_sext_twice:152; CHECK: # %bb.0:153; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma154; CHECK-NEXT: vrem.vv v8, v8, v9155; CHECK-NEXT: ret156 %sext_va = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>157 %sext_vb = sext <vscale x 4 x i8> %vb to <vscale x 4 x i16>158 %vc_ext = srem <vscale x 4 x i16> %sext_va, %sext_vb159 %vc = trunc <vscale x 4 x i16> %vc_ext to <vscale x 4 x i8>160 ret <vscale x 4 x i8> %vc161}162 163define <vscale x 8 x i8> @vrem_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {164; CHECK-LABEL: vrem_vv_nxv8i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma167; CHECK-NEXT: vrem.vv v8, v8, v9168; CHECK-NEXT: ret169 %vc = srem <vscale x 8 x i8> %va, %vb170 ret <vscale x 8 x i8> %vc171}172 173define <vscale x 8 x i8> @vrem_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {174; CHECK-LABEL: vrem_vx_nxv8i8:175; CHECK: # %bb.0:176; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma177; CHECK-NEXT: vrem.vx v8, v8, a0178; CHECK-NEXT: ret179 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0180 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer181 %vc = srem <vscale x 8 x i8> %va, %splat182 ret <vscale x 8 x i8> %vc183}184 185define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {186; CHECK-LABEL: vrem_vi_nxv8i8_0:187; CHECK: # %bb.0:188; CHECK-NEXT: li a0, 109189; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma190; CHECK-NEXT: vmulh.vx v9, v8, a0191; CHECK-NEXT: vsub.vv v9, v9, v8192; CHECK-NEXT: vsra.vi v9, v9, 2193; CHECK-NEXT: vsrl.vi v10, v9, 7194; CHECK-NEXT: vadd.vv v9, v9, v10195; CHECK-NEXT: li a0, -7196; CHECK-NEXT: vnmsac.vx v8, a0, v9197; CHECK-NEXT: ret198 %vc = srem <vscale x 8 x i8> %va, splat (i8 -7)199 ret <vscale x 8 x i8> %vc200}201 202define <vscale x 8 x i8> @vrem_vv_nxv8i8_sext_twice(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {203; CHECK-LABEL: vrem_vv_nxv8i8_sext_twice:204; CHECK: # %bb.0:205; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma206; CHECK-NEXT: vrem.vv v8, v8, v9207; CHECK-NEXT: ret208 %sext_va = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>209 %sext_vb = sext <vscale x 8 x i8> %vb to <vscale x 8 x i16>210 %vc_ext = srem <vscale x 8 x i16> %sext_va, %sext_vb211 %vc = trunc <vscale x 8 x i16> %vc_ext to <vscale x 8 x i8>212 ret <vscale x 8 x i8> %vc213}214 215define <vscale x 16 x i8> @vrem_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {216; CHECK-LABEL: vrem_vv_nxv16i8:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma219; CHECK-NEXT: vrem.vv v8, v8, v10220; CHECK-NEXT: ret221 %vc = srem <vscale x 16 x i8> %va, %vb222 ret <vscale x 16 x i8> %vc223}224 225define <vscale x 16 x i8> @vrem_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {226; CHECK-LABEL: vrem_vx_nxv16i8:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma229; CHECK-NEXT: vrem.vx v8, v8, a0230; CHECK-NEXT: ret231 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0232 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer233 %vc = srem <vscale x 16 x i8> %va, %splat234 ret <vscale x 16 x i8> %vc235}236 237define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {238; CHECK-LABEL: vrem_vi_nxv16i8_0:239; CHECK: # %bb.0:240; CHECK-NEXT: li a0, 109241; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma242; CHECK-NEXT: vmulh.vx v10, v8, a0243; CHECK-NEXT: vsub.vv v10, v10, v8244; CHECK-NEXT: vsra.vi v10, v10, 2245; CHECK-NEXT: vsrl.vi v12, v10, 7246; CHECK-NEXT: vadd.vv v10, v10, v12247; CHECK-NEXT: li a0, -7248; CHECK-NEXT: vnmsac.vx v8, a0, v10249; CHECK-NEXT: ret250 %vc = srem <vscale x 16 x i8> %va, splat (i8 -7)251 ret <vscale x 16 x i8> %vc252}253 254define <vscale x 16 x i8> @vrem_vv_nxv16i8_sext_twice(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {255; CHECK-LABEL: vrem_vv_nxv16i8_sext_twice:256; CHECK: # %bb.0:257; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma258; CHECK-NEXT: vrem.vv v8, v8, v10259; CHECK-NEXT: ret260 %sext_va = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>261 %sext_vb = sext <vscale x 16 x i8> %vb to <vscale x 16 x i16>262 %vc_ext = srem <vscale x 16 x i16> %sext_va, %sext_vb263 %vc = trunc <vscale x 16 x i16> %vc_ext to <vscale x 16 x i8>264 ret <vscale x 16 x i8> %vc265}266 267define <vscale x 32 x i8> @vrem_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {268; CHECK-LABEL: vrem_vv_nxv32i8:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma271; CHECK-NEXT: vrem.vv v8, v8, v12272; CHECK-NEXT: ret273 %vc = srem <vscale x 32 x i8> %va, %vb274 ret <vscale x 32 x i8> %vc275}276 277define <vscale x 32 x i8> @vrem_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {278; CHECK-LABEL: vrem_vx_nxv32i8:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma281; CHECK-NEXT: vrem.vx v8, v8, a0282; CHECK-NEXT: ret283 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0284 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer285 %vc = srem <vscale x 32 x i8> %va, %splat286 ret <vscale x 32 x i8> %vc287}288 289define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {290; CHECK-LABEL: vrem_vi_nxv32i8_0:291; CHECK: # %bb.0:292; CHECK-NEXT: li a0, 109293; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma294; CHECK-NEXT: vmulh.vx v12, v8, a0295; CHECK-NEXT: vsub.vv v12, v12, v8296; CHECK-NEXT: vsra.vi v12, v12, 2297; CHECK-NEXT: vsrl.vi v16, v12, 7298; CHECK-NEXT: vadd.vv v12, v12, v16299; CHECK-NEXT: li a0, -7300; CHECK-NEXT: vnmsac.vx v8, a0, v12301; CHECK-NEXT: ret302 %vc = srem <vscale x 32 x i8> %va, splat (i8 -7)303 ret <vscale x 32 x i8> %vc304}305 306define <vscale x 32 x i8> @vrem_vv_nxv32i8_sext_twice(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {307; CHECK-LABEL: vrem_vv_nxv32i8_sext_twice:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma310; CHECK-NEXT: vrem.vv v8, v8, v12311; CHECK-NEXT: ret312 %sext_va = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>313 %sext_vb = sext <vscale x 32 x i8> %vb to <vscale x 32 x i16>314 %vc_ext = srem <vscale x 32 x i16> %sext_va, %sext_vb315 %vc = trunc <vscale x 32 x i16> %vc_ext to <vscale x 32 x i8>316 ret <vscale x 32 x i8> %vc317}318 319define <vscale x 64 x i8> @vrem_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {320; CHECK-LABEL: vrem_vv_nxv64i8:321; CHECK: # %bb.0:322; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma323; CHECK-NEXT: vrem.vv v8, v8, v16324; CHECK-NEXT: ret325 %vc = srem <vscale x 64 x i8> %va, %vb326 ret <vscale x 64 x i8> %vc327}328 329define <vscale x 64 x i8> @vrem_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {330; CHECK-LABEL: vrem_vx_nxv64i8:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma333; CHECK-NEXT: vrem.vx v8, v8, a0334; CHECK-NEXT: ret335 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0336 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer337 %vc = srem <vscale x 64 x i8> %va, %splat338 ret <vscale x 64 x i8> %vc339}340 341define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {342; CHECK-LABEL: vrem_vi_nxv64i8_0:343; CHECK: # %bb.0:344; CHECK-NEXT: li a0, 109345; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma346; CHECK-NEXT: vmulh.vx v16, v8, a0347; CHECK-NEXT: vsub.vv v16, v16, v8348; CHECK-NEXT: vsra.vi v16, v16, 2349; CHECK-NEXT: vsrl.vi v24, v16, 7350; CHECK-NEXT: vadd.vv v16, v16, v24351; CHECK-NEXT: li a0, -7352; CHECK-NEXT: vnmsac.vx v8, a0, v16353; CHECK-NEXT: ret354 %vc = srem <vscale x 64 x i8> %va, splat (i8 -7)355 ret <vscale x 64 x i8> %vc356}357 358define <vscale x 1 x i16> @vrem_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {359; CHECK-LABEL: vrem_vv_nxv1i16:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma362; CHECK-NEXT: vrem.vv v8, v8, v9363; CHECK-NEXT: ret364 %vc = srem <vscale x 1 x i16> %va, %vb365 ret <vscale x 1 x i16> %vc366}367 368define <vscale x 1 x i16> @vrem_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {369; CHECK-LABEL: vrem_vx_nxv1i16:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma372; CHECK-NEXT: vrem.vx v8, v8, a0373; CHECK-NEXT: ret374 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0375 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer376 %vc = srem <vscale x 1 x i16> %va, %splat377 ret <vscale x 1 x i16> %vc378}379 380define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {381; CHECK-LABEL: vrem_vi_nxv1i16_0:382; CHECK: # %bb.0:383; CHECK-NEXT: lui a0, 1048571384; CHECK-NEXT: addi a0, a0, 1755385; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma386; CHECK-NEXT: vmulh.vx v9, v8, a0387; CHECK-NEXT: vsra.vi v9, v9, 1388; CHECK-NEXT: vsrl.vi v10, v9, 15389; CHECK-NEXT: vadd.vv v9, v9, v10390; CHECK-NEXT: li a0, -7391; CHECK-NEXT: vnmsac.vx v8, a0, v9392; CHECK-NEXT: ret393 %vc = srem <vscale x 1 x i16> %va, splat (i16 -7)394 ret <vscale x 1 x i16> %vc395}396 397define <vscale x 1 x i16> @vrem_vv_nxv1i16_sext_twice(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {398; CHECK-LABEL: vrem_vv_nxv1i16_sext_twice:399; CHECK: # %bb.0:400; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma401; CHECK-NEXT: vrem.vv v8, v8, v9402; CHECK-NEXT: ret403 %sext_va = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>404 %sext_vb = sext <vscale x 1 x i16> %vb to <vscale x 1 x i32>405 %vc_ext = srem <vscale x 1 x i32> %sext_va, %sext_vb406 %vc = trunc <vscale x 1 x i32> %vc_ext to <vscale x 1 x i16>407 ret <vscale x 1 x i16> %vc408}409 410define <vscale x 2 x i16> @vrem_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {411; CHECK-LABEL: vrem_vv_nxv2i16:412; CHECK: # %bb.0:413; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma414; CHECK-NEXT: vrem.vv v8, v8, v9415; CHECK-NEXT: ret416 %vc = srem <vscale x 2 x i16> %va, %vb417 ret <vscale x 2 x i16> %vc418}419 420define <vscale x 2 x i16> @vrem_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {421; CHECK-LABEL: vrem_vx_nxv2i16:422; CHECK: # %bb.0:423; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma424; CHECK-NEXT: vrem.vx v8, v8, a0425; CHECK-NEXT: ret426 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0427 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer428 %vc = srem <vscale x 2 x i16> %va, %splat429 ret <vscale x 2 x i16> %vc430}431 432define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {433; CHECK-LABEL: vrem_vi_nxv2i16_0:434; CHECK: # %bb.0:435; CHECK-NEXT: lui a0, 1048571436; CHECK-NEXT: addi a0, a0, 1755437; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma438; CHECK-NEXT: vmulh.vx v9, v8, a0439; CHECK-NEXT: vsra.vi v9, v9, 1440; CHECK-NEXT: vsrl.vi v10, v9, 15441; CHECK-NEXT: vadd.vv v9, v9, v10442; CHECK-NEXT: li a0, -7443; CHECK-NEXT: vnmsac.vx v8, a0, v9444; CHECK-NEXT: ret445 %vc = srem <vscale x 2 x i16> %va, splat (i16 -7)446 ret <vscale x 2 x i16> %vc447}448 449define <vscale x 2 x i16> @vrem_vv_nxv2i16_sext_twice(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {450; CHECK-LABEL: vrem_vv_nxv2i16_sext_twice:451; CHECK: # %bb.0:452; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma453; CHECK-NEXT: vrem.vv v8, v8, v9454; CHECK-NEXT: ret455 %sext_va = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>456 %sext_vb = sext <vscale x 2 x i16> %vb to <vscale x 2 x i32>457 %vc_ext = srem <vscale x 2 x i32> %sext_va, %sext_vb458 %vc = trunc <vscale x 2 x i32> %vc_ext to <vscale x 2 x i16>459 ret <vscale x 2 x i16> %vc460}461 462define <vscale x 4 x i16> @vrem_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {463; CHECK-LABEL: vrem_vv_nxv4i16:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma466; CHECK-NEXT: vrem.vv v8, v8, v9467; CHECK-NEXT: ret468 %vc = srem <vscale x 4 x i16> %va, %vb469 ret <vscale x 4 x i16> %vc470}471 472define <vscale x 4 x i16> @vrem_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {473; CHECK-LABEL: vrem_vx_nxv4i16:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma476; CHECK-NEXT: vrem.vx v8, v8, a0477; CHECK-NEXT: ret478 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0479 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer480 %vc = srem <vscale x 4 x i16> %va, %splat481 ret <vscale x 4 x i16> %vc482}483 484define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {485; CHECK-LABEL: vrem_vi_nxv4i16_0:486; CHECK: # %bb.0:487; CHECK-NEXT: lui a0, 1048571488; CHECK-NEXT: addi a0, a0, 1755489; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma490; CHECK-NEXT: vmulh.vx v9, v8, a0491; CHECK-NEXT: vsra.vi v9, v9, 1492; CHECK-NEXT: vsrl.vi v10, v9, 15493; CHECK-NEXT: vadd.vv v9, v9, v10494; CHECK-NEXT: li a0, -7495; CHECK-NEXT: vnmsac.vx v8, a0, v9496; CHECK-NEXT: ret497 %vc = srem <vscale x 4 x i16> %va, splat (i16 -7)498 ret <vscale x 4 x i16> %vc499}500 501define <vscale x 4 x i16> @vrem_vv_nxv4i16_sext_twice(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {502; CHECK-LABEL: vrem_vv_nxv4i16_sext_twice:503; CHECK: # %bb.0:504; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma505; CHECK-NEXT: vrem.vv v8, v8, v9506; CHECK-NEXT: ret507 %sext_va = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>508 %sext_vb = sext <vscale x 4 x i16> %vb to <vscale x 4 x i32>509 %vc_ext = srem <vscale x 4 x i32> %sext_va, %sext_vb510 %vc = trunc <vscale x 4 x i32> %vc_ext to <vscale x 4 x i16>511 ret <vscale x 4 x i16> %vc512}513 514define <vscale x 8 x i16> @vrem_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {515; CHECK-LABEL: vrem_vv_nxv8i16:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma518; CHECK-NEXT: vrem.vv v8, v8, v10519; CHECK-NEXT: ret520 %vc = srem <vscale x 8 x i16> %va, %vb521 ret <vscale x 8 x i16> %vc522}523 524define <vscale x 8 x i16> @vrem_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {525; CHECK-LABEL: vrem_vx_nxv8i16:526; CHECK: # %bb.0:527; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma528; CHECK-NEXT: vrem.vx v8, v8, a0529; CHECK-NEXT: ret530 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0531 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer532 %vc = srem <vscale x 8 x i16> %va, %splat533 ret <vscale x 8 x i16> %vc534}535 536define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {537; CHECK-LABEL: vrem_vi_nxv8i16_0:538; CHECK: # %bb.0:539; CHECK-NEXT: lui a0, 1048571540; CHECK-NEXT: addi a0, a0, 1755541; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma542; CHECK-NEXT: vmulh.vx v10, v8, a0543; CHECK-NEXT: vsra.vi v10, v10, 1544; CHECK-NEXT: vsrl.vi v12, v10, 15545; CHECK-NEXT: vadd.vv v10, v10, v12546; CHECK-NEXT: li a0, -7547; CHECK-NEXT: vnmsac.vx v8, a0, v10548; CHECK-NEXT: ret549 %vc = srem <vscale x 8 x i16> %va, splat (i16 -7)550 ret <vscale x 8 x i16> %vc551}552 553define <vscale x 8 x i16> @vrem_vv_nxv8i16_sext_twice(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {554; CHECK-LABEL: vrem_vv_nxv8i16_sext_twice:555; CHECK: # %bb.0:556; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma557; CHECK-NEXT: vrem.vv v8, v8, v10558; CHECK-NEXT: ret559 %sext_va = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>560 %sext_vb = sext <vscale x 8 x i16> %vb to <vscale x 8 x i32>561 %vc_ext = srem <vscale x 8 x i32> %sext_va, %sext_vb562 %vc = trunc <vscale x 8 x i32> %vc_ext to <vscale x 8 x i16>563 ret <vscale x 8 x i16> %vc564}565 566define <vscale x 16 x i16> @vrem_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {567; CHECK-LABEL: vrem_vv_nxv16i16:568; CHECK: # %bb.0:569; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma570; CHECK-NEXT: vrem.vv v8, v8, v12571; CHECK-NEXT: ret572 %vc = srem <vscale x 16 x i16> %va, %vb573 ret <vscale x 16 x i16> %vc574}575 576define <vscale x 16 x i16> @vrem_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {577; CHECK-LABEL: vrem_vx_nxv16i16:578; CHECK: # %bb.0:579; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma580; CHECK-NEXT: vrem.vx v8, v8, a0581; CHECK-NEXT: ret582 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0583 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer584 %vc = srem <vscale x 16 x i16> %va, %splat585 ret <vscale x 16 x i16> %vc586}587 588define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {589; CHECK-LABEL: vrem_vi_nxv16i16_0:590; CHECK: # %bb.0:591; CHECK-NEXT: lui a0, 1048571592; CHECK-NEXT: addi a0, a0, 1755593; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma594; CHECK-NEXT: vmulh.vx v12, v8, a0595; CHECK-NEXT: vsra.vi v12, v12, 1596; CHECK-NEXT: vsrl.vi v16, v12, 15597; CHECK-NEXT: vadd.vv v12, v12, v16598; CHECK-NEXT: li a0, -7599; CHECK-NEXT: vnmsac.vx v8, a0, v12600; CHECK-NEXT: ret601 %vc = srem <vscale x 16 x i16> %va, splat (i16 -7)602 ret <vscale x 16 x i16> %vc603}604 605define <vscale x 16 x i16> @vrem_vv_nxv16i16_sext_twice(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {606; CHECK-LABEL: vrem_vv_nxv16i16_sext_twice:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma609; CHECK-NEXT: vrem.vv v8, v8, v12610; CHECK-NEXT: ret611 %sext_va = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>612 %sext_vb = sext <vscale x 16 x i16> %vb to <vscale x 16 x i32>613 %vc_ext = srem <vscale x 16 x i32> %sext_va, %sext_vb614 %vc = trunc <vscale x 16 x i32> %vc_ext to <vscale x 16 x i16>615 ret <vscale x 16 x i16> %vc616}617 618define <vscale x 32 x i16> @vrem_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {619; CHECK-LABEL: vrem_vv_nxv32i16:620; CHECK: # %bb.0:621; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma622; CHECK-NEXT: vrem.vv v8, v8, v16623; CHECK-NEXT: ret624 %vc = srem <vscale x 32 x i16> %va, %vb625 ret <vscale x 32 x i16> %vc626}627 628define <vscale x 32 x i16> @vrem_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {629; CHECK-LABEL: vrem_vx_nxv32i16:630; CHECK: # %bb.0:631; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma632; CHECK-NEXT: vrem.vx v8, v8, a0633; CHECK-NEXT: ret634 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0635 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer636 %vc = srem <vscale x 32 x i16> %va, %splat637 ret <vscale x 32 x i16> %vc638}639 640define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {641; CHECK-LABEL: vrem_vi_nxv32i16_0:642; CHECK: # %bb.0:643; CHECK-NEXT: lui a0, 1048571644; CHECK-NEXT: addi a0, a0, 1755645; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma646; CHECK-NEXT: vmulh.vx v16, v8, a0647; CHECK-NEXT: vsra.vi v16, v16, 1648; CHECK-NEXT: vsrl.vi v24, v16, 15649; CHECK-NEXT: vadd.vv v16, v16, v24650; CHECK-NEXT: li a0, -7651; CHECK-NEXT: vnmsac.vx v8, a0, v16652; CHECK-NEXT: ret653 %vc = srem <vscale x 32 x i16> %va, splat (i16 -7)654 ret <vscale x 32 x i16> %vc655}656 657define <vscale x 1 x i32> @vrem_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {658; CHECK-LABEL: vrem_vv_nxv1i32:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma661; CHECK-NEXT: vrem.vv v8, v8, v9662; CHECK-NEXT: ret663 %vc = srem <vscale x 1 x i32> %va, %vb664 ret <vscale x 1 x i32> %vc665}666 667define <vscale x 1 x i32> @vrem_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {668; CHECK-LABEL: vrem_vx_nxv1i32:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma671; CHECK-NEXT: vrem.vx v8, v8, a0672; CHECK-NEXT: ret673 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0674 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer675 %vc = srem <vscale x 1 x i32> %va, %splat676 ret <vscale x 1 x i32> %vc677}678 679define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {680; RV32-LABEL: vrem_vi_nxv1i32_0:681; RV32: # %bb.0:682; RV32-NEXT: lui a0, 449390683; RV32-NEXT: addi a0, a0, -1171684; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma685; RV32-NEXT: vmulh.vx v9, v8, a0686; RV32-NEXT: vsub.vv v9, v9, v8687; RV32-NEXT: vsrl.vi v10, v9, 31688; RV32-NEXT: vsra.vi v9, v9, 2689; RV32-NEXT: vadd.vv v9, v9, v10690; RV32-NEXT: li a0, -7691; RV32-NEXT: vnmsac.vx v8, a0, v9692; RV32-NEXT: ret693;694; RV64-LABEL: vrem_vi_nxv1i32_0:695; RV64: # %bb.0:696; RV64-NEXT: lui a0, 449390697; RV64-NEXT: addi a0, a0, -1171698; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma699; RV64-NEXT: vmulh.vx v9, v8, a0700; RV64-NEXT: vsub.vv v9, v9, v8701; RV64-NEXT: vsra.vi v9, v9, 2702; RV64-NEXT: vsrl.vi v10, v9, 31703; RV64-NEXT: vadd.vv v9, v9, v10704; RV64-NEXT: li a0, -7705; RV64-NEXT: vnmsac.vx v8, a0, v9706; RV64-NEXT: ret707 %vc = srem <vscale x 1 x i32> %va, splat (i32 -7)708 ret <vscale x 1 x i32> %vc709}710 711define <vscale x 2 x i32> @vrem_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {712; CHECK-LABEL: vrem_vv_nxv2i32:713; CHECK: # %bb.0:714; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma715; CHECK-NEXT: vrem.vv v8, v8, v9716; CHECK-NEXT: ret717 %vc = srem <vscale x 2 x i32> %va, %vb718 ret <vscale x 2 x i32> %vc719}720 721define <vscale x 2 x i32> @vrem_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {722; CHECK-LABEL: vrem_vx_nxv2i32:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma725; CHECK-NEXT: vrem.vx v8, v8, a0726; CHECK-NEXT: ret727 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0728 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer729 %vc = srem <vscale x 2 x i32> %va, %splat730 ret <vscale x 2 x i32> %vc731}732 733define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {734; RV32-LABEL: vrem_vi_nxv2i32_0:735; RV32: # %bb.0:736; RV32-NEXT: lui a0, 449390737; RV32-NEXT: addi a0, a0, -1171738; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma739; RV32-NEXT: vmulh.vx v9, v8, a0740; RV32-NEXT: vsub.vv v9, v9, v8741; RV32-NEXT: vsrl.vi v10, v9, 31742; RV32-NEXT: vsra.vi v9, v9, 2743; RV32-NEXT: vadd.vv v9, v9, v10744; RV32-NEXT: li a0, -7745; RV32-NEXT: vnmsac.vx v8, a0, v9746; RV32-NEXT: ret747;748; RV64-LABEL: vrem_vi_nxv2i32_0:749; RV64: # %bb.0:750; RV64-NEXT: lui a0, 449390751; RV64-NEXT: addi a0, a0, -1171752; RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma753; RV64-NEXT: vmulh.vx v9, v8, a0754; RV64-NEXT: vsub.vv v9, v9, v8755; RV64-NEXT: vsra.vi v9, v9, 2756; RV64-NEXT: vsrl.vi v10, v9, 31757; RV64-NEXT: vadd.vv v9, v9, v10758; RV64-NEXT: li a0, -7759; RV64-NEXT: vnmsac.vx v8, a0, v9760; RV64-NEXT: ret761 %vc = srem <vscale x 2 x i32> %va, splat (i32 -7)762 ret <vscale x 2 x i32> %vc763}764 765define <vscale x 4 x i32> @vrem_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {766; CHECK-LABEL: vrem_vv_nxv4i32:767; CHECK: # %bb.0:768; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma769; CHECK-NEXT: vrem.vv v8, v8, v10770; CHECK-NEXT: ret771 %vc = srem <vscale x 4 x i32> %va, %vb772 ret <vscale x 4 x i32> %vc773}774 775define <vscale x 4 x i32> @vrem_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {776; CHECK-LABEL: vrem_vx_nxv4i32:777; CHECK: # %bb.0:778; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma779; CHECK-NEXT: vrem.vx v8, v8, a0780; CHECK-NEXT: ret781 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0782 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer783 %vc = srem <vscale x 4 x i32> %va, %splat784 ret <vscale x 4 x i32> %vc785}786 787define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {788; RV32-LABEL: vrem_vi_nxv4i32_0:789; RV32: # %bb.0:790; RV32-NEXT: lui a0, 449390791; RV32-NEXT: addi a0, a0, -1171792; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma793; RV32-NEXT: vmulh.vx v10, v8, a0794; RV32-NEXT: vsub.vv v10, v10, v8795; RV32-NEXT: vsrl.vi v12, v10, 31796; RV32-NEXT: vsra.vi v10, v10, 2797; RV32-NEXT: vadd.vv v10, v10, v12798; RV32-NEXT: li a0, -7799; RV32-NEXT: vnmsac.vx v8, a0, v10800; RV32-NEXT: ret801;802; RV64-LABEL: vrem_vi_nxv4i32_0:803; RV64: # %bb.0:804; RV64-NEXT: lui a0, 449390805; RV64-NEXT: addi a0, a0, -1171806; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma807; RV64-NEXT: vmulh.vx v10, v8, a0808; RV64-NEXT: vsub.vv v10, v10, v8809; RV64-NEXT: vsra.vi v10, v10, 2810; RV64-NEXT: vsrl.vi v12, v10, 31811; RV64-NEXT: vadd.vv v10, v10, v12812; RV64-NEXT: li a0, -7813; RV64-NEXT: vnmsac.vx v8, a0, v10814; RV64-NEXT: ret815 %vc = srem <vscale x 4 x i32> %va, splat (i32 -7)816 ret <vscale x 4 x i32> %vc817}818 819define <vscale x 8 x i32> @vrem_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {820; CHECK-LABEL: vrem_vv_nxv8i32:821; CHECK: # %bb.0:822; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma823; CHECK-NEXT: vrem.vv v8, v8, v12824; CHECK-NEXT: ret825 %vc = srem <vscale x 8 x i32> %va, %vb826 ret <vscale x 8 x i32> %vc827}828 829define <vscale x 8 x i32> @vrem_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {830; CHECK-LABEL: vrem_vx_nxv8i32:831; CHECK: # %bb.0:832; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma833; CHECK-NEXT: vrem.vx v8, v8, a0834; CHECK-NEXT: ret835 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0836 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer837 %vc = srem <vscale x 8 x i32> %va, %splat838 ret <vscale x 8 x i32> %vc839}840 841define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {842; RV32-LABEL: vrem_vi_nxv8i32_0:843; RV32: # %bb.0:844; RV32-NEXT: lui a0, 449390845; RV32-NEXT: addi a0, a0, -1171846; RV32-NEXT: vsetvli a1, zero, e32, m4, ta, ma847; RV32-NEXT: vmulh.vx v12, v8, a0848; RV32-NEXT: vsub.vv v12, v12, v8849; RV32-NEXT: vsrl.vi v16, v12, 31850; RV32-NEXT: vsra.vi v12, v12, 2851; RV32-NEXT: vadd.vv v12, v12, v16852; RV32-NEXT: li a0, -7853; RV32-NEXT: vnmsac.vx v8, a0, v12854; RV32-NEXT: ret855;856; RV64-LABEL: vrem_vi_nxv8i32_0:857; RV64: # %bb.0:858; RV64-NEXT: lui a0, 449390859; RV64-NEXT: addi a0, a0, -1171860; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma861; RV64-NEXT: vmulh.vx v12, v8, a0862; RV64-NEXT: vsub.vv v12, v12, v8863; RV64-NEXT: vsra.vi v12, v12, 2864; RV64-NEXT: vsrl.vi v16, v12, 31865; RV64-NEXT: vadd.vv v12, v12, v16866; RV64-NEXT: li a0, -7867; RV64-NEXT: vnmsac.vx v8, a0, v12868; RV64-NEXT: ret869 %vc = srem <vscale x 8 x i32> %va, splat (i32 -7)870 ret <vscale x 8 x i32> %vc871}872 873define <vscale x 16 x i32> @vrem_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {874; CHECK-LABEL: vrem_vv_nxv16i32:875; CHECK: # %bb.0:876; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma877; CHECK-NEXT: vrem.vv v8, v8, v16878; CHECK-NEXT: ret879 %vc = srem <vscale x 16 x i32> %va, %vb880 ret <vscale x 16 x i32> %vc881}882 883define <vscale x 16 x i32> @vrem_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {884; CHECK-LABEL: vrem_vx_nxv16i32:885; CHECK: # %bb.0:886; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma887; CHECK-NEXT: vrem.vx v8, v8, a0888; CHECK-NEXT: ret889 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0890 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer891 %vc = srem <vscale x 16 x i32> %va, %splat892 ret <vscale x 16 x i32> %vc893}894 895define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {896; RV32-LABEL: vrem_vi_nxv16i32_0:897; RV32: # %bb.0:898; RV32-NEXT: lui a0, 449390899; RV32-NEXT: addi a0, a0, -1171900; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma901; RV32-NEXT: vmulh.vx v16, v8, a0902; RV32-NEXT: vsub.vv v16, v16, v8903; RV32-NEXT: vsrl.vi v24, v16, 31904; RV32-NEXT: vsra.vi v16, v16, 2905; RV32-NEXT: vadd.vv v16, v16, v24906; RV32-NEXT: li a0, -7907; RV32-NEXT: vnmsac.vx v8, a0, v16908; RV32-NEXT: ret909;910; RV64-LABEL: vrem_vi_nxv16i32_0:911; RV64: # %bb.0:912; RV64-NEXT: lui a0, 449390913; RV64-NEXT: addi a0, a0, -1171914; RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma915; RV64-NEXT: vmulh.vx v16, v8, a0916; RV64-NEXT: vsub.vv v16, v16, v8917; RV64-NEXT: vsra.vi v16, v16, 2918; RV64-NEXT: vsrl.vi v24, v16, 31919; RV64-NEXT: vadd.vv v16, v16, v24920; RV64-NEXT: li a0, -7921; RV64-NEXT: vnmsac.vx v8, a0, v16922; RV64-NEXT: ret923 %vc = srem <vscale x 16 x i32> %va, splat (i32 -7)924 ret <vscale x 16 x i32> %vc925}926 927define <vscale x 1 x i64> @vrem_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {928; CHECK-LABEL: vrem_vv_nxv1i64:929; CHECK: # %bb.0:930; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma931; CHECK-NEXT: vrem.vv v8, v8, v9932; CHECK-NEXT: ret933 %vc = srem <vscale x 1 x i64> %va, %vb934 ret <vscale x 1 x i64> %vc935}936 937define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {938; RV32-LABEL: vrem_vx_nxv1i64:939; RV32: # %bb.0:940; RV32-NEXT: addi sp, sp, -16941; RV32-NEXT: .cfi_def_cfa_offset 16942; RV32-NEXT: sw a0, 8(sp)943; RV32-NEXT: sw a1, 12(sp)944; RV32-NEXT: addi a0, sp, 8945; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma946; RV32-NEXT: vlse64.v v9, (a0), zero947; RV32-NEXT: vrem.vv v8, v8, v9948; RV32-NEXT: addi sp, sp, 16949; RV32-NEXT: .cfi_def_cfa_offset 0950; RV32-NEXT: ret951;952; RV64-LABEL: vrem_vx_nxv1i64:953; RV64: # %bb.0:954; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma955; RV64-NEXT: vrem.vx v8, v8, a0956; RV64-NEXT: ret957 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0958 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer959 %vc = srem <vscale x 1 x i64> %va, %splat960 ret <vscale x 1 x i64> %vc961}962 963define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {964; RV32-V-LABEL: vrem_vi_nxv1i64_0:965; RV32-V: # %bb.0:966; RV32-V-NEXT: addi sp, sp, -16967; RV32-V-NEXT: .cfi_def_cfa_offset 16968; RV32-V-NEXT: lui a0, 748983969; RV32-V-NEXT: lui a1, 898779970; RV32-V-NEXT: addi a0, a0, -586971; RV32-V-NEXT: addi a1, a1, 1755972; RV32-V-NEXT: sw a1, 8(sp)973; RV32-V-NEXT: sw a0, 12(sp)974; RV32-V-NEXT: addi a0, sp, 8975; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma976; RV32-V-NEXT: vlse64.v v9, (a0), zero977; RV32-V-NEXT: li a0, 63978; RV32-V-NEXT: vmulh.vv v9, v8, v9979; RV32-V-NEXT: vsrl.vx v10, v9, a0980; RV32-V-NEXT: vsra.vi v9, v9, 1981; RV32-V-NEXT: vadd.vv v9, v9, v10982; RV32-V-NEXT: li a0, -7983; RV32-V-NEXT: vnmsac.vx v8, a0, v9984; RV32-V-NEXT: addi sp, sp, 16985; RV32-V-NEXT: .cfi_def_cfa_offset 0986; RV32-V-NEXT: ret987;988; ZVE64X-LABEL: vrem_vi_nxv1i64_0:989; ZVE64X: # %bb.0:990; ZVE64X-NEXT: li a0, -7991; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, ma992; ZVE64X-NEXT: vrem.vx v8, v8, a0993; ZVE64X-NEXT: ret994;995; RV64-V-LABEL: vrem_vi_nxv1i64_0:996; RV64-V: # %bb.0:997; RV64-V-NEXT: lui a0, %hi(.LCPI67_0)998; RV64-V-NEXT: ld a0, %lo(.LCPI67_0)(a0)999; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma1000; RV64-V-NEXT: vmulh.vx v9, v8, a01001; RV64-V-NEXT: li a0, 631002; RV64-V-NEXT: vsrl.vx v10, v9, a01003; RV64-V-NEXT: vsra.vi v9, v9, 11004; RV64-V-NEXT: vadd.vv v9, v9, v101005; RV64-V-NEXT: li a0, -71006; RV64-V-NEXT: vnmsac.vx v8, a0, v91007; RV64-V-NEXT: ret1008 %vc = srem <vscale x 1 x i64> %va, splat (i64 -7)1009 ret <vscale x 1 x i64> %vc1010}1011 1012define <vscale x 2 x i64> @vrem_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {1013; CHECK-LABEL: vrem_vv_nxv2i64:1014; CHECK: # %bb.0:1015; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma1016; CHECK-NEXT: vrem.vv v8, v8, v101017; CHECK-NEXT: ret1018 %vc = srem <vscale x 2 x i64> %va, %vb1019 ret <vscale x 2 x i64> %vc1020}1021 1022define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {1023; RV32-LABEL: vrem_vx_nxv2i64:1024; RV32: # %bb.0:1025; RV32-NEXT: addi sp, sp, -161026; RV32-NEXT: .cfi_def_cfa_offset 161027; RV32-NEXT: sw a0, 8(sp)1028; RV32-NEXT: sw a1, 12(sp)1029; RV32-NEXT: addi a0, sp, 81030; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1031; RV32-NEXT: vlse64.v v10, (a0), zero1032; RV32-NEXT: vrem.vv v8, v8, v101033; RV32-NEXT: addi sp, sp, 161034; RV32-NEXT: .cfi_def_cfa_offset 01035; RV32-NEXT: ret1036;1037; RV64-LABEL: vrem_vx_nxv2i64:1038; RV64: # %bb.0:1039; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma1040; RV64-NEXT: vrem.vx v8, v8, a01041; RV64-NEXT: ret1042 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01043 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1044 %vc = srem <vscale x 2 x i64> %va, %splat1045 ret <vscale x 2 x i64> %vc1046}1047 1048define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {1049; RV32-V-LABEL: vrem_vi_nxv2i64_0:1050; RV32-V: # %bb.0:1051; RV32-V-NEXT: addi sp, sp, -161052; RV32-V-NEXT: .cfi_def_cfa_offset 161053; RV32-V-NEXT: lui a0, 7489831054; RV32-V-NEXT: lui a1, 8987791055; RV32-V-NEXT: addi a0, a0, -5861056; RV32-V-NEXT: addi a1, a1, 17551057; RV32-V-NEXT: sw a1, 8(sp)1058; RV32-V-NEXT: sw a0, 12(sp)1059; RV32-V-NEXT: addi a0, sp, 81060; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma1061; RV32-V-NEXT: vlse64.v v10, (a0), zero1062; RV32-V-NEXT: li a0, 631063; RV32-V-NEXT: vmulh.vv v10, v8, v101064; RV32-V-NEXT: vsrl.vx v12, v10, a01065; RV32-V-NEXT: vsra.vi v10, v10, 11066; RV32-V-NEXT: vadd.vv v10, v10, v121067; RV32-V-NEXT: li a0, -71068; RV32-V-NEXT: vnmsac.vx v8, a0, v101069; RV32-V-NEXT: addi sp, sp, 161070; RV32-V-NEXT: .cfi_def_cfa_offset 01071; RV32-V-NEXT: ret1072;1073; ZVE64X-LABEL: vrem_vi_nxv2i64_0:1074; ZVE64X: # %bb.0:1075; ZVE64X-NEXT: li a0, -71076; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, ma1077; ZVE64X-NEXT: vrem.vx v8, v8, a01078; ZVE64X-NEXT: ret1079;1080; RV64-V-LABEL: vrem_vi_nxv2i64_0:1081; RV64-V: # %bb.0:1082; RV64-V-NEXT: lui a0, %hi(.LCPI70_0)1083; RV64-V-NEXT: ld a0, %lo(.LCPI70_0)(a0)1084; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma1085; RV64-V-NEXT: vmulh.vx v10, v8, a01086; RV64-V-NEXT: li a0, 631087; RV64-V-NEXT: vsrl.vx v12, v10, a01088; RV64-V-NEXT: vsra.vi v10, v10, 11089; RV64-V-NEXT: vadd.vv v10, v10, v121090; RV64-V-NEXT: li a0, -71091; RV64-V-NEXT: vnmsac.vx v8, a0, v101092; RV64-V-NEXT: ret1093 %vc = srem <vscale x 2 x i64> %va, splat (i64 -7)1094 ret <vscale x 2 x i64> %vc1095}1096 1097define <vscale x 4 x i64> @vrem_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {1098; CHECK-LABEL: vrem_vv_nxv4i64:1099; CHECK: # %bb.0:1100; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma1101; CHECK-NEXT: vrem.vv v8, v8, v121102; CHECK-NEXT: ret1103 %vc = srem <vscale x 4 x i64> %va, %vb1104 ret <vscale x 4 x i64> %vc1105}1106 1107define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {1108; RV32-LABEL: vrem_vx_nxv4i64:1109; RV32: # %bb.0:1110; RV32-NEXT: addi sp, sp, -161111; RV32-NEXT: .cfi_def_cfa_offset 161112; RV32-NEXT: sw a0, 8(sp)1113; RV32-NEXT: sw a1, 12(sp)1114; RV32-NEXT: addi a0, sp, 81115; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1116; RV32-NEXT: vlse64.v v12, (a0), zero1117; RV32-NEXT: vrem.vv v8, v8, v121118; RV32-NEXT: addi sp, sp, 161119; RV32-NEXT: .cfi_def_cfa_offset 01120; RV32-NEXT: ret1121;1122; RV64-LABEL: vrem_vx_nxv4i64:1123; RV64: # %bb.0:1124; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma1125; RV64-NEXT: vrem.vx v8, v8, a01126; RV64-NEXT: ret1127 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01128 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1129 %vc = srem <vscale x 4 x i64> %va, %splat1130 ret <vscale x 4 x i64> %vc1131}1132 1133define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {1134; RV32-V-LABEL: vrem_vi_nxv4i64_0:1135; RV32-V: # %bb.0:1136; RV32-V-NEXT: addi sp, sp, -161137; RV32-V-NEXT: .cfi_def_cfa_offset 161138; RV32-V-NEXT: lui a0, 7489831139; RV32-V-NEXT: lui a1, 8987791140; RV32-V-NEXT: addi a0, a0, -5861141; RV32-V-NEXT: addi a1, a1, 17551142; RV32-V-NEXT: sw a1, 8(sp)1143; RV32-V-NEXT: sw a0, 12(sp)1144; RV32-V-NEXT: addi a0, sp, 81145; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma1146; RV32-V-NEXT: vlse64.v v12, (a0), zero1147; RV32-V-NEXT: li a0, 631148; RV32-V-NEXT: vmulh.vv v12, v8, v121149; RV32-V-NEXT: vsrl.vx v16, v12, a01150; RV32-V-NEXT: vsra.vi v12, v12, 11151; RV32-V-NEXT: vadd.vv v12, v12, v161152; RV32-V-NEXT: li a0, -71153; RV32-V-NEXT: vnmsac.vx v8, a0, v121154; RV32-V-NEXT: addi sp, sp, 161155; RV32-V-NEXT: .cfi_def_cfa_offset 01156; RV32-V-NEXT: ret1157;1158; ZVE64X-LABEL: vrem_vi_nxv4i64_0:1159; ZVE64X: # %bb.0:1160; ZVE64X-NEXT: li a0, -71161; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, ma1162; ZVE64X-NEXT: vrem.vx v8, v8, a01163; ZVE64X-NEXT: ret1164;1165; RV64-V-LABEL: vrem_vi_nxv4i64_0:1166; RV64-V: # %bb.0:1167; RV64-V-NEXT: lui a0, %hi(.LCPI73_0)1168; RV64-V-NEXT: ld a0, %lo(.LCPI73_0)(a0)1169; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma1170; RV64-V-NEXT: vmulh.vx v12, v8, a01171; RV64-V-NEXT: li a0, 631172; RV64-V-NEXT: vsrl.vx v16, v12, a01173; RV64-V-NEXT: vsra.vi v12, v12, 11174; RV64-V-NEXT: vadd.vv v12, v12, v161175; RV64-V-NEXT: li a0, -71176; RV64-V-NEXT: vnmsac.vx v8, a0, v121177; RV64-V-NEXT: ret1178 %vc = srem <vscale x 4 x i64> %va, splat (i64 -7)1179 ret <vscale x 4 x i64> %vc1180}1181 1182define <vscale x 8 x i64> @vrem_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {1183; CHECK-LABEL: vrem_vv_nxv8i64:1184; CHECK: # %bb.0:1185; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1186; CHECK-NEXT: vrem.vv v8, v8, v161187; CHECK-NEXT: ret1188 %vc = srem <vscale x 8 x i64> %va, %vb1189 ret <vscale x 8 x i64> %vc1190}1191 1192define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {1193; RV32-LABEL: vrem_vx_nxv8i64:1194; RV32: # %bb.0:1195; RV32-NEXT: addi sp, sp, -161196; RV32-NEXT: .cfi_def_cfa_offset 161197; RV32-NEXT: sw a0, 8(sp)1198; RV32-NEXT: sw a1, 12(sp)1199; RV32-NEXT: addi a0, sp, 81200; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1201; RV32-NEXT: vlse64.v v16, (a0), zero1202; RV32-NEXT: vrem.vv v8, v8, v161203; RV32-NEXT: addi sp, sp, 161204; RV32-NEXT: .cfi_def_cfa_offset 01205; RV32-NEXT: ret1206;1207; RV64-LABEL: vrem_vx_nxv8i64:1208; RV64: # %bb.0:1209; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1210; RV64-NEXT: vrem.vx v8, v8, a01211; RV64-NEXT: ret1212 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01213 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1214 %vc = srem <vscale x 8 x i64> %va, %splat1215 ret <vscale x 8 x i64> %vc1216}1217 1218define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {1219; RV32-V-LABEL: vrem_vi_nxv8i64_0:1220; RV32-V: # %bb.0:1221; RV32-V-NEXT: addi sp, sp, -161222; RV32-V-NEXT: .cfi_def_cfa_offset 161223; RV32-V-NEXT: lui a0, 7489831224; RV32-V-NEXT: lui a1, 8987791225; RV32-V-NEXT: addi a0, a0, -5861226; RV32-V-NEXT: addi a1, a1, 17551227; RV32-V-NEXT: sw a1, 8(sp)1228; RV32-V-NEXT: sw a0, 12(sp)1229; RV32-V-NEXT: addi a0, sp, 81230; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1231; RV32-V-NEXT: vlse64.v v16, (a0), zero1232; RV32-V-NEXT: li a0, 631233; RV32-V-NEXT: vmulh.vv v16, v8, v161234; RV32-V-NEXT: vsrl.vx v24, v16, a01235; RV32-V-NEXT: vsra.vi v16, v16, 11236; RV32-V-NEXT: vadd.vv v16, v16, v241237; RV32-V-NEXT: li a0, -71238; RV32-V-NEXT: vnmsac.vx v8, a0, v161239; RV32-V-NEXT: addi sp, sp, 161240; RV32-V-NEXT: .cfi_def_cfa_offset 01241; RV32-V-NEXT: ret1242;1243; ZVE64X-LABEL: vrem_vi_nxv8i64_0:1244; ZVE64X: # %bb.0:1245; ZVE64X-NEXT: li a0, -71246; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma1247; ZVE64X-NEXT: vrem.vx v8, v8, a01248; ZVE64X-NEXT: ret1249;1250; RV64-V-LABEL: vrem_vi_nxv8i64_0:1251; RV64-V: # %bb.0:1252; RV64-V-NEXT: lui a0, %hi(.LCPI76_0)1253; RV64-V-NEXT: ld a0, %lo(.LCPI76_0)(a0)1254; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1255; RV64-V-NEXT: vmulh.vx v16, v8, a01256; RV64-V-NEXT: li a0, 631257; RV64-V-NEXT: vsrl.vx v24, v16, a01258; RV64-V-NEXT: vsra.vi v16, v16, 11259; RV64-V-NEXT: vadd.vv v16, v16, v241260; RV64-V-NEXT: li a0, -71261; RV64-V-NEXT: vnmsac.vx v8, a0, v161262; RV64-V-NEXT: ret1263 %vc = srem <vscale x 8 x i64> %va, splat (i64 -7)1264 ret <vscale x 8 x i64> %vc1265}1266