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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32-V3; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,ZVE64X4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64-V5; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,ZVE64X6 7define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {8; CHECK-LABEL: vremu_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vremu.vv v8, v8, v912; CHECK-NEXT: ret13 %vc = urem <vscale x 1 x i8> %va, %vb14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vremu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {18; CHECK-LABEL: vremu_vx_nxv1i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vremu.vx v8, v8, a022; CHECK-NEXT: ret23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %vc = urem <vscale x 1 x i8> %va, %splat26 ret <vscale x 1 x i8> %vc27}28 29define <vscale x 1 x i8> @vremu_vi_nxv1i8_0(<vscale x 1 x i8> %va) {30; CHECK-LABEL: vremu_vi_nxv1i8_0:31; CHECK: # %bb.0:32; CHECK-NEXT: li a0, 3333; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vmulhu.vx v9, v8, a035; CHECK-NEXT: vsrl.vi v9, v9, 536; CHECK-NEXT: li a0, -737; CHECK-NEXT: vnmsac.vx v8, a0, v938; CHECK-NEXT: ret39 %vc = urem <vscale x 1 x i8> %va, splat (i8 -7)40 ret <vscale x 1 x i8> %vc41}42 43define <vscale x 2 x i8> @vremu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {44; CHECK-LABEL: vremu_vv_nxv2i8:45; CHECK: # %bb.0:46; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma47; CHECK-NEXT: vremu.vv v8, v8, v948; CHECK-NEXT: ret49 %vc = urem <vscale x 2 x i8> %va, %vb50 ret <vscale x 2 x i8> %vc51}52 53define <vscale x 2 x i8> @vremu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {54; CHECK-LABEL: vremu_vx_nxv2i8:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma57; CHECK-NEXT: vremu.vx v8, v8, a058; CHECK-NEXT: ret59 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 060 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer61 %vc = urem <vscale x 2 x i8> %va, %splat62 ret <vscale x 2 x i8> %vc63}64 65define <vscale x 2 x i8> @vremu_vi_nxv2i8_0(<vscale x 2 x i8> %va) {66; CHECK-LABEL: vremu_vi_nxv2i8_0:67; CHECK: # %bb.0:68; CHECK-NEXT: li a0, 3369; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma70; CHECK-NEXT: vmulhu.vx v9, v8, a071; CHECK-NEXT: vsrl.vi v9, v9, 572; CHECK-NEXT: li a0, -773; CHECK-NEXT: vnmsac.vx v8, a0, v974; CHECK-NEXT: ret75 %vc = urem <vscale x 2 x i8> %va, splat (i8 -7)76 ret <vscale x 2 x i8> %vc77}78 79define <vscale x 4 x i8> @vremu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {80; CHECK-LABEL: vremu_vv_nxv4i8:81; CHECK: # %bb.0:82; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma83; CHECK-NEXT: vremu.vv v8, v8, v984; CHECK-NEXT: ret85 %vc = urem <vscale x 4 x i8> %va, %vb86 ret <vscale x 4 x i8> %vc87}88 89define <vscale x 4 x i8> @vremu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {90; CHECK-LABEL: vremu_vx_nxv4i8:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma93; CHECK-NEXT: vremu.vx v8, v8, a094; CHECK-NEXT: ret95 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 096 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer97 %vc = urem <vscale x 4 x i8> %va, %splat98 ret <vscale x 4 x i8> %vc99}100 101define <vscale x 4 x i8> @vremu_vi_nxv4i8_0(<vscale x 4 x i8> %va) {102; CHECK-LABEL: vremu_vi_nxv4i8_0:103; CHECK: # %bb.0:104; CHECK-NEXT: li a0, 33105; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma106; CHECK-NEXT: vmulhu.vx v9, v8, a0107; CHECK-NEXT: vsrl.vi v9, v9, 5108; CHECK-NEXT: li a0, -7109; CHECK-NEXT: vnmsac.vx v8, a0, v9110; CHECK-NEXT: ret111 %vc = urem <vscale x 4 x i8> %va, splat (i8 -7)112 ret <vscale x 4 x i8> %vc113}114 115define <vscale x 8 x i8> @vremu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {116; CHECK-LABEL: vremu_vv_nxv8i8:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma119; CHECK-NEXT: vremu.vv v8, v8, v9120; CHECK-NEXT: ret121 %vc = urem <vscale x 8 x i8> %va, %vb122 ret <vscale x 8 x i8> %vc123}124 125define <vscale x 8 x i8> @vremu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {126; CHECK-LABEL: vremu_vx_nxv8i8:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma129; CHECK-NEXT: vremu.vx v8, v8, a0130; CHECK-NEXT: ret131 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0132 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer133 %vc = urem <vscale x 8 x i8> %va, %splat134 ret <vscale x 8 x i8> %vc135}136 137define <vscale x 8 x i8> @vremu_vi_nxv8i8_0(<vscale x 8 x i8> %va) {138; CHECK-LABEL: vremu_vi_nxv8i8_0:139; CHECK: # %bb.0:140; CHECK-NEXT: li a0, 33141; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma142; CHECK-NEXT: vmulhu.vx v9, v8, a0143; CHECK-NEXT: vsrl.vi v9, v9, 5144; CHECK-NEXT: li a0, -7145; CHECK-NEXT: vnmsac.vx v8, a0, v9146; CHECK-NEXT: ret147 %vc = urem <vscale x 8 x i8> %va, splat (i8 -7)148 ret <vscale x 8 x i8> %vc149}150 151define <vscale x 16 x i8> @vremu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {152; CHECK-LABEL: vremu_vv_nxv16i8:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma155; CHECK-NEXT: vremu.vv v8, v8, v10156; CHECK-NEXT: ret157 %vc = urem <vscale x 16 x i8> %va, %vb158 ret <vscale x 16 x i8> %vc159}160 161define <vscale x 16 x i8> @vremu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {162; CHECK-LABEL: vremu_vx_nxv16i8:163; CHECK: # %bb.0:164; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma165; CHECK-NEXT: vremu.vx v8, v8, a0166; CHECK-NEXT: ret167 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0168 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer169 %vc = urem <vscale x 16 x i8> %va, %splat170 ret <vscale x 16 x i8> %vc171}172 173define <vscale x 16 x i8> @vremu_vi_nxv16i8_0(<vscale x 16 x i8> %va) {174; CHECK-LABEL: vremu_vi_nxv16i8_0:175; CHECK: # %bb.0:176; CHECK-NEXT: li a0, 33177; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma178; CHECK-NEXT: vmulhu.vx v10, v8, a0179; CHECK-NEXT: vsrl.vi v10, v10, 5180; CHECK-NEXT: li a0, -7181; CHECK-NEXT: vnmsac.vx v8, a0, v10182; CHECK-NEXT: ret183 %vc = urem <vscale x 16 x i8> %va, splat (i8 -7)184 ret <vscale x 16 x i8> %vc185}186 187define <vscale x 32 x i8> @vremu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {188; CHECK-LABEL: vremu_vv_nxv32i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma191; CHECK-NEXT: vremu.vv v8, v8, v12192; CHECK-NEXT: ret193 %vc = urem <vscale x 32 x i8> %va, %vb194 ret <vscale x 32 x i8> %vc195}196 197define <vscale x 32 x i8> @vremu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {198; CHECK-LABEL: vremu_vx_nxv32i8:199; CHECK: # %bb.0:200; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma201; CHECK-NEXT: vremu.vx v8, v8, a0202; CHECK-NEXT: ret203 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0204 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer205 %vc = urem <vscale x 32 x i8> %va, %splat206 ret <vscale x 32 x i8> %vc207}208 209define <vscale x 32 x i8> @vremu_vi_nxv32i8_0(<vscale x 32 x i8> %va) {210; CHECK-LABEL: vremu_vi_nxv32i8_0:211; CHECK: # %bb.0:212; CHECK-NEXT: li a0, 33213; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma214; CHECK-NEXT: vmulhu.vx v12, v8, a0215; CHECK-NEXT: vsrl.vi v12, v12, 5216; CHECK-NEXT: li a0, -7217; CHECK-NEXT: vnmsac.vx v8, a0, v12218; CHECK-NEXT: ret219 %vc = urem <vscale x 32 x i8> %va, splat (i8 -7)220 ret <vscale x 32 x i8> %vc221}222 223define <vscale x 64 x i8> @vremu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {224; CHECK-LABEL: vremu_vv_nxv64i8:225; CHECK: # %bb.0:226; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma227; CHECK-NEXT: vremu.vv v8, v8, v16228; CHECK-NEXT: ret229 %vc = urem <vscale x 64 x i8> %va, %vb230 ret <vscale x 64 x i8> %vc231}232 233define <vscale x 64 x i8> @vremu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {234; CHECK-LABEL: vremu_vx_nxv64i8:235; CHECK: # %bb.0:236; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma237; CHECK-NEXT: vremu.vx v8, v8, a0238; CHECK-NEXT: ret239 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0240 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer241 %vc = urem <vscale x 64 x i8> %va, %splat242 ret <vscale x 64 x i8> %vc243}244 245define <vscale x 64 x i8> @vremu_vi_nxv64i8_0(<vscale x 64 x i8> %va) {246; CHECK-LABEL: vremu_vi_nxv64i8_0:247; CHECK: # %bb.0:248; CHECK-NEXT: li a0, 33249; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma250; CHECK-NEXT: vmulhu.vx v16, v8, a0251; CHECK-NEXT: vsrl.vi v16, v16, 5252; CHECK-NEXT: li a0, -7253; CHECK-NEXT: vnmsac.vx v8, a0, v16254; CHECK-NEXT: ret255 %vc = urem <vscale x 64 x i8> %va, splat (i8 -7)256 ret <vscale x 64 x i8> %vc257}258 259define <vscale x 1 x i16> @vremu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {260; CHECK-LABEL: vremu_vv_nxv1i16:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma263; CHECK-NEXT: vremu.vv v8, v8, v9264; CHECK-NEXT: ret265 %vc = urem <vscale x 1 x i16> %va, %vb266 ret <vscale x 1 x i16> %vc267}268 269define <vscale x 1 x i16> @vremu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {270; CHECK-LABEL: vremu_vx_nxv1i16:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma273; CHECK-NEXT: vremu.vx v8, v8, a0274; CHECK-NEXT: ret275 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0276 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer277 %vc = urem <vscale x 1 x i16> %va, %splat278 ret <vscale x 1 x i16> %vc279}280 281define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {282; CHECK-LABEL: vremu_vi_nxv1i16_0:283; CHECK: # %bb.0:284; CHECK-NEXT: lui a0, 2285; CHECK-NEXT: addi a0, a0, 1286; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma287; CHECK-NEXT: vmulhu.vx v9, v8, a0288; CHECK-NEXT: vsrl.vi v9, v9, 13289; CHECK-NEXT: li a0, -7290; CHECK-NEXT: vnmsac.vx v8, a0, v9291; CHECK-NEXT: ret292 %vc = urem <vscale x 1 x i16> %va, splat (i16 -7)293 ret <vscale x 1 x i16> %vc294}295 296define <vscale x 2 x i16> @vremu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {297; CHECK-LABEL: vremu_vv_nxv2i16:298; CHECK: # %bb.0:299; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma300; CHECK-NEXT: vremu.vv v8, v8, v9301; CHECK-NEXT: ret302 %vc = urem <vscale x 2 x i16> %va, %vb303 ret <vscale x 2 x i16> %vc304}305 306define <vscale x 2 x i16> @vremu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {307; CHECK-LABEL: vremu_vx_nxv2i16:308; CHECK: # %bb.0:309; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma310; CHECK-NEXT: vremu.vx v8, v8, a0311; CHECK-NEXT: ret312 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0313 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer314 %vc = urem <vscale x 2 x i16> %va, %splat315 ret <vscale x 2 x i16> %vc316}317 318define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {319; CHECK-LABEL: vremu_vi_nxv2i16_0:320; CHECK: # %bb.0:321; CHECK-NEXT: lui a0, 2322; CHECK-NEXT: addi a0, a0, 1323; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma324; CHECK-NEXT: vmulhu.vx v9, v8, a0325; CHECK-NEXT: vsrl.vi v9, v9, 13326; CHECK-NEXT: li a0, -7327; CHECK-NEXT: vnmsac.vx v8, a0, v9328; CHECK-NEXT: ret329 %vc = urem <vscale x 2 x i16> %va, splat (i16 -7)330 ret <vscale x 2 x i16> %vc331}332 333define <vscale x 4 x i16> @vremu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {334; CHECK-LABEL: vremu_vv_nxv4i16:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma337; CHECK-NEXT: vremu.vv v8, v8, v9338; CHECK-NEXT: ret339 %vc = urem <vscale x 4 x i16> %va, %vb340 ret <vscale x 4 x i16> %vc341}342 343define <vscale x 4 x i16> @vremu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {344; CHECK-LABEL: vremu_vx_nxv4i16:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma347; CHECK-NEXT: vremu.vx v8, v8, a0348; CHECK-NEXT: ret349 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0350 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer351 %vc = urem <vscale x 4 x i16> %va, %splat352 ret <vscale x 4 x i16> %vc353}354 355define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {356; CHECK-LABEL: vremu_vi_nxv4i16_0:357; CHECK: # %bb.0:358; CHECK-NEXT: lui a0, 2359; CHECK-NEXT: addi a0, a0, 1360; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma361; CHECK-NEXT: vmulhu.vx v9, v8, a0362; CHECK-NEXT: vsrl.vi v9, v9, 13363; CHECK-NEXT: li a0, -7364; CHECK-NEXT: vnmsac.vx v8, a0, v9365; CHECK-NEXT: ret366 %vc = urem <vscale x 4 x i16> %va, splat (i16 -7)367 ret <vscale x 4 x i16> %vc368}369 370define <vscale x 8 x i16> @vremu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {371; CHECK-LABEL: vremu_vv_nxv8i16:372; CHECK: # %bb.0:373; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma374; CHECK-NEXT: vremu.vv v8, v8, v10375; CHECK-NEXT: ret376 %vc = urem <vscale x 8 x i16> %va, %vb377 ret <vscale x 8 x i16> %vc378}379 380define <vscale x 8 x i16> @vremu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {381; CHECK-LABEL: vremu_vx_nxv8i16:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma384; CHECK-NEXT: vremu.vx v8, v8, a0385; CHECK-NEXT: ret386 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0387 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer388 %vc = urem <vscale x 8 x i16> %va, %splat389 ret <vscale x 8 x i16> %vc390}391 392define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {393; CHECK-LABEL: vremu_vi_nxv8i16_0:394; CHECK: # %bb.0:395; CHECK-NEXT: lui a0, 2396; CHECK-NEXT: addi a0, a0, 1397; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma398; CHECK-NEXT: vmulhu.vx v10, v8, a0399; CHECK-NEXT: vsrl.vi v10, v10, 13400; CHECK-NEXT: li a0, -7401; CHECK-NEXT: vnmsac.vx v8, a0, v10402; CHECK-NEXT: ret403 %vc = urem <vscale x 8 x i16> %va, splat (i16 -7)404 ret <vscale x 8 x i16> %vc405}406 407define <vscale x 16 x i16> @vremu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {408; CHECK-LABEL: vremu_vv_nxv16i16:409; CHECK: # %bb.0:410; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma411; CHECK-NEXT: vremu.vv v8, v8, v12412; CHECK-NEXT: ret413 %vc = urem <vscale x 16 x i16> %va, %vb414 ret <vscale x 16 x i16> %vc415}416 417define <vscale x 16 x i16> @vremu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {418; CHECK-LABEL: vremu_vx_nxv16i16:419; CHECK: # %bb.0:420; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma421; CHECK-NEXT: vremu.vx v8, v8, a0422; CHECK-NEXT: ret423 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0424 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer425 %vc = urem <vscale x 16 x i16> %va, %splat426 ret <vscale x 16 x i16> %vc427}428 429define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {430; CHECK-LABEL: vremu_vi_nxv16i16_0:431; CHECK: # %bb.0:432; CHECK-NEXT: lui a0, 2433; CHECK-NEXT: addi a0, a0, 1434; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma435; CHECK-NEXT: vmulhu.vx v12, v8, a0436; CHECK-NEXT: vsrl.vi v12, v12, 13437; CHECK-NEXT: li a0, -7438; CHECK-NEXT: vnmsac.vx v8, a0, v12439; CHECK-NEXT: ret440 %vc = urem <vscale x 16 x i16> %va, splat (i16 -7)441 ret <vscale x 16 x i16> %vc442}443 444define <vscale x 32 x i16> @vremu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {445; CHECK-LABEL: vremu_vv_nxv32i16:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma448; CHECK-NEXT: vremu.vv v8, v8, v16449; CHECK-NEXT: ret450 %vc = urem <vscale x 32 x i16> %va, %vb451 ret <vscale x 32 x i16> %vc452}453 454define <vscale x 32 x i16> @vremu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {455; CHECK-LABEL: vremu_vx_nxv32i16:456; CHECK: # %bb.0:457; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma458; CHECK-NEXT: vremu.vx v8, v8, a0459; CHECK-NEXT: ret460 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0461 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer462 %vc = urem <vscale x 32 x i16> %va, %splat463 ret <vscale x 32 x i16> %vc464}465 466define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {467; CHECK-LABEL: vremu_vi_nxv32i16_0:468; CHECK: # %bb.0:469; CHECK-NEXT: lui a0, 2470; CHECK-NEXT: addi a0, a0, 1471; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma472; CHECK-NEXT: vmulhu.vx v16, v8, a0473; CHECK-NEXT: vsrl.vi v16, v16, 13474; CHECK-NEXT: li a0, -7475; CHECK-NEXT: vnmsac.vx v8, a0, v16476; CHECK-NEXT: ret477 %vc = urem <vscale x 32 x i16> %va, splat (i16 -7)478 ret <vscale x 32 x i16> %vc479}480 481define <vscale x 1 x i32> @vremu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {482; CHECK-LABEL: vremu_vv_nxv1i32:483; CHECK: # %bb.0:484; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma485; CHECK-NEXT: vremu.vv v8, v8, v9486; CHECK-NEXT: ret487 %vc = urem <vscale x 1 x i32> %va, %vb488 ret <vscale x 1 x i32> %vc489}490 491define <vscale x 1 x i32> @vremu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {492; CHECK-LABEL: vremu_vx_nxv1i32:493; CHECK: # %bb.0:494; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma495; CHECK-NEXT: vremu.vx v8, v8, a0496; CHECK-NEXT: ret497 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0498 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer499 %vc = urem <vscale x 1 x i32> %va, %splat500 ret <vscale x 1 x i32> %vc501}502 503define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {504; CHECK-LABEL: vremu_vi_nxv1i32_0:505; CHECK: # %bb.0:506; CHECK-NEXT: lui a0, 131072507; CHECK-NEXT: addi a0, a0, 1508; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma509; CHECK-NEXT: vmulhu.vx v9, v8, a0510; CHECK-NEXT: vsrl.vi v9, v9, 29511; CHECK-NEXT: li a0, -7512; CHECK-NEXT: vnmsac.vx v8, a0, v9513; CHECK-NEXT: ret514 %vc = urem <vscale x 1 x i32> %va, splat (i32 -7)515 ret <vscale x 1 x i32> %vc516}517 518define <vscale x 2 x i32> @vremu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {519; CHECK-LABEL: vremu_vv_nxv2i32:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma522; CHECK-NEXT: vremu.vv v8, v8, v9523; CHECK-NEXT: ret524 %vc = urem <vscale x 2 x i32> %va, %vb525 ret <vscale x 2 x i32> %vc526}527 528define <vscale x 2 x i32> @vremu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {529; CHECK-LABEL: vremu_vx_nxv2i32:530; CHECK: # %bb.0:531; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma532; CHECK-NEXT: vremu.vx v8, v8, a0533; CHECK-NEXT: ret534 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0535 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer536 %vc = urem <vscale x 2 x i32> %va, %splat537 ret <vscale x 2 x i32> %vc538}539 540define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {541; CHECK-LABEL: vremu_vi_nxv2i32_0:542; CHECK: # %bb.0:543; CHECK-NEXT: lui a0, 131072544; CHECK-NEXT: addi a0, a0, 1545; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma546; CHECK-NEXT: vmulhu.vx v9, v8, a0547; CHECK-NEXT: vsrl.vi v9, v9, 29548; CHECK-NEXT: li a0, -7549; CHECK-NEXT: vnmsac.vx v8, a0, v9550; CHECK-NEXT: ret551 %vc = urem <vscale x 2 x i32> %va, splat (i32 -7)552 ret <vscale x 2 x i32> %vc553}554 555define <vscale x 4 x i32> @vremu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {556; CHECK-LABEL: vremu_vv_nxv4i32:557; CHECK: # %bb.0:558; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma559; CHECK-NEXT: vremu.vv v8, v8, v10560; CHECK-NEXT: ret561 %vc = urem <vscale x 4 x i32> %va, %vb562 ret <vscale x 4 x i32> %vc563}564 565define <vscale x 4 x i32> @vremu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {566; CHECK-LABEL: vremu_vx_nxv4i32:567; CHECK: # %bb.0:568; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma569; CHECK-NEXT: vremu.vx v8, v8, a0570; CHECK-NEXT: ret571 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0572 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer573 %vc = urem <vscale x 4 x i32> %va, %splat574 ret <vscale x 4 x i32> %vc575}576 577define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {578; CHECK-LABEL: vremu_vi_nxv4i32_0:579; CHECK: # %bb.0:580; CHECK-NEXT: lui a0, 131072581; CHECK-NEXT: addi a0, a0, 1582; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma583; CHECK-NEXT: vmulhu.vx v10, v8, a0584; CHECK-NEXT: vsrl.vi v10, v10, 29585; CHECK-NEXT: li a0, -7586; CHECK-NEXT: vnmsac.vx v8, a0, v10587; CHECK-NEXT: ret588 %vc = urem <vscale x 4 x i32> %va, splat (i32 -7)589 ret <vscale x 4 x i32> %vc590}591 592define <vscale x 8 x i32> @vremu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {593; CHECK-LABEL: vremu_vv_nxv8i32:594; CHECK: # %bb.0:595; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma596; CHECK-NEXT: vremu.vv v8, v8, v12597; CHECK-NEXT: ret598 %vc = urem <vscale x 8 x i32> %va, %vb599 ret <vscale x 8 x i32> %vc600}601 602define <vscale x 8 x i32> @vremu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {603; CHECK-LABEL: vremu_vx_nxv8i32:604; CHECK: # %bb.0:605; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma606; CHECK-NEXT: vremu.vx v8, v8, a0607; CHECK-NEXT: ret608 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0609 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer610 %vc = urem <vscale x 8 x i32> %va, %splat611 ret <vscale x 8 x i32> %vc612}613 614define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {615; CHECK-LABEL: vremu_vi_nxv8i32_0:616; CHECK: # %bb.0:617; CHECK-NEXT: lui a0, 131072618; CHECK-NEXT: addi a0, a0, 1619; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma620; CHECK-NEXT: vmulhu.vx v12, v8, a0621; CHECK-NEXT: vsrl.vi v12, v12, 29622; CHECK-NEXT: li a0, -7623; CHECK-NEXT: vnmsac.vx v8, a0, v12624; CHECK-NEXT: ret625 %vc = urem <vscale x 8 x i32> %va, splat (i32 -7)626 ret <vscale x 8 x i32> %vc627}628 629define <vscale x 16 x i32> @vremu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {630; CHECK-LABEL: vremu_vv_nxv16i32:631; CHECK: # %bb.0:632; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma633; CHECK-NEXT: vremu.vv v8, v8, v16634; CHECK-NEXT: ret635 %vc = urem <vscale x 16 x i32> %va, %vb636 ret <vscale x 16 x i32> %vc637}638 639define <vscale x 16 x i32> @vremu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {640; CHECK-LABEL: vremu_vx_nxv16i32:641; CHECK: # %bb.0:642; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma643; CHECK-NEXT: vremu.vx v8, v8, a0644; CHECK-NEXT: ret645 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0646 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer647 %vc = urem <vscale x 16 x i32> %va, %splat648 ret <vscale x 16 x i32> %vc649}650 651define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {652; CHECK-LABEL: vremu_vi_nxv16i32_0:653; CHECK: # %bb.0:654; CHECK-NEXT: lui a0, 131072655; CHECK-NEXT: addi a0, a0, 1656; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma657; CHECK-NEXT: vmulhu.vx v16, v8, a0658; CHECK-NEXT: vsrl.vi v16, v16, 29659; CHECK-NEXT: li a0, -7660; CHECK-NEXT: vnmsac.vx v8, a0, v16661; CHECK-NEXT: ret662 %vc = urem <vscale x 16 x i32> %va, splat (i32 -7)663 ret <vscale x 16 x i32> %vc664}665 666define <vscale x 1 x i64> @vremu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {667; CHECK-LABEL: vremu_vv_nxv1i64:668; CHECK: # %bb.0:669; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma670; CHECK-NEXT: vremu.vv v8, v8, v9671; CHECK-NEXT: ret672 %vc = urem <vscale x 1 x i64> %va, %vb673 ret <vscale x 1 x i64> %vc674}675 676define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {677; RV32-LABEL: vremu_vx_nxv1i64:678; RV32: # %bb.0:679; RV32-NEXT: addi sp, sp, -16680; RV32-NEXT: .cfi_def_cfa_offset 16681; RV32-NEXT: sw a0, 8(sp)682; RV32-NEXT: sw a1, 12(sp)683; RV32-NEXT: addi a0, sp, 8684; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma685; RV32-NEXT: vlse64.v v9, (a0), zero686; RV32-NEXT: vremu.vv v8, v8, v9687; RV32-NEXT: addi sp, sp, 16688; RV32-NEXT: .cfi_def_cfa_offset 0689; RV32-NEXT: ret690;691; RV64-LABEL: vremu_vx_nxv1i64:692; RV64: # %bb.0:693; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma694; RV64-NEXT: vremu.vx v8, v8, a0695; RV64-NEXT: ret696 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0697 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer698 %vc = urem <vscale x 1 x i64> %va, %splat699 ret <vscale x 1 x i64> %vc700}701 702define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {703; RV32-V-LABEL: vremu_vi_nxv1i64_0:704; RV32-V: # %bb.0:705; RV32-V-NEXT: addi sp, sp, -16706; RV32-V-NEXT: .cfi_def_cfa_offset 16707; RV32-V-NEXT: lui a0, 131072708; RV32-V-NEXT: li a1, 1709; RV32-V-NEXT: sw a1, 8(sp)710; RV32-V-NEXT: sw a0, 12(sp)711; RV32-V-NEXT: addi a0, sp, 8712; RV32-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma713; RV32-V-NEXT: vlse64.v v9, (a0), zero714; RV32-V-NEXT: li a0, 61715; RV32-V-NEXT: vmulhu.vv v9, v8, v9716; RV32-V-NEXT: vsrl.vx v9, v9, a0717; RV32-V-NEXT: li a0, -7718; RV32-V-NEXT: vnmsac.vx v8, a0, v9719; RV32-V-NEXT: addi sp, sp, 16720; RV32-V-NEXT: .cfi_def_cfa_offset 0721; RV32-V-NEXT: ret722;723; ZVE64X-LABEL: vremu_vi_nxv1i64_0:724; ZVE64X: # %bb.0:725; ZVE64X-NEXT: li a0, -7726; ZVE64X-NEXT: vsetvli a1, zero, e64, m1, ta, ma727; ZVE64X-NEXT: vremu.vx v8, v8, a0728; ZVE64X-NEXT: ret729;730; RV64-V-LABEL: vremu_vi_nxv1i64_0:731; RV64-V: # %bb.0:732; RV64-V-NEXT: li a0, 1733; RV64-V-NEXT: slli a0, a0, 61734; RV64-V-NEXT: addi a0, a0, 1735; RV64-V-NEXT: vsetvli a1, zero, e64, m1, ta, ma736; RV64-V-NEXT: vmulhu.vx v9, v8, a0737; RV64-V-NEXT: li a0, 61738; RV64-V-NEXT: vsrl.vx v9, v9, a0739; RV64-V-NEXT: li a0, -7740; RV64-V-NEXT: vnmsac.vx v8, a0, v9741; RV64-V-NEXT: ret742 %vc = urem <vscale x 1 x i64> %va, splat (i64 -7)743 ret <vscale x 1 x i64> %vc744}745 746; fold (urem x, pow2) -> (and x, pow2-1)747define <vscale x 1 x i64> @vremu_vi_nxv1i64_1(<vscale x 1 x i64> %va) {748; CHECK-LABEL: vremu_vi_nxv1i64_1:749; CHECK: # %bb.0:750; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma751; CHECK-NEXT: vand.vi v8, v8, 15752; CHECK-NEXT: ret753 %vc = urem <vscale x 1 x i64> %va, splat (i64 16)754 ret <vscale x 1 x i64> %vc755}756 757; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))758define <vscale x 1 x i64> @vremu_vi_nxv1i64_2(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {759; CHECK-LABEL: vremu_vi_nxv1i64_2:760; CHECK: # %bb.0:761; CHECK-NEXT: li a0, 16762; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma763; CHECK-NEXT: vmv.v.x v10, a0764; CHECK-NEXT: vsll.vv v9, v10, v9765; CHECK-NEXT: vadd.vi v9, v9, -1766; CHECK-NEXT: vand.vv v8, v8, v9767; CHECK-NEXT: ret768 %vc = shl <vscale x 1 x i64> splat (i64 16), %vb769 %vd = urem <vscale x 1 x i64> %va, %vc770 ret <vscale x 1 x i64> %vd771}772 773define <vscale x 2 x i64> @vremu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {774; CHECK-LABEL: vremu_vv_nxv2i64:775; CHECK: # %bb.0:776; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma777; CHECK-NEXT: vremu.vv v8, v8, v10778; CHECK-NEXT: ret779 %vc = urem <vscale x 2 x i64> %va, %vb780 ret <vscale x 2 x i64> %vc781}782 783define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {784; RV32-LABEL: vremu_vx_nxv2i64:785; RV32: # %bb.0:786; RV32-NEXT: addi sp, sp, -16787; RV32-NEXT: .cfi_def_cfa_offset 16788; RV32-NEXT: sw a0, 8(sp)789; RV32-NEXT: sw a1, 12(sp)790; RV32-NEXT: addi a0, sp, 8791; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma792; RV32-NEXT: vlse64.v v10, (a0), zero793; RV32-NEXT: vremu.vv v8, v8, v10794; RV32-NEXT: addi sp, sp, 16795; RV32-NEXT: .cfi_def_cfa_offset 0796; RV32-NEXT: ret797;798; RV64-LABEL: vremu_vx_nxv2i64:799; RV64: # %bb.0:800; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma801; RV64-NEXT: vremu.vx v8, v8, a0802; RV64-NEXT: ret803 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0804 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer805 %vc = urem <vscale x 2 x i64> %va, %splat806 ret <vscale x 2 x i64> %vc807}808 809define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {810; RV32-V-LABEL: vremu_vi_nxv2i64_0:811; RV32-V: # %bb.0:812; RV32-V-NEXT: addi sp, sp, -16813; RV32-V-NEXT: .cfi_def_cfa_offset 16814; RV32-V-NEXT: lui a0, 131072815; RV32-V-NEXT: li a1, 1816; RV32-V-NEXT: sw a1, 8(sp)817; RV32-V-NEXT: sw a0, 12(sp)818; RV32-V-NEXT: addi a0, sp, 8819; RV32-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma820; RV32-V-NEXT: vlse64.v v10, (a0), zero821; RV32-V-NEXT: li a0, 61822; RV32-V-NEXT: vmulhu.vv v10, v8, v10823; RV32-V-NEXT: vsrl.vx v10, v10, a0824; RV32-V-NEXT: li a0, -7825; RV32-V-NEXT: vnmsac.vx v8, a0, v10826; RV32-V-NEXT: addi sp, sp, 16827; RV32-V-NEXT: .cfi_def_cfa_offset 0828; RV32-V-NEXT: ret829;830; ZVE64X-LABEL: vremu_vi_nxv2i64_0:831; ZVE64X: # %bb.0:832; ZVE64X-NEXT: li a0, -7833; ZVE64X-NEXT: vsetvli a1, zero, e64, m2, ta, ma834; ZVE64X-NEXT: vremu.vx v8, v8, a0835; ZVE64X-NEXT: ret836;837; RV64-V-LABEL: vremu_vi_nxv2i64_0:838; RV64-V: # %bb.0:839; RV64-V-NEXT: li a0, 1840; RV64-V-NEXT: slli a0, a0, 61841; RV64-V-NEXT: addi a0, a0, 1842; RV64-V-NEXT: vsetvli a1, zero, e64, m2, ta, ma843; RV64-V-NEXT: vmulhu.vx v10, v8, a0844; RV64-V-NEXT: li a0, 61845; RV64-V-NEXT: vsrl.vx v10, v10, a0846; RV64-V-NEXT: li a0, -7847; RV64-V-NEXT: vnmsac.vx v8, a0, v10848; RV64-V-NEXT: ret849 %vc = urem <vscale x 2 x i64> %va, splat (i64 -7)850 ret <vscale x 2 x i64> %vc851}852 853; fold (urem x, pow2) -> (and x, pow2-1)854define <vscale x 2 x i64> @vremu_vi_nxv2i64_1(<vscale x 2 x i64> %va) {855; CHECK-LABEL: vremu_vi_nxv2i64_1:856; CHECK: # %bb.0:857; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma858; CHECK-NEXT: vand.vi v8, v8, 15859; CHECK-NEXT: ret860 %vc = urem <vscale x 2 x i64> %va, splat (i64 16)861 ret <vscale x 2 x i64> %vc862}863 864; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))865define <vscale x 2 x i64> @vremu_vi_nxv2i64_2(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {866; CHECK-LABEL: vremu_vi_nxv2i64_2:867; CHECK: # %bb.0:868; CHECK-NEXT: li a0, 16869; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma870; CHECK-NEXT: vmv.v.x v12, a0871; CHECK-NEXT: vsll.vv v10, v12, v10872; CHECK-NEXT: vadd.vi v10, v10, -1873; CHECK-NEXT: vand.vv v8, v8, v10874; CHECK-NEXT: ret875 %vc = shl <vscale x 2 x i64> splat (i64 16), %vb876 %vd = urem <vscale x 2 x i64> %va, %vc877 ret <vscale x 2 x i64> %vd878}879 880define <vscale x 4 x i64> @vremu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {881; CHECK-LABEL: vremu_vv_nxv4i64:882; CHECK: # %bb.0:883; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma884; CHECK-NEXT: vremu.vv v8, v8, v12885; CHECK-NEXT: ret886 %vc = urem <vscale x 4 x i64> %va, %vb887 ret <vscale x 4 x i64> %vc888}889 890define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {891; RV32-LABEL: vremu_vx_nxv4i64:892; RV32: # %bb.0:893; RV32-NEXT: addi sp, sp, -16894; RV32-NEXT: .cfi_def_cfa_offset 16895; RV32-NEXT: sw a0, 8(sp)896; RV32-NEXT: sw a1, 12(sp)897; RV32-NEXT: addi a0, sp, 8898; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma899; RV32-NEXT: vlse64.v v12, (a0), zero900; RV32-NEXT: vremu.vv v8, v8, v12901; RV32-NEXT: addi sp, sp, 16902; RV32-NEXT: .cfi_def_cfa_offset 0903; RV32-NEXT: ret904;905; RV64-LABEL: vremu_vx_nxv4i64:906; RV64: # %bb.0:907; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma908; RV64-NEXT: vremu.vx v8, v8, a0909; RV64-NEXT: ret910 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0911 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer912 %vc = urem <vscale x 4 x i64> %va, %splat913 ret <vscale x 4 x i64> %vc914}915 916define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {917; RV32-V-LABEL: vremu_vi_nxv4i64_0:918; RV32-V: # %bb.0:919; RV32-V-NEXT: addi sp, sp, -16920; RV32-V-NEXT: .cfi_def_cfa_offset 16921; RV32-V-NEXT: lui a0, 131072922; RV32-V-NEXT: li a1, 1923; RV32-V-NEXT: sw a1, 8(sp)924; RV32-V-NEXT: sw a0, 12(sp)925; RV32-V-NEXT: addi a0, sp, 8926; RV32-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma927; RV32-V-NEXT: vlse64.v v12, (a0), zero928; RV32-V-NEXT: li a0, 61929; RV32-V-NEXT: vmulhu.vv v12, v8, v12930; RV32-V-NEXT: vsrl.vx v12, v12, a0931; RV32-V-NEXT: li a0, -7932; RV32-V-NEXT: vnmsac.vx v8, a0, v12933; RV32-V-NEXT: addi sp, sp, 16934; RV32-V-NEXT: .cfi_def_cfa_offset 0935; RV32-V-NEXT: ret936;937; ZVE64X-LABEL: vremu_vi_nxv4i64_0:938; ZVE64X: # %bb.0:939; ZVE64X-NEXT: li a0, -7940; ZVE64X-NEXT: vsetvli a1, zero, e64, m4, ta, ma941; ZVE64X-NEXT: vremu.vx v8, v8, a0942; ZVE64X-NEXT: ret943;944; RV64-V-LABEL: vremu_vi_nxv4i64_0:945; RV64-V: # %bb.0:946; RV64-V-NEXT: li a0, 1947; RV64-V-NEXT: slli a0, a0, 61948; RV64-V-NEXT: addi a0, a0, 1949; RV64-V-NEXT: vsetvli a1, zero, e64, m4, ta, ma950; RV64-V-NEXT: vmulhu.vx v12, v8, a0951; RV64-V-NEXT: li a0, 61952; RV64-V-NEXT: vsrl.vx v12, v12, a0953; RV64-V-NEXT: li a0, -7954; RV64-V-NEXT: vnmsac.vx v8, a0, v12955; RV64-V-NEXT: ret956 %vc = urem <vscale x 4 x i64> %va, splat (i64 -7)957 ret <vscale x 4 x i64> %vc958}959 960; fold (urem x, pow2) -> (and x, pow2-1)961define <vscale x 4 x i64> @vremu_vi_nxv4i64_1(<vscale x 4 x i64> %va) {962; CHECK-LABEL: vremu_vi_nxv4i64_1:963; CHECK: # %bb.0:964; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma965; CHECK-NEXT: vand.vi v8, v8, 15966; CHECK-NEXT: ret967 %vc = urem <vscale x 4 x i64> %va, splat (i64 16)968 ret <vscale x 4 x i64> %vc969}970 971;fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))972define <vscale x 4 x i64> @vremu_vi_nxv4i64_2(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {973; CHECK-LABEL: vremu_vi_nxv4i64_2:974; CHECK: # %bb.0:975; CHECK-NEXT: li a0, 16976; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma977; CHECK-NEXT: vmv.v.x v16, a0978; CHECK-NEXT: vsll.vv v12, v16, v12979; CHECK-NEXT: vadd.vi v12, v12, -1980; CHECK-NEXT: vand.vv v8, v8, v12981; CHECK-NEXT: ret982 %vc = shl <vscale x 4 x i64> splat (i64 16), %vb983 %vd = urem <vscale x 4 x i64> %va, %vc984 ret <vscale x 4 x i64> %vd985}986 987define <vscale x 8 x i64> @vremu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {988; CHECK-LABEL: vremu_vv_nxv8i64:989; CHECK: # %bb.0:990; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma991; CHECK-NEXT: vremu.vv v8, v8, v16992; CHECK-NEXT: ret993 %vc = urem <vscale x 8 x i64> %va, %vb994 ret <vscale x 8 x i64> %vc995}996 997define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {998; RV32-LABEL: vremu_vx_nxv8i64:999; RV32: # %bb.0:1000; RV32-NEXT: addi sp, sp, -161001; RV32-NEXT: .cfi_def_cfa_offset 161002; RV32-NEXT: sw a0, 8(sp)1003; RV32-NEXT: sw a1, 12(sp)1004; RV32-NEXT: addi a0, sp, 81005; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1006; RV32-NEXT: vlse64.v v16, (a0), zero1007; RV32-NEXT: vremu.vv v8, v8, v161008; RV32-NEXT: addi sp, sp, 161009; RV32-NEXT: .cfi_def_cfa_offset 01010; RV32-NEXT: ret1011;1012; RV64-LABEL: vremu_vx_nxv8i64:1013; RV64: # %bb.0:1014; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma1015; RV64-NEXT: vremu.vx v8, v8, a01016; RV64-NEXT: ret1017 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01018 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1019 %vc = urem <vscale x 8 x i64> %va, %splat1020 ret <vscale x 8 x i64> %vc1021}1022 1023define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {1024; RV32-V-LABEL: vremu_vi_nxv8i64_0:1025; RV32-V: # %bb.0:1026; RV32-V-NEXT: addi sp, sp, -161027; RV32-V-NEXT: .cfi_def_cfa_offset 161028; RV32-V-NEXT: lui a0, 1310721029; RV32-V-NEXT: li a1, 11030; RV32-V-NEXT: sw a1, 8(sp)1031; RV32-V-NEXT: sw a0, 12(sp)1032; RV32-V-NEXT: addi a0, sp, 81033; RV32-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1034; RV32-V-NEXT: vlse64.v v16, (a0), zero1035; RV32-V-NEXT: li a0, 611036; RV32-V-NEXT: vmulhu.vv v16, v8, v161037; RV32-V-NEXT: vsrl.vx v16, v16, a01038; RV32-V-NEXT: li a0, -71039; RV32-V-NEXT: vnmsac.vx v8, a0, v161040; RV32-V-NEXT: addi sp, sp, 161041; RV32-V-NEXT: .cfi_def_cfa_offset 01042; RV32-V-NEXT: ret1043;1044; ZVE64X-LABEL: vremu_vi_nxv8i64_0:1045; ZVE64X: # %bb.0:1046; ZVE64X-NEXT: li a0, -71047; ZVE64X-NEXT: vsetvli a1, zero, e64, m8, ta, ma1048; ZVE64X-NEXT: vremu.vx v8, v8, a01049; ZVE64X-NEXT: ret1050;1051; RV64-V-LABEL: vremu_vi_nxv8i64_0:1052; RV64-V: # %bb.0:1053; RV64-V-NEXT: li a0, 11054; RV64-V-NEXT: slli a0, a0, 611055; RV64-V-NEXT: addi a0, a0, 11056; RV64-V-NEXT: vsetvli a1, zero, e64, m8, ta, ma1057; RV64-V-NEXT: vmulhu.vx v16, v8, a01058; RV64-V-NEXT: li a0, 611059; RV64-V-NEXT: vsrl.vx v16, v16, a01060; RV64-V-NEXT: li a0, -71061; RV64-V-NEXT: vnmsac.vx v8, a0, v161062; RV64-V-NEXT: ret1063 %vc = urem <vscale x 8 x i64> %va, splat (i64 -7)1064 ret <vscale x 8 x i64> %vc1065}1066 1067; fold (urem x, pow2) -> (and x, pow2-1)1068define <vscale x 8 x i64> @vremu_vi_nxv8i64_1(<vscale x 8 x i64> %va) {1069; CHECK-LABEL: vremu_vi_nxv8i64_1:1070; CHECK: # %bb.0:1071; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma1072; CHECK-NEXT: vand.vi v8, v8, 151073; CHECK-NEXT: ret1074 %vc = urem <vscale x 8 x i64> %va, splat (i64 16)1075 ret <vscale x 8 x i64> %vc1076}1077 1078; fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))1079define <vscale x 8 x i64> @vremu_vi_nxv8i64_2(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {1080; CHECK-LABEL: vremu_vi_nxv8i64_2:1081; CHECK: # %bb.0:1082; CHECK-NEXT: li a0, 161083; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1084; CHECK-NEXT: vmv.v.x v24, a01085; CHECK-NEXT: vsll.vv v16, v24, v161086; CHECK-NEXT: vadd.vi v16, v16, -11087; CHECK-NEXT: vand.vv v8, v8, v161088; CHECK-NEXT: ret1089 %vc = shl <vscale x 8 x i64> splat (i64 16), %vb1090 %vd = urem <vscale x 8 x i64> %va, %vc1091 ret <vscale x 8 x i64> %vd1092}1093