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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zfhmin,+zvfh,+zvfbfmin \3; RUN:   -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zfhmin,+zvfh,+zvfbfmin \5; RUN:   -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT:    vrgather.vv v10, v8, v912; CHECK-NEXT:    vmv1r.v v8, v1013; CHECK-NEXT:    ret14entry:15  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.nxv1i8.iXLen(16    <vscale x 1 x i8> poison,17    <vscale x 1 x i8> %0,18    <vscale x 1 x i8> %1,19    iXLen %2)20 21  ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:26; CHECK:       # %bb.0: # %entry27; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu28; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t29; CHECK-NEXT:    ret30entry:31  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vv.mask.nxv1i8.iXLen(32    <vscale x 1 x i8> %0,33    <vscale x 1 x i8> %1,34    <vscale x 1 x i8> %2,35    <vscale x 1 x i1> %3,36    iXLen %4, iXLen 1)37 38  ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:43; CHECK:       # %bb.0: # %entry44; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma45; CHECK-NEXT:    vrgather.vv v10, v8, v946; CHECK-NEXT:    vmv1r.v v8, v1047; CHECK-NEXT:    ret48entry:49  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.nxv2i8.iXLen(50    <vscale x 2 x i8> poison,51    <vscale x 2 x i8> %0,52    <vscale x 2 x i8> %1,53    iXLen %2)54 55  ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8:60; CHECK:       # %bb.0: # %entry61; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu62; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t63; CHECK-NEXT:    ret64entry:65  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vv.mask.nxv2i8.iXLen(66    <vscale x 2 x i8> %0,67    <vscale x 2 x i8> %1,68    <vscale x 2 x i8> %2,69    <vscale x 2 x i1> %3,70    iXLen %4, iXLen 1)71 72  ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:77; CHECK:       # %bb.0: # %entry78; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma79; CHECK-NEXT:    vrgather.vv v10, v8, v980; CHECK-NEXT:    vmv1r.v v8, v1081; CHECK-NEXT:    ret82entry:83  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.nxv4i8.iXLen(84    <vscale x 4 x i8> poison,85    <vscale x 4 x i8> %0,86    <vscale x 4 x i8> %1,87    iXLen %2)88 89  ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8:94; CHECK:       # %bb.0: # %entry95; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu96; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t97; CHECK-NEXT:    ret98entry:99  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vv.mask.nxv4i8.iXLen(100    <vscale x 4 x i8> %0,101    <vscale x 4 x i8> %1,102    <vscale x 4 x i8> %2,103    <vscale x 4 x i1> %3,104    iXLen %4, iXLen 1)105 106  ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:111; CHECK:       # %bb.0: # %entry112; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma113; CHECK-NEXT:    vrgather.vv v10, v8, v9114; CHECK-NEXT:    vmv.v.v v8, v10115; CHECK-NEXT:    ret116entry:117  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.nxv8i8.iXLen(118    <vscale x 8 x i8> poison,119    <vscale x 8 x i8> %0,120    <vscale x 8 x i8> %1,121    iXLen %2)122 123  ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8:128; CHECK:       # %bb.0: # %entry129; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu130; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t131; CHECK-NEXT:    ret132entry:133  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vv.mask.nxv8i8.iXLen(134    <vscale x 8 x i8> %0,135    <vscale x 8 x i8> %1,136    <vscale x 8 x i8> %2,137    <vscale x 8 x i1> %3,138    iXLen %4, iXLen 1)139 140  ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:145; CHECK:       # %bb.0: # %entry146; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma147; CHECK-NEXT:    vrgather.vv v12, v8, v10148; CHECK-NEXT:    vmv.v.v v8, v12149; CHECK-NEXT:    ret150entry:151  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.nxv16i8.iXLen(152    <vscale x 16 x i8> poison,153    <vscale x 16 x i8> %0,154    <vscale x 16 x i8> %1,155    iXLen %2)156 157  ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8:162; CHECK:       # %bb.0: # %entry163; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu164; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t165; CHECK-NEXT:    ret166entry:167  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vv.mask.nxv16i8.iXLen(168    <vscale x 16 x i8> %0,169    <vscale x 16 x i8> %1,170    <vscale x 16 x i8> %2,171    <vscale x 16 x i1> %3,172    iXLen %4, iXLen 1)173 174  ret <vscale x 16 x i8> %a175}176 177define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:179; CHECK:       # %bb.0: # %entry180; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma181; CHECK-NEXT:    vrgather.vv v16, v8, v12182; CHECK-NEXT:    vmv.v.v v8, v16183; CHECK-NEXT:    ret184entry:185  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.nxv32i8.iXLen(186    <vscale x 32 x i8> poison,187    <vscale x 32 x i8> %0,188    <vscale x 32 x i8> %1,189    iXLen %2)190 191  ret <vscale x 32 x i8> %a192}193 194define <vscale x 32 x i8> @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu198; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t199; CHECK-NEXT:    ret200entry:201  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vv.mask.nxv32i8.iXLen(202    <vscale x 32 x i8> %0,203    <vscale x 32 x i8> %1,204    <vscale x 32 x i8> %2,205    <vscale x 32 x i1> %3,206    iXLen %4, iXLen 1)207 208  ret <vscale x 32 x i8> %a209}210 211define <vscale x 64 x i8> @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8:213; CHECK:       # %bb.0: # %entry214; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma215; CHECK-NEXT:    vrgather.vv v24, v8, v16216; CHECK-NEXT:    vmv.v.v v8, v24217; CHECK-NEXT:    ret218entry:219  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.nxv64i8.iXLen(220    <vscale x 64 x i8> poison,221    <vscale x 64 x i8> %0,222    <vscale x 64 x i8> %1,223    iXLen %2)224 225  ret <vscale x 64 x i8> %a226}227 228define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:230; CHECK:       # %bb.0: # %entry231; CHECK-NEXT:    vl8r.v v24, (a0)232; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu233; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t234; CHECK-NEXT:    ret235entry:236  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vv.mask.nxv64i8.iXLen(237    <vscale x 64 x i8> %0,238    <vscale x 64 x i8> %1,239    <vscale x 64 x i8> %2,240    <vscale x 64 x i1> %3,241    iXLen %4, iXLen 1)242 243  ret <vscale x 64 x i8> %a244}245 246define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {247; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:248; CHECK:       # %bb.0: # %entry249; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma250; CHECK-NEXT:    vrgather.vv v10, v8, v9251; CHECK-NEXT:    vmv1r.v v8, v10252; CHECK-NEXT:    ret253entry:254  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.nxv1i16.iXLen(255    <vscale x 1 x i16> poison,256    <vscale x 1 x i16> %0,257    <vscale x 1 x i16> %1,258    iXLen %2)259 260  ret <vscale x 1 x i16> %a261}262 263define <vscale x 1 x i16> @intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {264; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16:265; CHECK:       # %bb.0: # %entry266; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu267; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t268; CHECK-NEXT:    ret269entry:270  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vv.mask.nxv1i16.iXLen(271    <vscale x 1 x i16> %0,272    <vscale x 1 x i16> %1,273    <vscale x 1 x i16> %2,274    <vscale x 1 x i1> %3,275    iXLen %4, iXLen 1)276 277  ret <vscale x 1 x i16> %a278}279 280define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {281; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:282; CHECK:       # %bb.0: # %entry283; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma284; CHECK-NEXT:    vrgather.vv v10, v8, v9285; CHECK-NEXT:    vmv1r.v v8, v10286; CHECK-NEXT:    ret287entry:288  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.nxv2i16.iXLen(289    <vscale x 2 x i16> poison,290    <vscale x 2 x i16> %0,291    <vscale x 2 x i16> %1,292    iXLen %2)293 294  ret <vscale x 2 x i16> %a295}296 297define <vscale x 2 x i16> @intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {298; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16:299; CHECK:       # %bb.0: # %entry300; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu301; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t302; CHECK-NEXT:    ret303entry:304  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vv.mask.nxv2i16.iXLen(305    <vscale x 2 x i16> %0,306    <vscale x 2 x i16> %1,307    <vscale x 2 x i16> %2,308    <vscale x 2 x i1> %3,309    iXLen %4, iXLen 1)310 311  ret <vscale x 2 x i16> %a312}313 314define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {315; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:316; CHECK:       # %bb.0: # %entry317; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma318; CHECK-NEXT:    vrgather.vv v10, v8, v9319; CHECK-NEXT:    vmv.v.v v8, v10320; CHECK-NEXT:    ret321entry:322  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.nxv4i16.iXLen(323    <vscale x 4 x i16> poison,324    <vscale x 4 x i16> %0,325    <vscale x 4 x i16> %1,326    iXLen %2)327 328  ret <vscale x 4 x i16> %a329}330 331define <vscale x 4 x i16> @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {332; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16:333; CHECK:       # %bb.0: # %entry334; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu335; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t336; CHECK-NEXT:    ret337entry:338  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vv.mask.nxv4i16.iXLen(339    <vscale x 4 x i16> %0,340    <vscale x 4 x i16> %1,341    <vscale x 4 x i16> %2,342    <vscale x 4 x i1> %3,343    iXLen %4, iXLen 1)344 345  ret <vscale x 4 x i16> %a346}347 348define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {349; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:350; CHECK:       # %bb.0: # %entry351; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma352; CHECK-NEXT:    vrgather.vv v12, v8, v10353; CHECK-NEXT:    vmv.v.v v8, v12354; CHECK-NEXT:    ret355entry:356  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.nxv8i16.iXLen(357    <vscale x 8 x i16> poison,358    <vscale x 8 x i16> %0,359    <vscale x 8 x i16> %1,360    iXLen %2)361 362  ret <vscale x 8 x i16> %a363}364 365define <vscale x 8 x i16> @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {366; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16:367; CHECK:       # %bb.0: # %entry368; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu369; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t370; CHECK-NEXT:    ret371entry:372  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vv.mask.nxv8i16.iXLen(373    <vscale x 8 x i16> %0,374    <vscale x 8 x i16> %1,375    <vscale x 8 x i16> %2,376    <vscale x 8 x i1> %3,377    iXLen %4, iXLen 1)378 379  ret <vscale x 8 x i16> %a380}381 382define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {383; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:384; CHECK:       # %bb.0: # %entry385; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma386; CHECK-NEXT:    vrgather.vv v16, v8, v12387; CHECK-NEXT:    vmv.v.v v8, v16388; CHECK-NEXT:    ret389entry:390  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.nxv16i16.iXLen(391    <vscale x 16 x i16> poison,392    <vscale x 16 x i16> %0,393    <vscale x 16 x i16> %1,394    iXLen %2)395 396  ret <vscale x 16 x i16> %a397}398 399define <vscale x 16 x i16> @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {400; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16:401; CHECK:       # %bb.0: # %entry402; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu403; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t404; CHECK-NEXT:    ret405entry:406  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vv.mask.nxv16i16.iXLen(407    <vscale x 16 x i16> %0,408    <vscale x 16 x i16> %1,409    <vscale x 16 x i16> %2,410    <vscale x 16 x i1> %3,411    iXLen %4, iXLen 1)412 413  ret <vscale x 16 x i16> %a414}415 416define <vscale x 32 x i16> @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {417; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16:418; CHECK:       # %bb.0: # %entry419; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma420; CHECK-NEXT:    vrgather.vv v24, v8, v16421; CHECK-NEXT:    vmv.v.v v8, v24422; CHECK-NEXT:    ret423entry:424  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.nxv32i16.iXLen(425    <vscale x 32 x i16> poison,426    <vscale x 32 x i16> %0,427    <vscale x 32 x i16> %1,428    iXLen %2)429 430  ret <vscale x 32 x i16> %a431}432 433define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {434; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:435; CHECK:       # %bb.0: # %entry436; CHECK-NEXT:    vl8re16.v v24, (a0)437; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu438; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t439; CHECK-NEXT:    ret440entry:441  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vv.mask.nxv32i16.iXLen(442    <vscale x 32 x i16> %0,443    <vscale x 32 x i16> %1,444    <vscale x 32 x i16> %2,445    <vscale x 32 x i1> %3,446    iXLen %4, iXLen 1)447 448  ret <vscale x 32 x i16> %a449}450 451define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {452; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:453; CHECK:       # %bb.0: # %entry454; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma455; CHECK-NEXT:    vrgather.vv v10, v8, v9456; CHECK-NEXT:    vmv1r.v v8, v10457; CHECK-NEXT:    ret458entry:459  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.nxv1i32.iXLen(460    <vscale x 1 x i32> poison,461    <vscale x 1 x i32> %0,462    <vscale x 1 x i32> %1,463    iXLen %2)464 465  ret <vscale x 1 x i32> %a466}467 468define <vscale x 1 x i32> @intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {469; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32:470; CHECK:       # %bb.0: # %entry471; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu472; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t473; CHECK-NEXT:    ret474entry:475  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vv.mask.nxv1i32.iXLen(476    <vscale x 1 x i32> %0,477    <vscale x 1 x i32> %1,478    <vscale x 1 x i32> %2,479    <vscale x 1 x i1> %3,480    iXLen %4, iXLen 1)481 482  ret <vscale x 1 x i32> %a483}484 485define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {486; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:487; CHECK:       # %bb.0: # %entry488; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma489; CHECK-NEXT:    vrgather.vv v10, v8, v9490; CHECK-NEXT:    vmv.v.v v8, v10491; CHECK-NEXT:    ret492entry:493  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.nxv2i32.iXLen(494    <vscale x 2 x i32> poison,495    <vscale x 2 x i32> %0,496    <vscale x 2 x i32> %1,497    iXLen %2)498 499  ret <vscale x 2 x i32> %a500}501 502define <vscale x 2 x i32> @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {503; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32:504; CHECK:       # %bb.0: # %entry505; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu506; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t507; CHECK-NEXT:    ret508entry:509  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vv.mask.nxv2i32.iXLen(510    <vscale x 2 x i32> %0,511    <vscale x 2 x i32> %1,512    <vscale x 2 x i32> %2,513    <vscale x 2 x i1> %3,514    iXLen %4, iXLen 1)515 516  ret <vscale x 2 x i32> %a517}518 519define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {520; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:521; CHECK:       # %bb.0: # %entry522; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma523; CHECK-NEXT:    vrgather.vv v12, v8, v10524; CHECK-NEXT:    vmv.v.v v8, v12525; CHECK-NEXT:    ret526entry:527  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32.iXLen(528    <vscale x 4 x i32> poison,529    <vscale x 4 x i32> %0,530    <vscale x 4 x i32> %1,531    iXLen %2)532 533  ret <vscale x 4 x i32> %a534}535 536define <vscale x 4 x i32> @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {537; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32:538; CHECK:       # %bb.0: # %entry539; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu540; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t541; CHECK-NEXT:    ret542entry:543  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.mask.nxv4i32.iXLen(544    <vscale x 4 x i32> %0,545    <vscale x 4 x i32> %1,546    <vscale x 4 x i32> %2,547    <vscale x 4 x i1> %3,548    iXLen %4, iXLen 1)549 550  ret <vscale x 4 x i32> %a551}552 553define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {554; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:555; CHECK:       # %bb.0: # %entry556; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma557; CHECK-NEXT:    vrgather.vv v16, v8, v12558; CHECK-NEXT:    vmv.v.v v8, v16559; CHECK-NEXT:    ret560entry:561  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.nxv8i32.iXLen(562    <vscale x 8 x i32> poison,563    <vscale x 8 x i32> %0,564    <vscale x 8 x i32> %1,565    iXLen %2)566 567  ret <vscale x 8 x i32> %a568}569 570define <vscale x 8 x i32> @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {571; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32:572; CHECK:       # %bb.0: # %entry573; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu574; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t575; CHECK-NEXT:    ret576entry:577  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vv.mask.nxv8i32.iXLen(578    <vscale x 8 x i32> %0,579    <vscale x 8 x i32> %1,580    <vscale x 8 x i32> %2,581    <vscale x 8 x i1> %3,582    iXLen %4, iXLen 1)583 584  ret <vscale x 8 x i32> %a585}586 587define <vscale x 16 x i32> @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {588; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32:589; CHECK:       # %bb.0: # %entry590; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma591; CHECK-NEXT:    vrgather.vv v24, v8, v16592; CHECK-NEXT:    vmv.v.v v8, v24593; CHECK-NEXT:    ret594entry:595  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.nxv16i32.iXLen(596    <vscale x 16 x i32> poison,597    <vscale x 16 x i32> %0,598    <vscale x 16 x i32> %1,599    iXLen %2)600 601  ret <vscale x 16 x i32> %a602}603 604define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {605; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:606; CHECK:       # %bb.0: # %entry607; CHECK-NEXT:    vl8re32.v v24, (a0)608; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu609; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t610; CHECK-NEXT:    ret611entry:612  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vv.mask.nxv16i32.iXLen(613    <vscale x 16 x i32> %0,614    <vscale x 16 x i32> %1,615    <vscale x 16 x i32> %2,616    <vscale x 16 x i1> %3,617    iXLen %4, iXLen 1)618 619  ret <vscale x 16 x i32> %a620}621 622define <vscale x 1 x i64> @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {623; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64:624; CHECK:       # %bb.0: # %entry625; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma626; CHECK-NEXT:    vrgather.vv v10, v8, v9627; CHECK-NEXT:    vmv.v.v v8, v10628; CHECK-NEXT:    ret629entry:630  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.nxv1i64.iXLen(631    <vscale x 1 x i64> poison,632    <vscale x 1 x i64> %0,633    <vscale x 1 x i64> %1,634    iXLen %2)635 636  ret <vscale x 1 x i64> %a637}638 639define <vscale x 1 x i64> @intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {640; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64:641; CHECK:       # %bb.0: # %entry642; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu643; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t644; CHECK-NEXT:    ret645entry:646  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vv.mask.nxv1i64.iXLen(647    <vscale x 1 x i64> %0,648    <vscale x 1 x i64> %1,649    <vscale x 1 x i64> %2,650    <vscale x 1 x i1> %3,651    iXLen %4, iXLen 1)652 653  ret <vscale x 1 x i64> %a654}655 656define <vscale x 2 x i64> @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {657; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64:658; CHECK:       # %bb.0: # %entry659; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma660; CHECK-NEXT:    vrgather.vv v12, v8, v10661; CHECK-NEXT:    vmv.v.v v8, v12662; CHECK-NEXT:    ret663entry:664  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.nxv2i64.iXLen(665    <vscale x 2 x i64> poison,666    <vscale x 2 x i64> %0,667    <vscale x 2 x i64> %1,668    iXLen %2)669 670  ret <vscale x 2 x i64> %a671}672 673define <vscale x 2 x i64> @intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {674; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64:675; CHECK:       # %bb.0: # %entry676; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu677; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t678; CHECK-NEXT:    ret679entry:680  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vv.mask.nxv2i64.iXLen(681    <vscale x 2 x i64> %0,682    <vscale x 2 x i64> %1,683    <vscale x 2 x i64> %2,684    <vscale x 2 x i1> %3,685    iXLen %4, iXLen 1)686 687  ret <vscale x 2 x i64> %a688}689 690define <vscale x 4 x i64> @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {691; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64:692; CHECK:       # %bb.0: # %entry693; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma694; CHECK-NEXT:    vrgather.vv v16, v8, v12695; CHECK-NEXT:    vmv.v.v v8, v16696; CHECK-NEXT:    ret697entry:698  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.nxv4i64.iXLen(699    <vscale x 4 x i64> poison,700    <vscale x 4 x i64> %0,701    <vscale x 4 x i64> %1,702    iXLen %2)703 704  ret <vscale x 4 x i64> %a705}706 707define <vscale x 4 x i64> @intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {708; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64:709; CHECK:       # %bb.0: # %entry710; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu711; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t712; CHECK-NEXT:    ret713entry:714  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vv.mask.nxv4i64.iXLen(715    <vscale x 4 x i64> %0,716    <vscale x 4 x i64> %1,717    <vscale x 4 x i64> %2,718    <vscale x 4 x i1> %3,719    iXLen %4, iXLen 1)720 721  ret <vscale x 4 x i64> %a722}723 724define <vscale x 8 x i64> @intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {725; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64:726; CHECK:       # %bb.0: # %entry727; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma728; CHECK-NEXT:    vrgather.vv v24, v8, v16729; CHECK-NEXT:    vmv.v.v v8, v24730; CHECK-NEXT:    ret731entry:732  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.nxv8i64.iXLen(733    <vscale x 8 x i64> poison,734    <vscale x 8 x i64> %0,735    <vscale x 8 x i64> %1,736    iXLen %2)737 738  ret <vscale x 8 x i64> %a739}740 741define <vscale x 8 x i64> @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {742; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64:743; CHECK:       # %bb.0: # %entry744; CHECK-NEXT:    vl8re64.v v24, (a0)745; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu746; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t747; CHECK-NEXT:    ret748entry:749  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vv.mask.nxv8i64.iXLen(750    <vscale x 8 x i64> %0,751    <vscale x 8 x i64> %1,752    <vscale x 8 x i64> %2,753    <vscale x 8 x i1> %3,754    iXLen %4, iXLen 1)755 756  ret <vscale x 8 x i64> %a757}758 759define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {760; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:761; CHECK:       # %bb.0: # %entry762; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma763; CHECK-NEXT:    vrgather.vv v10, v8, v9764; CHECK-NEXT:    vmv1r.v v8, v10765; CHECK-NEXT:    ret766entry:767  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.nxv1f16.iXLen(768    <vscale x 1 x half> poison,769    <vscale x 1 x half> %0,770    <vscale x 1 x i16> %1,771    iXLen %2)772 773  ret <vscale x 1 x half> %a774}775 776define <vscale x 1 x half> @intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {777; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16:778; CHECK:       # %bb.0: # %entry779; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu780; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t781; CHECK-NEXT:    ret782entry:783  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vv.mask.nxv1f16.iXLen(784    <vscale x 1 x half> %0,785    <vscale x 1 x half> %1,786    <vscale x 1 x i16> %2,787    <vscale x 1 x i1> %3,788    iXLen %4, iXLen 1)789 790  ret <vscale x 1 x half> %a791}792 793define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {794; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:795; CHECK:       # %bb.0: # %entry796; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma797; CHECK-NEXT:    vrgather.vv v10, v8, v9798; CHECK-NEXT:    vmv1r.v v8, v10799; CHECK-NEXT:    ret800entry:801  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.nxv2f16.iXLen(802    <vscale x 2 x half> poison,803    <vscale x 2 x half> %0,804    <vscale x 2 x i16> %1,805    iXLen %2)806 807  ret <vscale x 2 x half> %a808}809 810define <vscale x 2 x half> @intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {811; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16:812; CHECK:       # %bb.0: # %entry813; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu814; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t815; CHECK-NEXT:    ret816entry:817  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vv.mask.nxv2f16.iXLen(818    <vscale x 2 x half> %0,819    <vscale x 2 x half> %1,820    <vscale x 2 x i16> %2,821    <vscale x 2 x i1> %3,822    iXLen %4, iXLen 1)823 824  ret <vscale x 2 x half> %a825}826 827define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {828; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:829; CHECK:       # %bb.0: # %entry830; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma831; CHECK-NEXT:    vrgather.vv v10, v8, v9832; CHECK-NEXT:    vmv.v.v v8, v10833; CHECK-NEXT:    ret834entry:835  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.nxv4f16.iXLen(836    <vscale x 4 x half> poison,837    <vscale x 4 x half> %0,838    <vscale x 4 x i16> %1,839    iXLen %2)840 841  ret <vscale x 4 x half> %a842}843 844define <vscale x 4 x half> @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {845; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16:846; CHECK:       # %bb.0: # %entry847; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu848; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t849; CHECK-NEXT:    ret850entry:851  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vv.mask.nxv4f16.iXLen(852    <vscale x 4 x half> %0,853    <vscale x 4 x half> %1,854    <vscale x 4 x i16> %2,855    <vscale x 4 x i1> %3,856    iXLen %4, iXLen 1)857 858  ret <vscale x 4 x half> %a859}860 861define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {862; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:863; CHECK:       # %bb.0: # %entry864; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma865; CHECK-NEXT:    vrgather.vv v12, v8, v10866; CHECK-NEXT:    vmv.v.v v8, v12867; CHECK-NEXT:    ret868entry:869  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.nxv8f16.iXLen(870    <vscale x 8 x half> poison,871    <vscale x 8 x half> %0,872    <vscale x 8 x i16> %1,873    iXLen %2)874 875  ret <vscale x 8 x half> %a876}877 878define <vscale x 8 x half> @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {879; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16:880; CHECK:       # %bb.0: # %entry881; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu882; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t883; CHECK-NEXT:    ret884entry:885  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vv.mask.nxv8f16.iXLen(886    <vscale x 8 x half> %0,887    <vscale x 8 x half> %1,888    <vscale x 8 x i16> %2,889    <vscale x 8 x i1> %3,890    iXLen %4, iXLen 1)891 892  ret <vscale x 8 x half> %a893}894 895define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {896; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:897; CHECK:       # %bb.0: # %entry898; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma899; CHECK-NEXT:    vrgather.vv v16, v8, v12900; CHECK-NEXT:    vmv.v.v v8, v16901; CHECK-NEXT:    ret902entry:903  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.nxv16f16.iXLen(904    <vscale x 16 x half> poison,905    <vscale x 16 x half> %0,906    <vscale x 16 x i16> %1,907    iXLen %2)908 909  ret <vscale x 16 x half> %a910}911 912define <vscale x 16 x half> @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {913; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16:914; CHECK:       # %bb.0: # %entry915; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu916; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t917; CHECK-NEXT:    ret918entry:919  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vv.mask.nxv16f16.iXLen(920    <vscale x 16 x half> %0,921    <vscale x 16 x half> %1,922    <vscale x 16 x i16> %2,923    <vscale x 16 x i1> %3,924    iXLen %4, iXLen 1)925 926  ret <vscale x 16 x half> %a927}928 929define <vscale x 32 x half> @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {930; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16:931; CHECK:       # %bb.0: # %entry932; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma933; CHECK-NEXT:    vrgather.vv v24, v8, v16934; CHECK-NEXT:    vmv.v.v v8, v24935; CHECK-NEXT:    ret936entry:937  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vv.nxv32f16.iXLen(938    <vscale x 32 x half> poison,939    <vscale x 32 x half> %0,940    <vscale x 32 x i16> %1,941    iXLen %2)942 943  ret <vscale x 32 x half> %a944}945 946define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {947; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:948; CHECK:       # %bb.0: # %entry949; CHECK-NEXT:    vl8re16.v v24, (a0)950; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu951; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t952; CHECK-NEXT:    ret953entry:954  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vv.mask.nxv32f16.iXLen(955    <vscale x 32 x half> %0,956    <vscale x 32 x half> %1,957    <vscale x 32 x i16> %2,958    <vscale x 32 x i1> %3,959    iXLen %4, iXLen 1)960 961  ret <vscale x 32 x half> %a962}963 964define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {965; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:966; CHECK:       # %bb.0: # %entry967; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma968; CHECK-NEXT:    vrgather.vv v10, v8, v9969; CHECK-NEXT:    vmv1r.v v8, v10970; CHECK-NEXT:    ret971entry:972  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.nxv1f32.iXLen(973    <vscale x 1 x float> poison,974    <vscale x 1 x float> %0,975    <vscale x 1 x i32> %1,976    iXLen %2)977 978  ret <vscale x 1 x float> %a979}980 981define <vscale x 1 x float> @intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {982; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32:983; CHECK:       # %bb.0: # %entry984; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu985; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t986; CHECK-NEXT:    ret987entry:988  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vv.mask.nxv1f32.iXLen(989    <vscale x 1 x float> %0,990    <vscale x 1 x float> %1,991    <vscale x 1 x i32> %2,992    <vscale x 1 x i1> %3,993    iXLen %4, iXLen 1)994 995  ret <vscale x 1 x float> %a996}997 998define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {999; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:1000; CHECK:       # %bb.0: # %entry1001; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1002; CHECK-NEXT:    vrgather.vv v10, v8, v91003; CHECK-NEXT:    vmv.v.v v8, v101004; CHECK-NEXT:    ret1005entry:1006  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.nxv2f32.iXLen(1007    <vscale x 2 x float> poison,1008    <vscale x 2 x float> %0,1009    <vscale x 2 x i32> %1,1010    iXLen %2)1011 1012  ret <vscale x 2 x float> %a1013}1014 1015define <vscale x 2 x float> @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1016; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32:1017; CHECK:       # %bb.0: # %entry1018; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu1019; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t1020; CHECK-NEXT:    ret1021entry:1022  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vv.mask.nxv2f32.iXLen(1023    <vscale x 2 x float> %0,1024    <vscale x 2 x float> %1,1025    <vscale x 2 x i32> %2,1026    <vscale x 2 x i1> %3,1027    iXLen %4, iXLen 1)1028 1029  ret <vscale x 2 x float> %a1030}1031 1032define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {1033; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:1034; CHECK:       # %bb.0: # %entry1035; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1036; CHECK-NEXT:    vrgather.vv v12, v8, v101037; CHECK-NEXT:    vmv.v.v v8, v121038; CHECK-NEXT:    ret1039entry:1040  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.nxv4f32.iXLen(1041    <vscale x 4 x float> poison,1042    <vscale x 4 x float> %0,1043    <vscale x 4 x i32> %1,1044    iXLen %2)1045 1046  ret <vscale x 4 x float> %a1047}1048 1049define <vscale x 4 x float> @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1050; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32:1051; CHECK:       # %bb.0: # %entry1052; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu1053; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t1054; CHECK-NEXT:    ret1055entry:1056  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vv.mask.nxv4f32.iXLen(1057    <vscale x 4 x float> %0,1058    <vscale x 4 x float> %1,1059    <vscale x 4 x i32> %2,1060    <vscale x 4 x i1> %3,1061    iXLen %4, iXLen 1)1062 1063  ret <vscale x 4 x float> %a1064}1065 1066define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {1067; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:1068; CHECK:       # %bb.0: # %entry1069; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1070; CHECK-NEXT:    vrgather.vv v16, v8, v121071; CHECK-NEXT:    vmv.v.v v8, v161072; CHECK-NEXT:    ret1073entry:1074  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.nxv8f32.iXLen(1075    <vscale x 8 x float> poison,1076    <vscale x 8 x float> %0,1077    <vscale x 8 x i32> %1,1078    iXLen %2)1079 1080  ret <vscale x 8 x float> %a1081}1082 1083define <vscale x 8 x float> @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1084; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32:1085; CHECK:       # %bb.0: # %entry1086; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu1087; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t1088; CHECK-NEXT:    ret1089entry:1090  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vv.mask.nxv8f32.iXLen(1091    <vscale x 8 x float> %0,1092    <vscale x 8 x float> %1,1093    <vscale x 8 x i32> %2,1094    <vscale x 8 x i1> %3,1095    iXLen %4, iXLen 1)1096 1097  ret <vscale x 8 x float> %a1098}1099 1100define <vscale x 16 x float> @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {1101; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32:1102; CHECK:       # %bb.0: # %entry1103; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1104; CHECK-NEXT:    vrgather.vv v24, v8, v161105; CHECK-NEXT:    vmv.v.v v8, v241106; CHECK-NEXT:    ret1107entry:1108  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.nxv16f32.iXLen(1109    <vscale x 16 x float> poison,1110    <vscale x 16 x float> %0,1111    <vscale x 16 x i32> %1,1112    iXLen %2)1113 1114  ret <vscale x 16 x float> %a1115}1116 1117define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1118; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:1119; CHECK:       # %bb.0: # %entry1120; CHECK-NEXT:    vl8re32.v v24, (a0)1121; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1122; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t1123; CHECK-NEXT:    ret1124entry:1125  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vv.mask.nxv16f32.iXLen(1126    <vscale x 16 x float> %0,1127    <vscale x 16 x float> %1,1128    <vscale x 16 x i32> %2,1129    <vscale x 16 x i1> %3,1130    iXLen %4, iXLen 1)1131 1132  ret <vscale x 16 x float> %a1133}1134 1135define <vscale x 1 x double> @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {1136; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64:1137; CHECK:       # %bb.0: # %entry1138; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1139; CHECK-NEXT:    vrgather.vv v10, v8, v91140; CHECK-NEXT:    vmv.v.v v8, v101141; CHECK-NEXT:    ret1142entry:1143  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.nxv1f64.iXLen(1144    <vscale x 1 x double> poison,1145    <vscale x 1 x double> %0,1146    <vscale x 1 x i64> %1,1147    iXLen %2)1148 1149  ret <vscale x 1 x double> %a1150}1151 1152define <vscale x 1 x double> @intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1153; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64:1154; CHECK:       # %bb.0: # %entry1155; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu1156; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t1157; CHECK-NEXT:    ret1158entry:1159  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vv.mask.nxv1f64.iXLen(1160    <vscale x 1 x double> %0,1161    <vscale x 1 x double> %1,1162    <vscale x 1 x i64> %2,1163    <vscale x 1 x i1> %3,1164    iXLen %4, iXLen 1)1165 1166  ret <vscale x 1 x double> %a1167}1168 1169define <vscale x 2 x double> @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {1170; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64:1171; CHECK:       # %bb.0: # %entry1172; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1173; CHECK-NEXT:    vrgather.vv v12, v8, v101174; CHECK-NEXT:    vmv.v.v v8, v121175; CHECK-NEXT:    ret1176entry:1177  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.nxv2f64.iXLen(1178    <vscale x 2 x double> poison,1179    <vscale x 2 x double> %0,1180    <vscale x 2 x i64> %1,1181    iXLen %2)1182 1183  ret <vscale x 2 x double> %a1184}1185 1186define <vscale x 2 x double> @intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1187; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64:1188; CHECK:       # %bb.0: # %entry1189; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu1190; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t1191; CHECK-NEXT:    ret1192entry:1193  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vv.mask.nxv2f64.iXLen(1194    <vscale x 2 x double> %0,1195    <vscale x 2 x double> %1,1196    <vscale x 2 x i64> %2,1197    <vscale x 2 x i1> %3,1198    iXLen %4, iXLen 1)1199 1200  ret <vscale x 2 x double> %a1201}1202 1203define <vscale x 4 x double> @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {1204; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64:1205; CHECK:       # %bb.0: # %entry1206; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1207; CHECK-NEXT:    vrgather.vv v16, v8, v121208; CHECK-NEXT:    vmv.v.v v8, v161209; CHECK-NEXT:    ret1210entry:1211  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.nxv4f64.iXLen(1212    <vscale x 4 x double> poison,1213    <vscale x 4 x double> %0,1214    <vscale x 4 x i64> %1,1215    iXLen %2)1216 1217  ret <vscale x 4 x double> %a1218}1219 1220define <vscale x 4 x double> @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1221; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64:1222; CHECK:       # %bb.0: # %entry1223; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu1224; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t1225; CHECK-NEXT:    ret1226entry:1227  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vv.mask.nxv4f64.iXLen(1228    <vscale x 4 x double> %0,1229    <vscale x 4 x double> %1,1230    <vscale x 4 x i64> %2,1231    <vscale x 4 x i1> %3,1232    iXLen %4, iXLen 1)1233 1234  ret <vscale x 4 x double> %a1235}1236 1237define <vscale x 8 x double> @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {1238; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64:1239; CHECK:       # %bb.0: # %entry1240; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1241; CHECK-NEXT:    vrgather.vv v24, v8, v161242; CHECK-NEXT:    vmv.v.v v8, v241243; CHECK-NEXT:    ret1244entry:1245  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.nxv8f64.iXLen(1246    <vscale x 8 x double> poison,1247    <vscale x 8 x double> %0,1248    <vscale x 8 x i64> %1,1249    iXLen %2)1250 1251  ret <vscale x 8 x double> %a1252}1253 1254define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1255; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64:1256; CHECK:       # %bb.0: # %entry1257; CHECK-NEXT:    vl8re64.v v24, (a0)1258; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu1259; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t1260; CHECK-NEXT:    ret1261entry:1262  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vv.mask.nxv8f64.iXLen(1263    <vscale x 8 x double> %0,1264    <vscale x 8 x double> %1,1265    <vscale x 8 x i64> %2,1266    <vscale x 8 x i1> %3,1267    iXLen %4, iXLen 1)1268 1269  ret <vscale x 8 x double> %a1270}1271 1272define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1, iXLen %2) nounwind {1273; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8:1274; CHECK:       # %bb.0: # %entry1275; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma1276; CHECK-NEXT:    vrgather.vx v9, v8, a01277; CHECK-NEXT:    vmv1r.v v8, v91278; CHECK-NEXT:    ret1279entry:1280  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.iXLen(1281    <vscale x 1 x i8> poison,1282    <vscale x 1 x i8> %0,1283    iXLen %1,1284    iXLen %2)1285 1286  ret <vscale x 1 x i8> %a1287}1288 1289define <vscale x 1 x i8> @intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1290; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8:1291; CHECK:       # %bb.0: # %entry1292; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu1293; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1294; CHECK-NEXT:    ret1295entry:1296  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.iXLen(1297    <vscale x 1 x i8> %0,1298    <vscale x 1 x i8> %1,1299    iXLen %2,1300    <vscale x 1 x i1> %3,1301    iXLen %4, iXLen 1)1302 1303  ret <vscale x 1 x i8> %a1304}1305 1306define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, iXLen %1, iXLen %2) nounwind {1307; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8:1308; CHECK:       # %bb.0: # %entry1309; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma1310; CHECK-NEXT:    vrgather.vx v9, v8, a01311; CHECK-NEXT:    vmv1r.v v8, v91312; CHECK-NEXT:    ret1313entry:1314  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.iXLen(1315    <vscale x 2 x i8> poison,1316    <vscale x 2 x i8> %0,1317    iXLen %1,1318    iXLen %2)1319 1320  ret <vscale x 2 x i8> %a1321}1322 1323define <vscale x 2 x i8> @intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1324; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8:1325; CHECK:       # %bb.0: # %entry1326; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu1327; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1328; CHECK-NEXT:    ret1329entry:1330  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.iXLen(1331    <vscale x 2 x i8> %0,1332    <vscale x 2 x i8> %1,1333    iXLen %2,1334    <vscale x 2 x i1> %3,1335    iXLen %4, iXLen 1)1336 1337  ret <vscale x 2 x i8> %a1338}1339 1340define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, iXLen %1, iXLen %2) nounwind {1341; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8:1342; CHECK:       # %bb.0: # %entry1343; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma1344; CHECK-NEXT:    vrgather.vx v9, v8, a01345; CHECK-NEXT:    vmv1r.v v8, v91346; CHECK-NEXT:    ret1347entry:1348  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.iXLen(1349    <vscale x 4 x i8> poison,1350    <vscale x 4 x i8> %0,1351    iXLen %1,1352    iXLen %2)1353 1354  ret <vscale x 4 x i8> %a1355}1356 1357define <vscale x 4 x i8> @intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1358; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8:1359; CHECK:       # %bb.0: # %entry1360; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, mu1361; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1362; CHECK-NEXT:    ret1363entry:1364  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.iXLen(1365    <vscale x 4 x i8> %0,1366    <vscale x 4 x i8> %1,1367    iXLen %2,1368    <vscale x 4 x i1> %3,1369    iXLen %4, iXLen 1)1370 1371  ret <vscale x 4 x i8> %a1372}1373 1374define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, iXLen %1, iXLen %2) nounwind {1375; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8:1376; CHECK:       # %bb.0: # %entry1377; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma1378; CHECK-NEXT:    vrgather.vx v9, v8, a01379; CHECK-NEXT:    vmv.v.v v8, v91380; CHECK-NEXT:    ret1381entry:1382  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.iXLen(1383    <vscale x 8 x i8> poison,1384    <vscale x 8 x i8> %0,1385    iXLen %1,1386    iXLen %2)1387 1388  ret <vscale x 8 x i8> %a1389}1390 1391define <vscale x 8 x i8> @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1392; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8:1393; CHECK:       # %bb.0: # %entry1394; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu1395; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1396; CHECK-NEXT:    ret1397entry:1398  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.iXLen(1399    <vscale x 8 x i8> %0,1400    <vscale x 8 x i8> %1,1401    iXLen %2,1402    <vscale x 8 x i1> %3,1403    iXLen %4, iXLen 1)1404 1405  ret <vscale x 8 x i8> %a1406}1407 1408define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, iXLen %1, iXLen %2) nounwind {1409; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8:1410; CHECK:       # %bb.0: # %entry1411; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma1412; CHECK-NEXT:    vrgather.vx v10, v8, a01413; CHECK-NEXT:    vmv.v.v v8, v101414; CHECK-NEXT:    ret1415entry:1416  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.iXLen(1417    <vscale x 16 x i8> poison,1418    <vscale x 16 x i8> %0,1419    iXLen %1,1420    iXLen %2)1421 1422  ret <vscale x 16 x i8> %a1423}1424 1425define <vscale x 16 x i8> @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1426; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8:1427; CHECK:       # %bb.0: # %entry1428; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, mu1429; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t1430; CHECK-NEXT:    ret1431entry:1432  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.iXLen(1433    <vscale x 16 x i8> %0,1434    <vscale x 16 x i8> %1,1435    iXLen %2,1436    <vscale x 16 x i1> %3,1437    iXLen %4, iXLen 1)1438 1439  ret <vscale x 16 x i8> %a1440}1441 1442define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, iXLen %1, iXLen %2) nounwind {1443; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8:1444; CHECK:       # %bb.0: # %entry1445; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma1446; CHECK-NEXT:    vrgather.vx v12, v8, a01447; CHECK-NEXT:    vmv.v.v v8, v121448; CHECK-NEXT:    ret1449entry:1450  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.iXLen(1451    <vscale x 32 x i8> poison,1452    <vscale x 32 x i8> %0,1453    iXLen %1,1454    iXLen %2)1455 1456  ret <vscale x 32 x i8> %a1457}1458 1459define <vscale x 32 x i8> @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1460; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8:1461; CHECK:       # %bb.0: # %entry1462; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, mu1463; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t1464; CHECK-NEXT:    ret1465entry:1466  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.iXLen(1467    <vscale x 32 x i8> %0,1468    <vscale x 32 x i8> %1,1469    iXLen %2,1470    <vscale x 32 x i1> %3,1471    iXLen %4, iXLen 1)1472 1473  ret <vscale x 32 x i8> %a1474}1475 1476define <vscale x 64 x i8> @intrinsic_vrgather_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, iXLen %1, iXLen %2) nounwind {1477; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8:1478; CHECK:       # %bb.0: # %entry1479; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma1480; CHECK-NEXT:    vrgather.vx v16, v8, a01481; CHECK-NEXT:    vmv.v.v v8, v161482; CHECK-NEXT:    ret1483entry:1484  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.iXLen(1485    <vscale x 64 x i8> poison,1486    <vscale x 64 x i8> %0,1487    iXLen %1,1488    iXLen %2)1489 1490  ret <vscale x 64 x i8> %a1491}1492 1493define <vscale x 64 x i8> @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {1494; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8:1495; CHECK:       # %bb.0: # %entry1496; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, mu1497; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t1498; CHECK-NEXT:    ret1499entry:1500  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.iXLen(1501    <vscale x 64 x i8> %0,1502    <vscale x 64 x i8> %1,1503    iXLen %2,1504    <vscale x 64 x i1> %3,1505    iXLen %4, iXLen 1)1506 1507  ret <vscale x 64 x i8> %a1508}1509 1510define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1, iXLen %2) nounwind {1511; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16:1512; CHECK:       # %bb.0: # %entry1513; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1514; CHECK-NEXT:    vrgather.vx v9, v8, a01515; CHECK-NEXT:    vmv1r.v v8, v91516; CHECK-NEXT:    ret1517entry:1518  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.iXLen(1519    <vscale x 1 x i16> poison,1520    <vscale x 1 x i16> %0,1521    iXLen %1,1522    iXLen %2)1523 1524  ret <vscale x 1 x i16> %a1525}1526 1527define <vscale x 1 x i16> @intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1528; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16:1529; CHECK:       # %bb.0: # %entry1530; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu1531; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1532; CHECK-NEXT:    ret1533entry:1534  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.iXLen(1535    <vscale x 1 x i16> %0,1536    <vscale x 1 x i16> %1,1537    iXLen %2,1538    <vscale x 1 x i1> %3,1539    iXLen %4, iXLen 1)1540 1541  ret <vscale x 1 x i16> %a1542}1543 1544define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1, iXLen %2) nounwind {1545; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16:1546; CHECK:       # %bb.0: # %entry1547; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1548; CHECK-NEXT:    vrgather.vx v9, v8, a01549; CHECK-NEXT:    vmv1r.v v8, v91550; CHECK-NEXT:    ret1551entry:1552  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.iXLen(1553    <vscale x 2 x i16> poison,1554    <vscale x 2 x i16> %0,1555    iXLen %1,1556    iXLen %2)1557 1558  ret <vscale x 2 x i16> %a1559}1560 1561define <vscale x 2 x i16> @intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1562; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16:1563; CHECK:       # %bb.0: # %entry1564; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu1565; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1566; CHECK-NEXT:    ret1567entry:1568  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.iXLen(1569    <vscale x 2 x i16> %0,1570    <vscale x 2 x i16> %1,1571    iXLen %2,1572    <vscale x 2 x i1> %3,1573    iXLen %4, iXLen 1)1574 1575  ret <vscale x 2 x i16> %a1576}1577 1578define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1, iXLen %2) nounwind {1579; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16:1580; CHECK:       # %bb.0: # %entry1581; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1582; CHECK-NEXT:    vrgather.vx v9, v8, a01583; CHECK-NEXT:    vmv.v.v v8, v91584; CHECK-NEXT:    ret1585entry:1586  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.iXLen(1587    <vscale x 4 x i16> poison,1588    <vscale x 4 x i16> %0,1589    iXLen %1,1590    iXLen %2)1591 1592  ret <vscale x 4 x i16> %a1593}1594 1595define <vscale x 4 x i16> @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1596; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16:1597; CHECK:       # %bb.0: # %entry1598; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu1599; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1600; CHECK-NEXT:    ret1601entry:1602  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.iXLen(1603    <vscale x 4 x i16> %0,1604    <vscale x 4 x i16> %1,1605    iXLen %2,1606    <vscale x 4 x i1> %3,1607    iXLen %4, iXLen 1)1608 1609  ret <vscale x 4 x i16> %a1610}1611 1612define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1, iXLen %2) nounwind {1613; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16:1614; CHECK:       # %bb.0: # %entry1615; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1616; CHECK-NEXT:    vrgather.vx v10, v8, a01617; CHECK-NEXT:    vmv.v.v v8, v101618; CHECK-NEXT:    ret1619entry:1620  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.iXLen(1621    <vscale x 8 x i16> poison,1622    <vscale x 8 x i16> %0,1623    iXLen %1,1624    iXLen %2)1625 1626  ret <vscale x 8 x i16> %a1627}1628 1629define <vscale x 8 x i16> @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1630; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16:1631; CHECK:       # %bb.0: # %entry1632; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu1633; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t1634; CHECK-NEXT:    ret1635entry:1636  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.iXLen(1637    <vscale x 8 x i16> %0,1638    <vscale x 8 x i16> %1,1639    iXLen %2,1640    <vscale x 8 x i1> %3,1641    iXLen %4, iXLen 1)1642 1643  ret <vscale x 8 x i16> %a1644}1645 1646define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1, iXLen %2) nounwind {1647; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16:1648; CHECK:       # %bb.0: # %entry1649; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1650; CHECK-NEXT:    vrgather.vx v12, v8, a01651; CHECK-NEXT:    vmv.v.v v8, v121652; CHECK-NEXT:    ret1653entry:1654  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.iXLen(1655    <vscale x 16 x i16> poison,1656    <vscale x 16 x i16> %0,1657    iXLen %1,1658    iXLen %2)1659 1660  ret <vscale x 16 x i16> %a1661}1662 1663define <vscale x 16 x i16> @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1664; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16:1665; CHECK:       # %bb.0: # %entry1666; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu1667; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t1668; CHECK-NEXT:    ret1669entry:1670  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.iXLen(1671    <vscale x 16 x i16> %0,1672    <vscale x 16 x i16> %1,1673    iXLen %2,1674    <vscale x 16 x i1> %3,1675    iXLen %4, iXLen 1)1676 1677  ret <vscale x 16 x i16> %a1678}1679 1680define <vscale x 32 x i16> @intrinsic_vrgather_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1, iXLen %2) nounwind {1681; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16:1682; CHECK:       # %bb.0: # %entry1683; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma1684; CHECK-NEXT:    vrgather.vx v16, v8, a01685; CHECK-NEXT:    vmv.v.v v8, v161686; CHECK-NEXT:    ret1687entry:1688  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.iXLen(1689    <vscale x 32 x i16> poison,1690    <vscale x 32 x i16> %0,1691    iXLen %1,1692    iXLen %2)1693 1694  ret <vscale x 32 x i16> %a1695}1696 1697define <vscale x 32 x i16> @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1698; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16:1699; CHECK:       # %bb.0: # %entry1700; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu1701; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t1702; CHECK-NEXT:    ret1703entry:1704  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.iXLen(1705    <vscale x 32 x i16> %0,1706    <vscale x 32 x i16> %1,1707    iXLen %2,1708    <vscale x 32 x i1> %3,1709    iXLen %4, iXLen 1)1710 1711  ret <vscale x 32 x i16> %a1712}1713 1714define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1, iXLen %2) nounwind {1715; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32:1716; CHECK:       # %bb.0: # %entry1717; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1718; CHECK-NEXT:    vrgather.vx v9, v8, a01719; CHECK-NEXT:    vmv1r.v v8, v91720; CHECK-NEXT:    ret1721entry:1722  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.iXLen(1723    <vscale x 1 x i32> poison,1724    <vscale x 1 x i32> %0,1725    iXLen %1,1726    iXLen %2)1727 1728  ret <vscale x 1 x i32> %a1729}1730 1731define <vscale x 1 x i32> @intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1732; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32:1733; CHECK:       # %bb.0: # %entry1734; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu1735; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1736; CHECK-NEXT:    ret1737entry:1738  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.iXLen(1739    <vscale x 1 x i32> %0,1740    <vscale x 1 x i32> %1,1741    iXLen %2,1742    <vscale x 1 x i1> %3,1743    iXLen %4, iXLen 1)1744 1745  ret <vscale x 1 x i32> %a1746}1747 1748define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1, iXLen %2) nounwind {1749; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32:1750; CHECK:       # %bb.0: # %entry1751; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1752; CHECK-NEXT:    vrgather.vx v9, v8, a01753; CHECK-NEXT:    vmv.v.v v8, v91754; CHECK-NEXT:    ret1755entry:1756  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.iXLen(1757    <vscale x 2 x i32> poison,1758    <vscale x 2 x i32> %0,1759    iXLen %1,1760    iXLen %2)1761 1762  ret <vscale x 2 x i32> %a1763}1764 1765define <vscale x 2 x i32> @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1766; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32:1767; CHECK:       # %bb.0: # %entry1768; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu1769; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1770; CHECK-NEXT:    ret1771entry:1772  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.iXLen(1773    <vscale x 2 x i32> %0,1774    <vscale x 2 x i32> %1,1775    iXLen %2,1776    <vscale x 2 x i1> %3,1777    iXLen %4, iXLen 1)1778 1779  ret <vscale x 2 x i32> %a1780}1781 1782define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1, iXLen %2) nounwind {1783; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32:1784; CHECK:       # %bb.0: # %entry1785; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1786; CHECK-NEXT:    vrgather.vx v10, v8, a01787; CHECK-NEXT:    vmv.v.v v8, v101788; CHECK-NEXT:    ret1789entry:1790  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(1791    <vscale x 4 x i32> poison,1792    <vscale x 4 x i32> %0,1793    iXLen %1,1794    iXLen %2)1795 1796  ret <vscale x 4 x i32> %a1797}1798 1799define <vscale x 4 x i32> @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1800; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32:1801; CHECK:       # %bb.0: # %entry1802; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu1803; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t1804; CHECK-NEXT:    ret1805entry:1806  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.iXLen(1807    <vscale x 4 x i32> %0,1808    <vscale x 4 x i32> %1,1809    iXLen %2,1810    <vscale x 4 x i1> %3,1811    iXLen %4, iXLen 1)1812 1813  ret <vscale x 4 x i32> %a1814}1815 1816define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1, iXLen %2) nounwind {1817; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32:1818; CHECK:       # %bb.0: # %entry1819; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1820; CHECK-NEXT:    vrgather.vx v12, v8, a01821; CHECK-NEXT:    vmv.v.v v8, v121822; CHECK-NEXT:    ret1823entry:1824  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.iXLen(1825    <vscale x 8 x i32> poison,1826    <vscale x 8 x i32> %0,1827    iXLen %1,1828    iXLen %2)1829 1830  ret <vscale x 8 x i32> %a1831}1832 1833define <vscale x 8 x i32> @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1834; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32:1835; CHECK:       # %bb.0: # %entry1836; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu1837; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t1838; CHECK-NEXT:    ret1839entry:1840  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.iXLen(1841    <vscale x 8 x i32> %0,1842    <vscale x 8 x i32> %1,1843    iXLen %2,1844    <vscale x 8 x i1> %3,1845    iXLen %4, iXLen 1)1846 1847  ret <vscale x 8 x i32> %a1848}1849 1850define <vscale x 16 x i32> @intrinsic_vrgather_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1, iXLen %2) nounwind {1851; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32:1852; CHECK:       # %bb.0: # %entry1853; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1854; CHECK-NEXT:    vrgather.vx v16, v8, a01855; CHECK-NEXT:    vmv.v.v v8, v161856; CHECK-NEXT:    ret1857entry:1858  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.iXLen(1859    <vscale x 16 x i32> poison,1860    <vscale x 16 x i32> %0,1861    iXLen %1,1862    iXLen %2)1863 1864  ret <vscale x 16 x i32> %a1865}1866 1867define <vscale x 16 x i32> @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1868; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32:1869; CHECK:       # %bb.0: # %entry1870; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu1871; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t1872; CHECK-NEXT:    ret1873entry:1874  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.iXLen(1875    <vscale x 16 x i32> %0,1876    <vscale x 16 x i32> %1,1877    iXLen %2,1878    <vscale x 16 x i1> %3,1879    iXLen %4, iXLen 1)1880 1881  ret <vscale x 16 x i32> %a1882}1883 1884define <vscale x 1 x i64> @intrinsic_vrgather_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1, iXLen %2) nounwind {1885; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64:1886; CHECK:       # %bb.0: # %entry1887; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1888; CHECK-NEXT:    vrgather.vx v9, v8, a01889; CHECK-NEXT:    vmv.v.v v8, v91890; CHECK-NEXT:    ret1891entry:1892  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.iXLen(1893    <vscale x 1 x i64> poison,1894    <vscale x 1 x i64> %0,1895    iXLen %1,1896    iXLen %2)1897 1898  ret <vscale x 1 x i64> %a1899}1900 1901define <vscale x 1 x i64> @intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1902; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64:1903; CHECK:       # %bb.0: # %entry1904; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu1905; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t1906; CHECK-NEXT:    ret1907entry:1908  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.iXLen(1909    <vscale x 1 x i64> %0,1910    <vscale x 1 x i64> %1,1911    iXLen %2,1912    <vscale x 1 x i1> %3,1913    iXLen %4, iXLen 1)1914 1915  ret <vscale x 1 x i64> %a1916}1917 1918define <vscale x 2 x i64> @intrinsic_vrgather_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1, iXLen %2) nounwind {1919; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64:1920; CHECK:       # %bb.0: # %entry1921; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1922; CHECK-NEXT:    vrgather.vx v10, v8, a01923; CHECK-NEXT:    vmv.v.v v8, v101924; CHECK-NEXT:    ret1925entry:1926  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.iXLen(1927    <vscale x 2 x i64> poison,1928    <vscale x 2 x i64> %0,1929    iXLen %1,1930    iXLen %2)1931 1932  ret <vscale x 2 x i64> %a1933}1934 1935define <vscale x 2 x i64> @intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1936; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64:1937; CHECK:       # %bb.0: # %entry1938; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu1939; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t1940; CHECK-NEXT:    ret1941entry:1942  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.iXLen(1943    <vscale x 2 x i64> %0,1944    <vscale x 2 x i64> %1,1945    iXLen %2,1946    <vscale x 2 x i1> %3,1947    iXLen %4, iXLen 1)1948 1949  ret <vscale x 2 x i64> %a1950}1951 1952define <vscale x 4 x i64> @intrinsic_vrgather_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1, iXLen %2) nounwind {1953; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64:1954; CHECK:       # %bb.0: # %entry1955; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1956; CHECK-NEXT:    vrgather.vx v12, v8, a01957; CHECK-NEXT:    vmv.v.v v8, v121958; CHECK-NEXT:    ret1959entry:1960  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.iXLen(1961    <vscale x 4 x i64> poison,1962    <vscale x 4 x i64> %0,1963    iXLen %1,1964    iXLen %2)1965 1966  ret <vscale x 4 x i64> %a1967}1968 1969define <vscale x 4 x i64> @intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1970; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64:1971; CHECK:       # %bb.0: # %entry1972; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu1973; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t1974; CHECK-NEXT:    ret1975entry:1976  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.iXLen(1977    <vscale x 4 x i64> %0,1978    <vscale x 4 x i64> %1,1979    iXLen %2,1980    <vscale x 4 x i1> %3,1981    iXLen %4, iXLen 1)1982 1983  ret <vscale x 4 x i64> %a1984}1985 1986define <vscale x 8 x i64> @intrinsic_vrgather_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1, iXLen %2) nounwind {1987; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i64_nxv8i64:1988; CHECK:       # %bb.0: # %entry1989; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1990; CHECK-NEXT:    vrgather.vx v16, v8, a01991; CHECK-NEXT:    vmv.v.v v8, v161992; CHECK-NEXT:    ret1993entry:1994  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.iXLen(1995    <vscale x 8 x i64> poison,1996    <vscale x 8 x i64> %0,1997    iXLen %1,1998    iXLen %2)1999 2000  ret <vscale x 8 x i64> %a2001}2002 2003define <vscale x 8 x i64> @intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2004; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64:2005; CHECK:       # %bb.0: # %entry2006; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu2007; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t2008; CHECK-NEXT:    ret2009entry:2010  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.iXLen(2011    <vscale x 8 x i64> %0,2012    <vscale x 8 x i64> %1,2013    iXLen %2,2014    <vscale x 8 x i1> %3,2015    iXLen %4, iXLen 1)2016 2017  ret <vscale x 8 x i64> %a2018}2019 2020define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1, iXLen %2) nounwind {2021; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16:2022; CHECK:       # %bb.0: # %entry2023; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2024; CHECK-NEXT:    vrgather.vx v9, v8, a02025; CHECK-NEXT:    vmv1r.v v8, v92026; CHECK-NEXT:    ret2027entry:2028  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.iXLen(2029    <vscale x 1 x half> poison,2030    <vscale x 1 x half> %0,2031    iXLen %1,2032    iXLen %2)2033 2034  ret <vscale x 1 x half> %a2035}2036 2037define <vscale x 1 x half> @intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2038; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16:2039; CHECK:       # %bb.0: # %entry2040; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu2041; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2042; CHECK-NEXT:    ret2043entry:2044  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.mask.nxv1f16.iXLen(2045    <vscale x 1 x half> %0,2046    <vscale x 1 x half> %1,2047    iXLen %2,2048    <vscale x 1 x i1> %3,2049    iXLen %4, iXLen 1)2050 2051  ret <vscale x 1 x half> %a2052}2053 2054define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1, iXLen %2) nounwind {2055; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16:2056; CHECK:       # %bb.0: # %entry2057; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2058; CHECK-NEXT:    vrgather.vx v9, v8, a02059; CHECK-NEXT:    vmv1r.v v8, v92060; CHECK-NEXT:    ret2061entry:2062  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.iXLen(2063    <vscale x 2 x half> poison,2064    <vscale x 2 x half> %0,2065    iXLen %1,2066    iXLen %2)2067 2068  ret <vscale x 2 x half> %a2069}2070 2071define <vscale x 2 x half> @intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2072; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16:2073; CHECK:       # %bb.0: # %entry2074; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu2075; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2076; CHECK-NEXT:    ret2077entry:2078  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.mask.nxv2f16.iXLen(2079    <vscale x 2 x half> %0,2080    <vscale x 2 x half> %1,2081    iXLen %2,2082    <vscale x 2 x i1> %3,2083    iXLen %4, iXLen 1)2084 2085  ret <vscale x 2 x half> %a2086}2087 2088define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1, iXLen %2) nounwind {2089; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16:2090; CHECK:       # %bb.0: # %entry2091; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2092; CHECK-NEXT:    vrgather.vx v9, v8, a02093; CHECK-NEXT:    vmv.v.v v8, v92094; CHECK-NEXT:    ret2095entry:2096  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.iXLen(2097    <vscale x 4 x half> poison,2098    <vscale x 4 x half> %0,2099    iXLen %1,2100    iXLen %2)2101 2102  ret <vscale x 4 x half> %a2103}2104 2105define <vscale x 4 x half> @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2106; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16:2107; CHECK:       # %bb.0: # %entry2108; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu2109; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2110; CHECK-NEXT:    ret2111entry:2112  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.mask.nxv4f16.iXLen(2113    <vscale x 4 x half> %0,2114    <vscale x 4 x half> %1,2115    iXLen %2,2116    <vscale x 4 x i1> %3,2117    iXLen %4, iXLen 1)2118 2119  ret <vscale x 4 x half> %a2120}2121 2122define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1, iXLen %2) nounwind {2123; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16:2124; CHECK:       # %bb.0: # %entry2125; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2126; CHECK-NEXT:    vrgather.vx v10, v8, a02127; CHECK-NEXT:    vmv.v.v v8, v102128; CHECK-NEXT:    ret2129entry:2130  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.iXLen(2131    <vscale x 8 x half> poison,2132    <vscale x 8 x half> %0,2133    iXLen %1,2134    iXLen %2)2135 2136  ret <vscale x 8 x half> %a2137}2138 2139define <vscale x 8 x half> @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2140; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16:2141; CHECK:       # %bb.0: # %entry2142; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu2143; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t2144; CHECK-NEXT:    ret2145entry:2146  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.mask.nxv8f16.iXLen(2147    <vscale x 8 x half> %0,2148    <vscale x 8 x half> %1,2149    iXLen %2,2150    <vscale x 8 x i1> %3,2151    iXLen %4, iXLen 1)2152 2153  ret <vscale x 8 x half> %a2154}2155 2156define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1, iXLen %2) nounwind {2157; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16:2158; CHECK:       # %bb.0: # %entry2159; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2160; CHECK-NEXT:    vrgather.vx v12, v8, a02161; CHECK-NEXT:    vmv.v.v v8, v122162; CHECK-NEXT:    ret2163entry:2164  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.iXLen(2165    <vscale x 16 x half> poison,2166    <vscale x 16 x half> %0,2167    iXLen %1,2168    iXLen %2)2169 2170  ret <vscale x 16 x half> %a2171}2172 2173define <vscale x 16 x half> @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2174; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16:2175; CHECK:       # %bb.0: # %entry2176; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu2177; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t2178; CHECK-NEXT:    ret2179entry:2180  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.mask.nxv16f16.iXLen(2181    <vscale x 16 x half> %0,2182    <vscale x 16 x half> %1,2183    iXLen %2,2184    <vscale x 16 x i1> %3,2185    iXLen %4, iXLen 1)2186 2187  ret <vscale x 16 x half> %a2188}2189 2190define <vscale x 32 x half> @intrinsic_vrgather_vx_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1, iXLen %2) nounwind {2191; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16:2192; CHECK:       # %bb.0: # %entry2193; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma2194; CHECK-NEXT:    vrgather.vx v16, v8, a02195; CHECK-NEXT:    vmv.v.v v8, v162196; CHECK-NEXT:    ret2197entry:2198  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.nxv32f16.iXLen(2199    <vscale x 32 x half> poison,2200    <vscale x 32 x half> %0,2201    iXLen %1,2202    iXLen %2)2203 2204  ret <vscale x 32 x half> %a2205}2206 2207define <vscale x 32 x half> @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {2208; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16:2209; CHECK:       # %bb.0: # %entry2210; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu2211; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t2212; CHECK-NEXT:    ret2213entry:2214  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.mask.nxv32f16.iXLen(2215    <vscale x 32 x half> %0,2216    <vscale x 32 x half> %1,2217    iXLen %2,2218    <vscale x 32 x i1> %3,2219    iXLen %4, iXLen 1)2220 2221  ret <vscale x 32 x half> %a2222}2223 2224define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1, iXLen %2) nounwind {2225; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32:2226; CHECK:       # %bb.0: # %entry2227; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma2228; CHECK-NEXT:    vrgather.vx v9, v8, a02229; CHECK-NEXT:    vmv1r.v v8, v92230; CHECK-NEXT:    ret2231entry:2232  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.iXLen(2233    <vscale x 1 x float> poison,2234    <vscale x 1 x float> %0,2235    iXLen %1,2236    iXLen %2)2237 2238  ret <vscale x 1 x float> %a2239}2240 2241define <vscale x 1 x float> @intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2242; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32:2243; CHECK:       # %bb.0: # %entry2244; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, mu2245; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2246; CHECK-NEXT:    ret2247entry:2248  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.iXLen(2249    <vscale x 1 x float> %0,2250    <vscale x 1 x float> %1,2251    iXLen %2,2252    <vscale x 1 x i1> %3,2253    iXLen %4, iXLen 1)2254 2255  ret <vscale x 1 x float> %a2256}2257 2258define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1, iXLen %2) nounwind {2259; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32:2260; CHECK:       # %bb.0: # %entry2261; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma2262; CHECK-NEXT:    vrgather.vx v9, v8, a02263; CHECK-NEXT:    vmv.v.v v8, v92264; CHECK-NEXT:    ret2265entry:2266  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.iXLen(2267    <vscale x 2 x float> poison,2268    <vscale x 2 x float> %0,2269    iXLen %1,2270    iXLen %2)2271 2272  ret <vscale x 2 x float> %a2273}2274 2275define <vscale x 2 x float> @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2276; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32:2277; CHECK:       # %bb.0: # %entry2278; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu2279; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2280; CHECK-NEXT:    ret2281entry:2282  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.iXLen(2283    <vscale x 2 x float> %0,2284    <vscale x 2 x float> %1,2285    iXLen %2,2286    <vscale x 2 x i1> %3,2287    iXLen %4, iXLen 1)2288 2289  ret <vscale x 2 x float> %a2290}2291 2292define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1, iXLen %2) nounwind {2293; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32:2294; CHECK:       # %bb.0: # %entry2295; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma2296; CHECK-NEXT:    vrgather.vx v10, v8, a02297; CHECK-NEXT:    vmv.v.v v8, v102298; CHECK-NEXT:    ret2299entry:2300  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.iXLen(2301    <vscale x 4 x float> poison,2302    <vscale x 4 x float> %0,2303    iXLen %1,2304    iXLen %2)2305 2306  ret <vscale x 4 x float> %a2307}2308 2309define <vscale x 4 x float> @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2310; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32:2311; CHECK:       # %bb.0: # %entry2312; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, mu2313; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t2314; CHECK-NEXT:    ret2315entry:2316  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.iXLen(2317    <vscale x 4 x float> %0,2318    <vscale x 4 x float> %1,2319    iXLen %2,2320    <vscale x 4 x i1> %3,2321    iXLen %4, iXLen 1)2322 2323  ret <vscale x 4 x float> %a2324}2325 2326define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1, iXLen %2) nounwind {2327; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32:2328; CHECK:       # %bb.0: # %entry2329; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma2330; CHECK-NEXT:    vrgather.vx v12, v8, a02331; CHECK-NEXT:    vmv.v.v v8, v122332; CHECK-NEXT:    ret2333entry:2334  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.iXLen(2335    <vscale x 8 x float> poison,2336    <vscale x 8 x float> %0,2337    iXLen %1,2338    iXLen %2)2339 2340  ret <vscale x 8 x float> %a2341}2342 2343define <vscale x 8 x float> @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2344; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32:2345; CHECK:       # %bb.0: # %entry2346; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, mu2347; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t2348; CHECK-NEXT:    ret2349entry:2350  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.iXLen(2351    <vscale x 8 x float> %0,2352    <vscale x 8 x float> %1,2353    iXLen %2,2354    <vscale x 8 x i1> %3,2355    iXLen %4, iXLen 1)2356 2357  ret <vscale x 8 x float> %a2358}2359 2360define <vscale x 16 x float> @intrinsic_vrgather_vx_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1, iXLen %2) nounwind {2361; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32:2362; CHECK:       # %bb.0: # %entry2363; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma2364; CHECK-NEXT:    vrgather.vx v16, v8, a02365; CHECK-NEXT:    vmv.v.v v8, v162366; CHECK-NEXT:    ret2367entry:2368  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.iXLen(2369    <vscale x 16 x float> poison,2370    <vscale x 16 x float> %0,2371    iXLen %1,2372    iXLen %2)2373 2374  ret <vscale x 16 x float> %a2375}2376 2377define <vscale x 16 x float> @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2378; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32:2379; CHECK:       # %bb.0: # %entry2380; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, mu2381; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t2382; CHECK-NEXT:    ret2383entry:2384  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.iXLen(2385    <vscale x 16 x float> %0,2386    <vscale x 16 x float> %1,2387    iXLen %2,2388    <vscale x 16 x i1> %3,2389    iXLen %4, iXLen 1)2390 2391  ret <vscale x 16 x float> %a2392}2393 2394define <vscale x 1 x double> @intrinsic_vrgather_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1, iXLen %2) nounwind {2395; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64:2396; CHECK:       # %bb.0: # %entry2397; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma2398; CHECK-NEXT:    vrgather.vx v9, v8, a02399; CHECK-NEXT:    vmv.v.v v8, v92400; CHECK-NEXT:    ret2401entry:2402  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.iXLen(2403    <vscale x 1 x double> poison,2404    <vscale x 1 x double> %0,2405    iXLen %1,2406    iXLen %2)2407 2408  ret <vscale x 1 x double> %a2409}2410 2411define <vscale x 1 x double> @intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2412; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64:2413; CHECK:       # %bb.0: # %entry2414; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu2415; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t2416; CHECK-NEXT:    ret2417entry:2418  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.iXLen(2419    <vscale x 1 x double> %0,2420    <vscale x 1 x double> %1,2421    iXLen %2,2422    <vscale x 1 x i1> %3,2423    iXLen %4, iXLen 1)2424 2425  ret <vscale x 1 x double> %a2426}2427 2428define <vscale x 2 x double> @intrinsic_vrgather_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1, iXLen %2) nounwind {2429; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64:2430; CHECK:       # %bb.0: # %entry2431; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma2432; CHECK-NEXT:    vrgather.vx v10, v8, a02433; CHECK-NEXT:    vmv.v.v v8, v102434; CHECK-NEXT:    ret2435entry:2436  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.iXLen(2437    <vscale x 2 x double> poison,2438    <vscale x 2 x double> %0,2439    iXLen %1,2440    iXLen %2)2441 2442  ret <vscale x 2 x double> %a2443}2444 2445define <vscale x 2 x double> @intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2446; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64:2447; CHECK:       # %bb.0: # %entry2448; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu2449; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t2450; CHECK-NEXT:    ret2451entry:2452  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.iXLen(2453    <vscale x 2 x double> %0,2454    <vscale x 2 x double> %1,2455    iXLen %2,2456    <vscale x 2 x i1> %3,2457    iXLen %4, iXLen 1)2458 2459  ret <vscale x 2 x double> %a2460}2461 2462define <vscale x 4 x double> @intrinsic_vrgather_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1, iXLen %2) nounwind {2463; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64:2464; CHECK:       # %bb.0: # %entry2465; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma2466; CHECK-NEXT:    vrgather.vx v12, v8, a02467; CHECK-NEXT:    vmv.v.v v8, v122468; CHECK-NEXT:    ret2469entry:2470  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.iXLen(2471    <vscale x 4 x double> poison,2472    <vscale x 4 x double> %0,2473    iXLen %1,2474    iXLen %2)2475 2476  ret <vscale x 4 x double> %a2477}2478 2479define <vscale x 4 x double> @intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2480; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64:2481; CHECK:       # %bb.0: # %entry2482; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, mu2483; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t2484; CHECK-NEXT:    ret2485entry:2486  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.iXLen(2487    <vscale x 4 x double> %0,2488    <vscale x 4 x double> %1,2489    iXLen %2,2490    <vscale x 4 x i1> %3,2491    iXLen %4, iXLen 1)2492 2493  ret <vscale x 4 x double> %a2494}2495 2496define <vscale x 8 x double> @intrinsic_vrgather_vx_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1, iXLen %2) nounwind {2497; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64:2498; CHECK:       # %bb.0: # %entry2499; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, ma2500; CHECK-NEXT:    vrgather.vx v16, v8, a02501; CHECK-NEXT:    vmv.v.v v8, v162502; CHECK-NEXT:    ret2503entry:2504  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.iXLen(2505    <vscale x 8 x double> poison,2506    <vscale x 8 x double> %0,2507    iXLen %1,2508    iXLen %2)2509 2510  ret <vscale x 8 x double> %a2511}2512 2513define <vscale x 8 x double> @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2514; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64:2515; CHECK:       # %bb.0: # %entry2516; CHECK-NEXT:    vsetvli zero, a1, e64, m8, ta, mu2517; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t2518; CHECK-NEXT:    ret2519entry:2520  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.iXLen(2521    <vscale x 8 x double> %0,2522    <vscale x 8 x double> %1,2523    iXLen %2,2524    <vscale x 8 x i1> %3,2525    iXLen %4, iXLen 1)2526 2527  ret <vscale x 8 x double> %a2528}2529 2530define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {2531; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8:2532; CHECK:       # %bb.0: # %entry2533; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma2534; CHECK-NEXT:    vrgather.vi v9, v8, 92535; CHECK-NEXT:    vmv1r.v v8, v92536; CHECK-NEXT:    ret2537entry:2538  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.nxv1i8.iXLen(2539    <vscale x 1 x i8> poison,2540    <vscale x 1 x i8> %0,2541    iXLen 9,2542    iXLen %1)2543 2544  ret <vscale x 1 x i8> %a2545}2546 2547define <vscale x 1 x i8> @intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2548; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8:2549; CHECK:       # %bb.0: # %entry2550; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu2551; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2552; CHECK-NEXT:    ret2553entry:2554  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.vx.mask.nxv1i8.iXLen(2555    <vscale x 1 x i8> %0,2556    <vscale x 1 x i8> %1,2557    iXLen 9,2558    <vscale x 1 x i1> %2,2559    iXLen %3, iXLen 1)2560 2561  ret <vscale x 1 x i8> %a2562}2563 2564define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {2565; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8:2566; CHECK:       # %bb.0: # %entry2567; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma2568; CHECK-NEXT:    vrgather.vi v9, v8, 92569; CHECK-NEXT:    vmv1r.v v8, v92570; CHECK-NEXT:    ret2571entry:2572  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.nxv2i8.iXLen(2573    <vscale x 2 x i8> poison,2574    <vscale x 2 x i8> %0,2575    iXLen 9,2576    iXLen %1)2577 2578  ret <vscale x 2 x i8> %a2579}2580 2581define <vscale x 2 x i8> @intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2582; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8:2583; CHECK:       # %bb.0: # %entry2584; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, mu2585; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2586; CHECK-NEXT:    ret2587entry:2588  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.vx.mask.nxv2i8.iXLen(2589    <vscale x 2 x i8> %0,2590    <vscale x 2 x i8> %1,2591    iXLen 9,2592    <vscale x 2 x i1> %2,2593    iXLen %3, iXLen 1)2594 2595  ret <vscale x 2 x i8> %a2596}2597 2598define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {2599; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8:2600; CHECK:       # %bb.0: # %entry2601; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma2602; CHECK-NEXT:    vrgather.vi v9, v8, 92603; CHECK-NEXT:    vmv1r.v v8, v92604; CHECK-NEXT:    ret2605entry:2606  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.nxv4i8.iXLen(2607    <vscale x 4 x i8> poison,2608    <vscale x 4 x i8> %0,2609    iXLen 9,2610    iXLen %1)2611 2612  ret <vscale x 4 x i8> %a2613}2614 2615define <vscale x 4 x i8> @intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2616; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8:2617; CHECK:       # %bb.0: # %entry2618; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, mu2619; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2620; CHECK-NEXT:    ret2621entry:2622  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.vx.mask.nxv4i8.iXLen(2623    <vscale x 4 x i8> %0,2624    <vscale x 4 x i8> %1,2625    iXLen 9,2626    <vscale x 4 x i1> %2,2627    iXLen %3, iXLen 1)2628 2629  ret <vscale x 4 x i8> %a2630}2631 2632define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {2633; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8:2634; CHECK:       # %bb.0: # %entry2635; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma2636; CHECK-NEXT:    vrgather.vi v9, v8, 92637; CHECK-NEXT:    vmv.v.v v8, v92638; CHECK-NEXT:    ret2639entry:2640  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.nxv8i8.iXLen(2641    <vscale x 8 x i8> poison,2642    <vscale x 8 x i8> %0,2643    iXLen 9,2644    iXLen %1)2645 2646  ret <vscale x 8 x i8> %a2647}2648 2649define <vscale x 8 x i8> @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2650; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8:2651; CHECK:       # %bb.0: # %entry2652; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu2653; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2654; CHECK-NEXT:    ret2655entry:2656  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.vx.mask.nxv8i8.iXLen(2657    <vscale x 8 x i8> %0,2658    <vscale x 8 x i8> %1,2659    iXLen 9,2660    <vscale x 8 x i1> %2,2661    iXLen %3, iXLen 1)2662 2663  ret <vscale x 8 x i8> %a2664}2665 2666define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {2667; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8:2668; CHECK:       # %bb.0: # %entry2669; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma2670; CHECK-NEXT:    vrgather.vi v10, v8, 92671; CHECK-NEXT:    vmv.v.v v8, v102672; CHECK-NEXT:    ret2673entry:2674  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.nxv16i8.iXLen(2675    <vscale x 16 x i8> poison,2676    <vscale x 16 x i8> %0,2677    iXLen 9,2678    iXLen %1)2679 2680  ret <vscale x 16 x i8> %a2681}2682 2683define <vscale x 16 x i8> @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2684; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8:2685; CHECK:       # %bb.0: # %entry2686; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu2687; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t2688; CHECK-NEXT:    ret2689entry:2690  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.vx.mask.nxv16i8.iXLen(2691    <vscale x 16 x i8> %0,2692    <vscale x 16 x i8> %1,2693    iXLen 9,2694    <vscale x 16 x i1> %2,2695    iXLen %3, iXLen 1)2696 2697  ret <vscale x 16 x i8> %a2698}2699 2700define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {2701; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8:2702; CHECK:       # %bb.0: # %entry2703; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma2704; CHECK-NEXT:    vrgather.vi v12, v8, 92705; CHECK-NEXT:    vmv.v.v v8, v122706; CHECK-NEXT:    ret2707entry:2708  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.nxv32i8.iXLen(2709    <vscale x 32 x i8> poison,2710    <vscale x 32 x i8> %0,2711    iXLen 9,2712    iXLen %1)2713 2714  ret <vscale x 32 x i8> %a2715}2716 2717define <vscale x 32 x i8> @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {2718; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8:2719; CHECK:       # %bb.0: # %entry2720; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, mu2721; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t2722; CHECK-NEXT:    ret2723entry:2724  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.vx.mask.nxv32i8.iXLen(2725    <vscale x 32 x i8> %0,2726    <vscale x 32 x i8> %1,2727    iXLen 9,2728    <vscale x 32 x i1> %2,2729    iXLen %3, iXLen 1)2730 2731  ret <vscale x 32 x i8> %a2732}2733 2734define <vscale x 64 x i8> @intrinsic_vrgather_vi_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {2735; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8:2736; CHECK:       # %bb.0: # %entry2737; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma2738; CHECK-NEXT:    vrgather.vi v16, v8, 92739; CHECK-NEXT:    vmv.v.v v8, v162740; CHECK-NEXT:    ret2741entry:2742  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.nxv64i8.iXLen(2743    <vscale x 64 x i8> poison,2744    <vscale x 64 x i8> %0,2745    iXLen 9,2746    iXLen %1)2747 2748  ret <vscale x 64 x i8> %a2749}2750 2751define <vscale x 64 x i8> @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {2752; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8:2753; CHECK:       # %bb.0: # %entry2754; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, mu2755; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t2756; CHECK-NEXT:    ret2757entry:2758  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.vx.mask.nxv64i8.iXLen(2759    <vscale x 64 x i8> %0,2760    <vscale x 64 x i8> %1,2761    iXLen 9,2762    <vscale x 64 x i1> %2,2763    iXLen %3, iXLen 1)2764 2765  ret <vscale x 64 x i8> %a2766}2767 2768define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {2769; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16:2770; CHECK:       # %bb.0: # %entry2771; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2772; CHECK-NEXT:    vrgather.vi v9, v8, 92773; CHECK-NEXT:    vmv1r.v v8, v92774; CHECK-NEXT:    ret2775entry:2776  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.nxv1i16.iXLen(2777    <vscale x 1 x i16> poison,2778    <vscale x 1 x i16> %0,2779    iXLen 9,2780    iXLen %1)2781 2782  ret <vscale x 1 x i16> %a2783}2784 2785define <vscale x 1 x i16> @intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2786; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16:2787; CHECK:       # %bb.0: # %entry2788; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu2789; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2790; CHECK-NEXT:    ret2791entry:2792  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.vx.mask.nxv1i16.iXLen(2793    <vscale x 1 x i16> %0,2794    <vscale x 1 x i16> %1,2795    iXLen 9,2796    <vscale x 1 x i1> %2,2797    iXLen %3, iXLen 1)2798 2799  ret <vscale x 1 x i16> %a2800}2801 2802define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {2803; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16:2804; CHECK:       # %bb.0: # %entry2805; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2806; CHECK-NEXT:    vrgather.vi v9, v8, 92807; CHECK-NEXT:    vmv1r.v v8, v92808; CHECK-NEXT:    ret2809entry:2810  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.nxv2i16.iXLen(2811    <vscale x 2 x i16> poison,2812    <vscale x 2 x i16> %0,2813    iXLen 9,2814    iXLen %1)2815 2816  ret <vscale x 2 x i16> %a2817}2818 2819define <vscale x 2 x i16> @intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2820; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16:2821; CHECK:       # %bb.0: # %entry2822; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu2823; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2824; CHECK-NEXT:    ret2825entry:2826  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.vx.mask.nxv2i16.iXLen(2827    <vscale x 2 x i16> %0,2828    <vscale x 2 x i16> %1,2829    iXLen 9,2830    <vscale x 2 x i1> %2,2831    iXLen %3, iXLen 1)2832 2833  ret <vscale x 2 x i16> %a2834}2835 2836define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {2837; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16:2838; CHECK:       # %bb.0: # %entry2839; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2840; CHECK-NEXT:    vrgather.vi v9, v8, 92841; CHECK-NEXT:    vmv.v.v v8, v92842; CHECK-NEXT:    ret2843entry:2844  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.nxv4i16.iXLen(2845    <vscale x 4 x i16> poison,2846    <vscale x 4 x i16> %0,2847    iXLen 9,2848    iXLen %1)2849 2850  ret <vscale x 4 x i16> %a2851}2852 2853define <vscale x 4 x i16> @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2854; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16:2855; CHECK:       # %bb.0: # %entry2856; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu2857; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2858; CHECK-NEXT:    ret2859entry:2860  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.vx.mask.nxv4i16.iXLen(2861    <vscale x 4 x i16> %0,2862    <vscale x 4 x i16> %1,2863    iXLen 9,2864    <vscale x 4 x i1> %2,2865    iXLen %3, iXLen 1)2866 2867  ret <vscale x 4 x i16> %a2868}2869 2870define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {2871; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16:2872; CHECK:       # %bb.0: # %entry2873; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2874; CHECK-NEXT:    vrgather.vi v10, v8, 92875; CHECK-NEXT:    vmv.v.v v8, v102876; CHECK-NEXT:    ret2877entry:2878  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.nxv8i16.iXLen(2879    <vscale x 8 x i16> poison,2880    <vscale x 8 x i16> %0,2881    iXLen 9,2882    iXLen %1)2883 2884  ret <vscale x 8 x i16> %a2885}2886 2887define <vscale x 8 x i16> @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2888; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16:2889; CHECK:       # %bb.0: # %entry2890; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu2891; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t2892; CHECK-NEXT:    ret2893entry:2894  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.vx.mask.nxv8i16.iXLen(2895    <vscale x 8 x i16> %0,2896    <vscale x 8 x i16> %1,2897    iXLen 9,2898    <vscale x 8 x i1> %2,2899    iXLen %3, iXLen 1)2900 2901  ret <vscale x 8 x i16> %a2902}2903 2904define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {2905; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16:2906; CHECK:       # %bb.0: # %entry2907; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2908; CHECK-NEXT:    vrgather.vi v12, v8, 92909; CHECK-NEXT:    vmv.v.v v8, v122910; CHECK-NEXT:    ret2911entry:2912  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.nxv16i16.iXLen(2913    <vscale x 16 x i16> poison,2914    <vscale x 16 x i16> %0,2915    iXLen 9,2916    iXLen %1)2917 2918  ret <vscale x 16 x i16> %a2919}2920 2921define <vscale x 16 x i16> @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2922; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16:2923; CHECK:       # %bb.0: # %entry2924; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu2925; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t2926; CHECK-NEXT:    ret2927entry:2928  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.vx.mask.nxv16i16.iXLen(2929    <vscale x 16 x i16> %0,2930    <vscale x 16 x i16> %1,2931    iXLen 9,2932    <vscale x 16 x i1> %2,2933    iXLen %3, iXLen 1)2934 2935  ret <vscale x 16 x i16> %a2936}2937 2938define <vscale x 32 x i16> @intrinsic_vrgather_vi_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {2939; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16:2940; CHECK:       # %bb.0: # %entry2941; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma2942; CHECK-NEXT:    vrgather.vi v16, v8, 92943; CHECK-NEXT:    vmv.v.v v8, v162944; CHECK-NEXT:    ret2945entry:2946  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.nxv32i16.iXLen(2947    <vscale x 32 x i16> poison,2948    <vscale x 32 x i16> %0,2949    iXLen 9,2950    iXLen %1)2951 2952  ret <vscale x 32 x i16> %a2953}2954 2955define <vscale x 32 x i16> @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {2956; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16:2957; CHECK:       # %bb.0: # %entry2958; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu2959; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t2960; CHECK-NEXT:    ret2961entry:2962  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.vx.mask.nxv32i16.iXLen(2963    <vscale x 32 x i16> %0,2964    <vscale x 32 x i16> %1,2965    iXLen 9,2966    <vscale x 32 x i1> %2,2967    iXLen %3, iXLen 1)2968 2969  ret <vscale x 32 x i16> %a2970}2971 2972define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {2973; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32:2974; CHECK:       # %bb.0: # %entry2975; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma2976; CHECK-NEXT:    vrgather.vi v9, v8, 92977; CHECK-NEXT:    vmv1r.v v8, v92978; CHECK-NEXT:    ret2979entry:2980  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.nxv1i32.iXLen(2981    <vscale x 1 x i32> poison,2982    <vscale x 1 x i32> %0,2983    iXLen 9,2984    iXLen %1)2985 2986  ret <vscale x 1 x i32> %a2987}2988 2989define <vscale x 1 x i32> @intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2990; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32:2991; CHECK:       # %bb.0: # %entry2992; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu2993; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t2994; CHECK-NEXT:    ret2995entry:2996  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.vx.mask.nxv1i32.iXLen(2997    <vscale x 1 x i32> %0,2998    <vscale x 1 x i32> %1,2999    iXLen 9,3000    <vscale x 1 x i1> %2,3001    iXLen %3, iXLen 1)3002 3003  ret <vscale x 1 x i32> %a3004}3005 3006define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {3007; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32:3008; CHECK:       # %bb.0: # %entry3009; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma3010; CHECK-NEXT:    vrgather.vi v9, v8, 93011; CHECK-NEXT:    vmv.v.v v8, v93012; CHECK-NEXT:    ret3013entry:3014  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.nxv2i32.iXLen(3015    <vscale x 2 x i32> poison,3016    <vscale x 2 x i32> %0,3017    iXLen 9,3018    iXLen %1)3019 3020  ret <vscale x 2 x i32> %a3021}3022 3023define <vscale x 2 x i32> @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {3024; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32:3025; CHECK:       # %bb.0: # %entry3026; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu3027; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3028; CHECK-NEXT:    ret3029entry:3030  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.vx.mask.nxv2i32.iXLen(3031    <vscale x 2 x i32> %0,3032    <vscale x 2 x i32> %1,3033    iXLen 9,3034    <vscale x 2 x i1> %2,3035    iXLen %3, iXLen 1)3036 3037  ret <vscale x 2 x i32> %a3038}3039 3040define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {3041; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32:3042; CHECK:       # %bb.0: # %entry3043; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3044; CHECK-NEXT:    vrgather.vi v10, v8, 93045; CHECK-NEXT:    vmv.v.v v8, v103046; CHECK-NEXT:    ret3047entry:3048  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(3049    <vscale x 4 x i32> poison,3050    <vscale x 4 x i32> %0,3051    iXLen 9,3052    iXLen %1)3053 3054  ret <vscale x 4 x i32> %a3055}3056 3057define <vscale x 4 x i32> @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {3058; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32:3059; CHECK:       # %bb.0: # %entry3060; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu3061; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t3062; CHECK-NEXT:    ret3063entry:3064  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.mask.nxv4i32.iXLen(3065    <vscale x 4 x i32> %0,3066    <vscale x 4 x i32> %1,3067    iXLen 9,3068    <vscale x 4 x i1> %2,3069    iXLen %3, iXLen 1)3070 3071  ret <vscale x 4 x i32> %a3072}3073 3074define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {3075; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32:3076; CHECK:       # %bb.0: # %entry3077; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma3078; CHECK-NEXT:    vrgather.vi v12, v8, 93079; CHECK-NEXT:    vmv.v.v v8, v123080; CHECK-NEXT:    ret3081entry:3082  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.nxv8i32.iXLen(3083    <vscale x 8 x i32> poison,3084    <vscale x 8 x i32> %0,3085    iXLen 9,3086    iXLen %1)3087 3088  ret <vscale x 8 x i32> %a3089}3090 3091define <vscale x 8 x i32> @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {3092; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32:3093; CHECK:       # %bb.0: # %entry3094; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu3095; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t3096; CHECK-NEXT:    ret3097entry:3098  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.vx.mask.nxv8i32.iXLen(3099    <vscale x 8 x i32> %0,3100    <vscale x 8 x i32> %1,3101    iXLen 9,3102    <vscale x 8 x i1> %2,3103    iXLen %3, iXLen 1)3104 3105  ret <vscale x 8 x i32> %a3106}3107 3108define <vscale x 16 x i32> @intrinsic_vrgather_vi_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {3109; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32:3110; CHECK:       # %bb.0: # %entry3111; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma3112; CHECK-NEXT:    vrgather.vi v16, v8, 93113; CHECK-NEXT:    vmv.v.v v8, v163114; CHECK-NEXT:    ret3115entry:3116  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.nxv16i32.iXLen(3117    <vscale x 16 x i32> poison,3118    <vscale x 16 x i32> %0,3119    iXLen 9,3120    iXLen %1)3121 3122  ret <vscale x 16 x i32> %a3123}3124 3125define <vscale x 16 x i32> @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {3126; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32:3127; CHECK:       # %bb.0: # %entry3128; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu3129; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t3130; CHECK-NEXT:    ret3131entry:3132  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.vx.mask.nxv16i32.iXLen(3133    <vscale x 16 x i32> %0,3134    <vscale x 16 x i32> %1,3135    iXLen 9,3136    <vscale x 16 x i1> %2,3137    iXLen %3, iXLen 1)3138 3139  ret <vscale x 16 x i32> %a3140}3141 3142define <vscale x 1 x i64> @intrinsic_vrgather_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {3143; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64:3144; CHECK:       # %bb.0: # %entry3145; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma3146; CHECK-NEXT:    vrgather.vi v9, v8, 93147; CHECK-NEXT:    vmv.v.v v8, v93148; CHECK-NEXT:    ret3149entry:3150  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.nxv1i64.iXLen(3151    <vscale x 1 x i64> poison,3152    <vscale x 1 x i64> %0,3153    iXLen 9,3154    iXLen %1)3155 3156  ret <vscale x 1 x i64> %a3157}3158 3159define <vscale x 1 x i64> @intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {3160; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64:3161; CHECK:       # %bb.0: # %entry3162; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu3163; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3164; CHECK-NEXT:    ret3165entry:3166  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.vx.mask.nxv1i64.iXLen(3167    <vscale x 1 x i64> %0,3168    <vscale x 1 x i64> %1,3169    iXLen 9,3170    <vscale x 1 x i1> %2,3171    iXLen %3, iXLen 1)3172 3173  ret <vscale x 1 x i64> %a3174}3175 3176define <vscale x 2 x i64> @intrinsic_vrgather_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {3177; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64:3178; CHECK:       # %bb.0: # %entry3179; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma3180; CHECK-NEXT:    vrgather.vi v10, v8, 93181; CHECK-NEXT:    vmv.v.v v8, v103182; CHECK-NEXT:    ret3183entry:3184  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.nxv2i64.iXLen(3185    <vscale x 2 x i64> poison,3186    <vscale x 2 x i64> %0,3187    iXLen 9,3188    iXLen %1)3189 3190  ret <vscale x 2 x i64> %a3191}3192 3193define <vscale x 2 x i64> @intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {3194; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64:3195; CHECK:       # %bb.0: # %entry3196; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu3197; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t3198; CHECK-NEXT:    ret3199entry:3200  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.vx.mask.nxv2i64.iXLen(3201    <vscale x 2 x i64> %0,3202    <vscale x 2 x i64> %1,3203    iXLen 9,3204    <vscale x 2 x i1> %2,3205    iXLen %3, iXLen 1)3206 3207  ret <vscale x 2 x i64> %a3208}3209 3210define <vscale x 4 x i64> @intrinsic_vrgather_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {3211; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64:3212; CHECK:       # %bb.0: # %entry3213; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma3214; CHECK-NEXT:    vrgather.vi v12, v8, 93215; CHECK-NEXT:    vmv.v.v v8, v123216; CHECK-NEXT:    ret3217entry:3218  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.nxv4i64.iXLen(3219    <vscale x 4 x i64> poison,3220    <vscale x 4 x i64> %0,3221    iXLen 9,3222    iXLen %1)3223 3224  ret <vscale x 4 x i64> %a3225}3226 3227define <vscale x 4 x i64> @intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {3228; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64:3229; CHECK:       # %bb.0: # %entry3230; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu3231; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t3232; CHECK-NEXT:    ret3233entry:3234  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.vx.mask.nxv4i64.iXLen(3235    <vscale x 4 x i64> %0,3236    <vscale x 4 x i64> %1,3237    iXLen 9,3238    <vscale x 4 x i1> %2,3239    iXLen %3, iXLen 1)3240 3241  ret <vscale x 4 x i64> %a3242}3243 3244define <vscale x 8 x i64> @intrinsic_vrgather_vi_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {3245; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i64_nxv8i64:3246; CHECK:       # %bb.0: # %entry3247; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma3248; CHECK-NEXT:    vrgather.vi v16, v8, 93249; CHECK-NEXT:    vmv.v.v v8, v163250; CHECK-NEXT:    ret3251entry:3252  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.nxv8i64.iXLen(3253    <vscale x 8 x i64> poison,3254    <vscale x 8 x i64> %0,3255    iXLen 9,3256    iXLen %1)3257 3258  ret <vscale x 8 x i64> %a3259}3260 3261define <vscale x 8 x i64> @intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {3262; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64:3263; CHECK:       # %bb.0: # %entry3264; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu3265; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t3266; CHECK-NEXT:    ret3267entry:3268  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.vx.mask.nxv8i64.iXLen(3269    <vscale x 8 x i64> %0,3270    <vscale x 8 x i64> %1,3271    iXLen 9,3272    <vscale x 8 x i1> %2,3273    iXLen %3, iXLen 1)3274 3275  ret <vscale x 8 x i64> %a3276}3277 3278define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {3279; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16:3280; CHECK:       # %bb.0: # %entry3281; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma3282; CHECK-NEXT:    vrgather.vi v9, v8, 93283; CHECK-NEXT:    vmv1r.v v8, v93284; CHECK-NEXT:    ret3285entry:3286  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.nxv1f16.iXLen(3287    <vscale x 1 x half> poison,3288    <vscale x 1 x half> %0,3289    iXLen 9,3290    iXLen %1)3291 3292  ret <vscale x 1 x half> %a3293}3294 3295define <vscale x 1 x half> @intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {3296; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16:3297; CHECK:       # %bb.0: # %entry3298; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu3299; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3300; CHECK-NEXT:    ret3301entry:3302  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.vx.mask.nxv1f16.iXLen(3303    <vscale x 1 x half> %0,3304    <vscale x 1 x half> %1,3305    iXLen 9,3306    <vscale x 1 x i1> %2,3307    iXLen %3, iXLen 1)3308 3309  ret <vscale x 1 x half> %a3310}3311 3312define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {3313; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16:3314; CHECK:       # %bb.0: # %entry3315; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma3316; CHECK-NEXT:    vrgather.vi v9, v8, 93317; CHECK-NEXT:    vmv1r.v v8, v93318; CHECK-NEXT:    ret3319entry:3320  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.nxv2f16.iXLen(3321    <vscale x 2 x half> poison,3322    <vscale x 2 x half> %0,3323    iXLen 9,3324    iXLen %1)3325 3326  ret <vscale x 2 x half> %a3327}3328 3329define <vscale x 2 x half> @intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {3330; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16:3331; CHECK:       # %bb.0: # %entry3332; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu3333; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3334; CHECK-NEXT:    ret3335entry:3336  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.vx.mask.nxv2f16.iXLen(3337    <vscale x 2 x half> %0,3338    <vscale x 2 x half> %1,3339    iXLen 9,3340    <vscale x 2 x i1> %2,3341    iXLen %3, iXLen 1)3342 3343  ret <vscale x 2 x half> %a3344}3345 3346define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {3347; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16:3348; CHECK:       # %bb.0: # %entry3349; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma3350; CHECK-NEXT:    vrgather.vi v9, v8, 93351; CHECK-NEXT:    vmv.v.v v8, v93352; CHECK-NEXT:    ret3353entry:3354  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.nxv4f16.iXLen(3355    <vscale x 4 x half> poison,3356    <vscale x 4 x half> %0,3357    iXLen 9,3358    iXLen %1)3359 3360  ret <vscale x 4 x half> %a3361}3362 3363define <vscale x 4 x half> @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {3364; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16:3365; CHECK:       # %bb.0: # %entry3366; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu3367; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3368; CHECK-NEXT:    ret3369entry:3370  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.vx.mask.nxv4f16.iXLen(3371    <vscale x 4 x half> %0,3372    <vscale x 4 x half> %1,3373    iXLen 9,3374    <vscale x 4 x i1> %2,3375    iXLen %3, iXLen 1)3376 3377  ret <vscale x 4 x half> %a3378}3379 3380define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {3381; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16:3382; CHECK:       # %bb.0: # %entry3383; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma3384; CHECK-NEXT:    vrgather.vi v10, v8, 93385; CHECK-NEXT:    vmv.v.v v8, v103386; CHECK-NEXT:    ret3387entry:3388  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.nxv8f16.iXLen(3389    <vscale x 8 x half> poison,3390    <vscale x 8 x half> %0,3391    iXLen 9,3392    iXLen %1)3393 3394  ret <vscale x 8 x half> %a3395}3396 3397define <vscale x 8 x half> @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {3398; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16:3399; CHECK:       # %bb.0: # %entry3400; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu3401; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t3402; CHECK-NEXT:    ret3403entry:3404  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.vx.mask.nxv8f16.iXLen(3405    <vscale x 8 x half> %0,3406    <vscale x 8 x half> %1,3407    iXLen 9,3408    <vscale x 8 x i1> %2,3409    iXLen %3, iXLen 1)3410 3411  ret <vscale x 8 x half> %a3412}3413 3414define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {3415; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16:3416; CHECK:       # %bb.0: # %entry3417; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma3418; CHECK-NEXT:    vrgather.vi v12, v8, 93419; CHECK-NEXT:    vmv.v.v v8, v123420; CHECK-NEXT:    ret3421entry:3422  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.nxv16f16.iXLen(3423    <vscale x 16 x half> poison,3424    <vscale x 16 x half> %0,3425    iXLen 9,3426    iXLen %1)3427 3428  ret <vscale x 16 x half> %a3429}3430 3431define <vscale x 16 x half> @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {3432; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16:3433; CHECK:       # %bb.0: # %entry3434; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu3435; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t3436; CHECK-NEXT:    ret3437entry:3438  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.vx.mask.nxv16f16.iXLen(3439    <vscale x 16 x half> %0,3440    <vscale x 16 x half> %1,3441    iXLen 9,3442    <vscale x 16 x i1> %2,3443    iXLen %3, iXLen 1)3444 3445  ret <vscale x 16 x half> %a3446}3447 3448define <vscale x 32 x half> @intrinsic_vrgather_vi_nxv32f16_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {3449; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16:3450; CHECK:       # %bb.0: # %entry3451; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma3452; CHECK-NEXT:    vrgather.vi v16, v8, 93453; CHECK-NEXT:    vmv.v.v v8, v163454; CHECK-NEXT:    ret3455entry:3456  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.nxv32f16.iXLen(3457    <vscale x 32 x half> poison,3458    <vscale x 32 x half> %0,3459    iXLen 9,3460    iXLen %1)3461 3462  ret <vscale x 32 x half> %a3463}3464 3465define <vscale x 32 x half> @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {3466; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16:3467; CHECK:       # %bb.0: # %entry3468; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu3469; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t3470; CHECK-NEXT:    ret3471entry:3472  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.vx.mask.nxv32f16.iXLen(3473    <vscale x 32 x half> %0,3474    <vscale x 32 x half> %1,3475    iXLen 9,3476    <vscale x 32 x i1> %2,3477    iXLen %3, iXLen 1)3478 3479  ret <vscale x 32 x half> %a3480}3481 3482define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {3483; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32:3484; CHECK:       # %bb.0: # %entry3485; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma3486; CHECK-NEXT:    vrgather.vi v9, v8, 93487; CHECK-NEXT:    vmv1r.v v8, v93488; CHECK-NEXT:    ret3489entry:3490  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.nxv1f32.iXLen(3491    <vscale x 1 x float> poison,3492    <vscale x 1 x float> %0,3493    iXLen 9,3494    iXLen %1)3495 3496  ret <vscale x 1 x float> %a3497}3498 3499define <vscale x 1 x float> @intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {3500; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32:3501; CHECK:       # %bb.0: # %entry3502; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, mu3503; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3504; CHECK-NEXT:    ret3505entry:3506  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.vx.mask.nxv1f32.iXLen(3507    <vscale x 1 x float> %0,3508    <vscale x 1 x float> %1,3509    iXLen 9,3510    <vscale x 1 x i1> %2,3511    iXLen %3, iXLen 1)3512 3513  ret <vscale x 1 x float> %a3514}3515 3516define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {3517; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32:3518; CHECK:       # %bb.0: # %entry3519; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma3520; CHECK-NEXT:    vrgather.vi v9, v8, 93521; CHECK-NEXT:    vmv.v.v v8, v93522; CHECK-NEXT:    ret3523entry:3524  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.iXLen(3525    <vscale x 2 x float> poison,3526    <vscale x 2 x float> %0,3527    iXLen 9,3528    iXLen %1)3529 3530  ret <vscale x 2 x float> %a3531}3532 3533define <vscale x 2 x float> @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {3534; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32:3535; CHECK:       # %bb.0: # %entry3536; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, mu3537; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3538; CHECK-NEXT:    ret3539entry:3540  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.vx.mask.nxv2f32.iXLen(3541    <vscale x 2 x float> %0,3542    <vscale x 2 x float> %1,3543    iXLen 9,3544    <vscale x 2 x i1> %2,3545    iXLen %3, iXLen 1)3546 3547  ret <vscale x 2 x float> %a3548}3549 3550define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {3551; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32:3552; CHECK:       # %bb.0: # %entry3553; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma3554; CHECK-NEXT:    vrgather.vi v10, v8, 93555; CHECK-NEXT:    vmv.v.v v8, v103556; CHECK-NEXT:    ret3557entry:3558  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.nxv4f32.iXLen(3559    <vscale x 4 x float> poison,3560    <vscale x 4 x float> %0,3561    iXLen 9,3562    iXLen %1)3563 3564  ret <vscale x 4 x float> %a3565}3566 3567define <vscale x 4 x float> @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {3568; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32:3569; CHECK:       # %bb.0: # %entry3570; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, mu3571; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t3572; CHECK-NEXT:    ret3573entry:3574  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.vx.mask.nxv4f32.iXLen(3575    <vscale x 4 x float> %0,3576    <vscale x 4 x float> %1,3577    iXLen 9,3578    <vscale x 4 x i1> %2,3579    iXLen %3, iXLen 1)3580 3581  ret <vscale x 4 x float> %a3582}3583 3584define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {3585; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32:3586; CHECK:       # %bb.0: # %entry3587; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma3588; CHECK-NEXT:    vrgather.vi v12, v8, 93589; CHECK-NEXT:    vmv.v.v v8, v123590; CHECK-NEXT:    ret3591entry:3592  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.nxv8f32.iXLen(3593    <vscale x 8 x float> poison,3594    <vscale x 8 x float> %0,3595    iXLen 9,3596    iXLen %1)3597 3598  ret <vscale x 8 x float> %a3599}3600 3601define <vscale x 8 x float> @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {3602; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32:3603; CHECK:       # %bb.0: # %entry3604; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, mu3605; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t3606; CHECK-NEXT:    ret3607entry:3608  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.vx.mask.nxv8f32.iXLen(3609    <vscale x 8 x float> %0,3610    <vscale x 8 x float> %1,3611    iXLen 9,3612    <vscale x 8 x i1> %2,3613    iXLen %3, iXLen 1)3614 3615  ret <vscale x 8 x float> %a3616}3617 3618define <vscale x 16 x float> @intrinsic_vrgather_vi_nxv16f32_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {3619; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32:3620; CHECK:       # %bb.0: # %entry3621; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma3622; CHECK-NEXT:    vrgather.vi v16, v8, 93623; CHECK-NEXT:    vmv.v.v v8, v163624; CHECK-NEXT:    ret3625entry:3626  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.nxv16f32.iXLen(3627    <vscale x 16 x float> poison,3628    <vscale x 16 x float> %0,3629    iXLen 9,3630    iXLen %1)3631 3632  ret <vscale x 16 x float> %a3633}3634 3635define <vscale x 16 x float> @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {3636; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32:3637; CHECK:       # %bb.0: # %entry3638; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, mu3639; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t3640; CHECK-NEXT:    ret3641entry:3642  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.vx.mask.nxv16f32.iXLen(3643    <vscale x 16 x float> %0,3644    <vscale x 16 x float> %1,3645    iXLen 9,3646    <vscale x 16 x i1> %2,3647    iXLen %3, iXLen 1)3648 3649  ret <vscale x 16 x float> %a3650}3651 3652define <vscale x 1 x double> @intrinsic_vrgather_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {3653; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64:3654; CHECK:       # %bb.0: # %entry3655; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma3656; CHECK-NEXT:    vrgather.vi v9, v8, 93657; CHECK-NEXT:    vmv.v.v v8, v93658; CHECK-NEXT:    ret3659entry:3660  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.nxv1f64.iXLen(3661    <vscale x 1 x double> poison,3662    <vscale x 1 x double> %0,3663    iXLen 9,3664    iXLen %1)3665 3666  ret <vscale x 1 x double> %a3667}3668 3669define <vscale x 1 x double> @intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {3670; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64:3671; CHECK:       # %bb.0: # %entry3672; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu3673; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t3674; CHECK-NEXT:    ret3675entry:3676  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.vx.mask.nxv1f64.iXLen(3677    <vscale x 1 x double> %0,3678    <vscale x 1 x double> %1,3679    iXLen 9,3680    <vscale x 1 x i1> %2,3681    iXLen %3, iXLen 1)3682 3683  ret <vscale x 1 x double> %a3684}3685 3686define <vscale x 2 x double> @intrinsic_vrgather_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {3687; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64:3688; CHECK:       # %bb.0: # %entry3689; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma3690; CHECK-NEXT:    vrgather.vi v10, v8, 93691; CHECK-NEXT:    vmv.v.v v8, v103692; CHECK-NEXT:    ret3693entry:3694  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.nxv2f64.iXLen(3695    <vscale x 2 x double> poison,3696    <vscale x 2 x double> %0,3697    iXLen 9,3698    iXLen %1)3699 3700  ret <vscale x 2 x double> %a3701}3702 3703define <vscale x 2 x double> @intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {3704; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64:3705; CHECK:       # %bb.0: # %entry3706; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, mu3707; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t3708; CHECK-NEXT:    ret3709entry:3710  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.vx.mask.nxv2f64.iXLen(3711    <vscale x 2 x double> %0,3712    <vscale x 2 x double> %1,3713    iXLen 9,3714    <vscale x 2 x i1> %2,3715    iXLen %3, iXLen 1)3716 3717  ret <vscale x 2 x double> %a3718}3719 3720define <vscale x 4 x double> @intrinsic_vrgather_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {3721; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64:3722; CHECK:       # %bb.0: # %entry3723; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma3724; CHECK-NEXT:    vrgather.vi v12, v8, 93725; CHECK-NEXT:    vmv.v.v v8, v123726; CHECK-NEXT:    ret3727entry:3728  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.nxv4f64.iXLen(3729    <vscale x 4 x double> poison,3730    <vscale x 4 x double> %0,3731    iXLen 9,3732    iXLen %1)3733 3734  ret <vscale x 4 x double> %a3735}3736 3737define <vscale x 4 x double> @intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {3738; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64:3739; CHECK:       # %bb.0: # %entry3740; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, mu3741; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t3742; CHECK-NEXT:    ret3743entry:3744  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.vx.mask.nxv4f64.iXLen(3745    <vscale x 4 x double> %0,3746    <vscale x 4 x double> %1,3747    iXLen 9,3748    <vscale x 4 x i1> %2,3749    iXLen %3, iXLen 1)3750 3751  ret <vscale x 4 x double> %a3752}3753 3754define <vscale x 8 x double> @intrinsic_vrgather_vi_nxv8f64_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {3755; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64:3756; CHECK:       # %bb.0: # %entry3757; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma3758; CHECK-NEXT:    vrgather.vi v16, v8, 93759; CHECK-NEXT:    vmv.v.v v8, v163760; CHECK-NEXT:    ret3761entry:3762  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.nxv8f64.iXLen(3763    <vscale x 8 x double> poison,3764    <vscale x 8 x double> %0,3765    iXLen 9,3766    iXLen %1)3767 3768  ret <vscale x 8 x double> %a3769}3770 3771define <vscale x 8 x double> @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {3772; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64:3773; CHECK:       # %bb.0: # %entry3774; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, mu3775; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t3776; CHECK-NEXT:    ret3777entry:3778  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.vx.mask.nxv8f64.iXLen(3779    <vscale x 8 x double> %0,3780    <vscale x 8 x double> %1,3781    iXLen 9,3782    <vscale x 8 x i1> %2,3783    iXLen %3, iXLen 1)3784 3785  ret <vscale x 8 x double> %a3786}3787 3788define <vscale x 1 x bfloat> @intrinsic_vrgather_vv_nxv1bf16_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {3789; CHECK-LABEL: intrinsic_vrgather_vv_nxv1bf16_nxv1bf16_nxv1i16:3790; CHECK:       # %bb.0: # %entry3791; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma3792; CHECK-NEXT:    vrgather.vv v10, v8, v93793; CHECK-NEXT:    vmv1r.v v8, v103794; CHECK-NEXT:    ret3795entry:3796  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.nxv1bf16.iXLen(3797    <vscale x 1 x bfloat> poison,3798    <vscale x 1 x bfloat> %0,3799    <vscale x 1 x i16> %1,3800    iXLen %2)3801 3802  ret <vscale x 1 x bfloat> %a3803}3804 3805define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vv_nxv1bf16_nxv1bf16_nxv1i16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {3806; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1bf16_nxv1bf16_nxv1i16:3807; CHECK:       # %bb.0: # %entry3808; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu3809; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t3810; CHECK-NEXT:    ret3811entry:3812  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv1bf16.iXLen(3813    <vscale x 1 x bfloat> %0,3814    <vscale x 1 x bfloat> %1,3815    <vscale x 1 x i16> %2,3816    <vscale x 1 x i1> %3,3817    iXLen %4, iXLen 1)3818 3819  ret <vscale x 1 x bfloat> %a3820}3821 3822define <vscale x 2 x bfloat> @intrinsic_vrgather_vv_nxv2bf16_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {3823; CHECK-LABEL: intrinsic_vrgather_vv_nxv2bf16_nxv2bf16_nxv2i16:3824; CHECK:       # %bb.0: # %entry3825; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma3826; CHECK-NEXT:    vrgather.vv v10, v8, v93827; CHECK-NEXT:    vmv1r.v v8, v103828; CHECK-NEXT:    ret3829entry:3830  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.nxv2bf16.iXLen(3831    <vscale x 2 x bfloat> poison,3832    <vscale x 2 x bfloat> %0,3833    <vscale x 2 x i16> %1,3834    iXLen %2)3835 3836  ret <vscale x 2 x bfloat> %a3837}3838 3839define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vv_nxv2bf16_nxv2bf16_nxv2i16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {3840; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2bf16_nxv2bf16_nxv2i16:3841; CHECK:       # %bb.0: # %entry3842; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu3843; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t3844; CHECK-NEXT:    ret3845entry:3846  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv2bf16.iXLen(3847    <vscale x 2 x bfloat> %0,3848    <vscale x 2 x bfloat> %1,3849    <vscale x 2 x i16> %2,3850    <vscale x 2 x i1> %3,3851    iXLen %4, iXLen 1)3852 3853  ret <vscale x 2 x bfloat> %a3854}3855 3856define <vscale x 4 x bfloat> @intrinsic_vrgather_vv_nxv4bf16_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {3857; CHECK-LABEL: intrinsic_vrgather_vv_nxv4bf16_nxv4bf16_nxv4i16:3858; CHECK:       # %bb.0: # %entry3859; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma3860; CHECK-NEXT:    vrgather.vv v10, v8, v93861; CHECK-NEXT:    vmv.v.v v8, v103862; CHECK-NEXT:    ret3863entry:3864  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.nxv4bf16.iXLen(3865    <vscale x 4 x bfloat> poison,3866    <vscale x 4 x bfloat> %0,3867    <vscale x 4 x i16> %1,3868    iXLen %2)3869 3870  ret <vscale x 4 x bfloat> %a3871}3872 3873define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vv_nxv4bf16_nxv4bf16_nxv4i16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {3874; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4bf16_nxv4bf16_nxv4i16:3875; CHECK:       # %bb.0: # %entry3876; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu3877; CHECK-NEXT:    vrgather.vv v8, v9, v10, v0.t3878; CHECK-NEXT:    ret3879entry:3880  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv4bf16.iXLen(3881    <vscale x 4 x bfloat> %0,3882    <vscale x 4 x bfloat> %1,3883    <vscale x 4 x i16> %2,3884    <vscale x 4 x i1> %3,3885    iXLen %4, iXLen 1)3886 3887  ret <vscale x 4 x bfloat> %a3888}3889 3890define <vscale x 8 x bfloat> @intrinsic_vrgather_vv_nxv8bf16_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {3891; CHECK-LABEL: intrinsic_vrgather_vv_nxv8bf16_nxv8bf16_nxv8i16:3892; CHECK:       # %bb.0: # %entry3893; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma3894; CHECK-NEXT:    vrgather.vv v12, v8, v103895; CHECK-NEXT:    vmv.v.v v8, v123896; CHECK-NEXT:    ret3897entry:3898  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.nxv8bf16.iXLen(3899    <vscale x 8 x bfloat> poison,3900    <vscale x 8 x bfloat> %0,3901    <vscale x 8 x i16> %1,3902    iXLen %2)3903 3904  ret <vscale x 8 x bfloat> %a3905}3906 3907define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vv_nxv8bf16_nxv8bf16_nxv8i16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {3908; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8bf16_nxv8bf16_nxv8i16:3909; CHECK:       # %bb.0: # %entry3910; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu3911; CHECK-NEXT:    vrgather.vv v8, v10, v12, v0.t3912; CHECK-NEXT:    ret3913entry:3914  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv8bf16.iXLen(3915    <vscale x 8 x bfloat> %0,3916    <vscale x 8 x bfloat> %1,3917    <vscale x 8 x i16> %2,3918    <vscale x 8 x i1> %3,3919    iXLen %4, iXLen 1)3920 3921  ret <vscale x 8 x bfloat> %a3922}3923 3924define <vscale x 16 x bfloat> @intrinsic_vrgather_vv_nxv16bf16_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {3925; CHECK-LABEL: intrinsic_vrgather_vv_nxv16bf16_nxv16bf16_nxv16i16:3926; CHECK:       # %bb.0: # %entry3927; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma3928; CHECK-NEXT:    vrgather.vv v16, v8, v123929; CHECK-NEXT:    vmv.v.v v8, v163930; CHECK-NEXT:    ret3931entry:3932  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.nxv16bf16.iXLen(3933    <vscale x 16 x bfloat> poison,3934    <vscale x 16 x bfloat> %0,3935    <vscale x 16 x i16> %1,3936    iXLen %2)3937 3938  ret <vscale x 16 x bfloat> %a3939}3940 3941define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vv_nxv16bf16_nxv16bf16_nxv16i16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {3942; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16bf16_nxv16bf16_nxv16i16:3943; CHECK:       # %bb.0: # %entry3944; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu3945; CHECK-NEXT:    vrgather.vv v8, v12, v16, v0.t3946; CHECK-NEXT:    ret3947entry:3948  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv16bf16.iXLen(3949    <vscale x 16 x bfloat> %0,3950    <vscale x 16 x bfloat> %1,3951    <vscale x 16 x i16> %2,3952    <vscale x 16 x i1> %3,3953    iXLen %4, iXLen 1)3954 3955  ret <vscale x 16 x bfloat> %a3956}3957 3958define <vscale x 32 x bfloat> @intrinsic_vrgather_vv_nxv32bf16_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {3959; CHECK-LABEL: intrinsic_vrgather_vv_nxv32bf16_nxv32bf16_nxv32i16:3960; CHECK:       # %bb.0: # %entry3961; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma3962; CHECK-NEXT:    vrgather.vv v24, v8, v163963; CHECK-NEXT:    vmv.v.v v8, v243964; CHECK-NEXT:    ret3965entry:3966  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.nxv32bf16.iXLen(3967    <vscale x 32 x bfloat> poison,3968    <vscale x 32 x bfloat> %0,3969    <vscale x 32 x i16> %1,3970    iXLen %2)3971 3972  ret <vscale x 32 x bfloat> %a3973}3974 3975define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vv_nxv32bf16_nxv32bf16_nxv32i16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {3976; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32bf16_nxv32bf16_nxv32i16:3977; CHECK:       # %bb.0: # %entry3978; CHECK-NEXT:    vl8re16.v v24, (a0)3979; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu3980; CHECK-NEXT:    vrgather.vv v8, v16, v24, v0.t3981; CHECK-NEXT:    ret3982entry:3983  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vv.mask.nxv32bf16.iXLen(3984    <vscale x 32 x bfloat> %0,3985    <vscale x 32 x bfloat> %1,3986    <vscale x 32 x i16> %2,3987    <vscale x 32 x i1> %3,3988    iXLen %4, iXLen 1)3989 3990  ret <vscale x 32 x bfloat> %a3991}3992 3993define <vscale x 1 x bfloat> @intrinsic_vrgather_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1, iXLen %2) nounwind {3994; CHECK-LABEL: intrinsic_vrgather_vx_nxv1bf16_nxv1bf16:3995; CHECK:       # %bb.0: # %entry3996; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma3997; CHECK-NEXT:    vrgather.vx v9, v8, a03998; CHECK-NEXT:    vmv1r.v v8, v93999; CHECK-NEXT:    ret4000entry:4001  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.iXLen(4002    <vscale x 1 x bfloat> poison,4003    <vscale x 1 x bfloat> %0,4004    iXLen %1,4005    iXLen %2)4006 4007  ret <vscale x 1 x bfloat> %a4008}4009 4010define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {4011; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1bf16_nxv1bf16:4012; CHECK:       # %bb.0: # %entry4013; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, mu4014; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t4015; CHECK-NEXT:    ret4016entry:4017  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv1bf16.iXLen(4018    <vscale x 1 x bfloat> %0,4019    <vscale x 1 x bfloat> %1,4020    iXLen %2,4021    <vscale x 1 x i1> %3,4022    iXLen %4, iXLen 1)4023 4024  ret <vscale x 1 x bfloat> %a4025}4026 4027define <vscale x 2 x bfloat> @intrinsic_vrgather_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1, iXLen %2) nounwind {4028; CHECK-LABEL: intrinsic_vrgather_vx_nxv2bf16_nxv2bf16:4029; CHECK:       # %bb.0: # %entry4030; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma4031; CHECK-NEXT:    vrgather.vx v9, v8, a04032; CHECK-NEXT:    vmv1r.v v8, v94033; CHECK-NEXT:    ret4034entry:4035  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.iXLen(4036    <vscale x 2 x bfloat> poison,4037    <vscale x 2 x bfloat> %0,4038    iXLen %1,4039    iXLen %2)4040 4041  ret <vscale x 2 x bfloat> %a4042}4043 4044define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {4045; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2bf16_nxv2bf16:4046; CHECK:       # %bb.0: # %entry4047; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, mu4048; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t4049; CHECK-NEXT:    ret4050entry:4051  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv2bf1bf16XLen(4052    <vscale x 2 x bfloat> %0,4053    <vscale x 2 x bfloat> %1,4054    iXLen %2,4055    <vscale x 2 x i1> %3,4056    iXLen %4, iXLen 1)4057 4058  ret <vscale x 2 x bfloat> %a4059}4060 4061define <vscale x 4 x bfloat> @intrinsic_vrgather_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1, iXLen %2) nounwind {4062; CHECK-LABEL: intrinsic_vrgather_vx_nxv4bf16_nxv4bf16:4063; CHECK:       # %bb.0: # %entry4064; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma4065; CHECK-NEXT:    vrgather.vx v9, v8, a04066; CHECK-NEXT:    vmv.v.v v8, v94067; CHECK-NEXT:    ret4068entry:4069  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.iXLen(4070    <vscale x 4 x bfloat> poison,4071    <vscale x 4 x bfloat> %0,4072    iXLen %1,4073    iXLen %2)4074 4075  ret <vscale x 4 x bfloat> %a4076}4077 4078define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {4079; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4bf16_nxv4bf16:4080; CHECK:       # %bb.0: # %entry4081; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu4082; CHECK-NEXT:    vrgather.vx v8, v9, a0, v0.t4083; CHECK-NEXT:    ret4084entry:4085  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv4bf16.iXLen(4086    <vscale x 4 x bfloat> %0,4087    <vscale x 4 x bfloat> %1,4088    iXLen %2,4089    <vscale x 4 x i1> %3,4090    iXLen %4, iXLen 1)4091 4092  ret <vscale x 4 x bfloat> %a4093}4094 4095define <vscale x 8 x bfloat> @intrinsic_vrgather_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1, iXLen %2) nounwind {4096; CHECK-LABEL: intrinsic_vrgather_vx_nxv8bf16_nxv8bf16:4097; CHECK:       # %bb.0: # %entry4098; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma4099; CHECK-NEXT:    vrgather.vx v10, v8, a04100; CHECK-NEXT:    vmv.v.v v8, v104101; CHECK-NEXT:    ret4102entry:4103  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.iXLen(4104    <vscale x 8 x bfloat> poison,4105    <vscale x 8 x bfloat> %0,4106    iXLen %1,4107    iXLen %2)4108 4109  ret <vscale x 8 x bfloat> %a4110}4111 4112define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {4113; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8bf16_nxv8bf16:4114; CHECK:       # %bb.0: # %entry4115; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, mu4116; CHECK-NEXT:    vrgather.vx v8, v10, a0, v0.t4117; CHECK-NEXT:    ret4118entry:4119  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv8bf16.iXLen(4120    <vscale x 8 x bfloat> %0,4121    <vscale x 8 x bfloat> %1,4122    iXLen %2,4123    <vscale x 8 x i1> %3,4124    iXLen %4, iXLen 1)4125 4126  ret <vscale x 8 x bfloat> %a4127}4128 4129define <vscale x 16 x bfloat> @intrinsic_vrgather_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1, iXLen %2) nounwind {4130; CHECK-LABEL: intrinsic_vrgather_vx_nxv16bf16_nxv16bf16:4131; CHECK:       # %bb.0: # %entry4132; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma4133; CHECK-NEXT:    vrgather.vx v12, v8, a04134; CHECK-NEXT:    vmv.v.v v8, v124135; CHECK-NEXT:    ret4136entry:4137  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.nxv16bf16.iXLen(4138    <vscale x 16 x bfloat> poison,4139    <vscale x 16 x bfloat> %0,4140    iXLen %1,4141    iXLen %2)4142 4143  ret <vscale x 16 x bfloat> %a4144}4145 4146define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {4147; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16bf16_nxv16bf16:4148; CHECK:       # %bb.0: # %entry4149; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, mu4150; CHECK-NEXT:    vrgather.vx v8, v12, a0, v0.t4151; CHECK-NEXT:    ret4152entry:4153  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv16bf16.iXLen(4154    <vscale x 16 x bfloat> %0,4155    <vscale x 16 x bfloat> %1,4156    iXLen %2,4157    <vscale x 16 x i1> %3,4158    iXLen %4, iXLen 1)4159 4160  ret <vscale x 16 x bfloat> %a4161}4162 4163define <vscale x 32 x bfloat> @intrinsic_vrgather_vx_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1, iXLen %2) nounwind {4164; CHECK-LABEL: intrinsic_vrgather_vx_nxv32bf16_nxv32bf16:4165; CHECK:       # %bb.0: # %entry4166; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma4167; CHECK-NEXT:    vrgather.vx v16, v8, a04168; CHECK-NEXT:    vmv.v.v v8, v164169; CHECK-NEXT:    ret4170entry:4171  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.nxv32bf16.iXLen(4172    <vscale x 32 x bfloat> poison,4173    <vscale x 32 x bfloat> %0,4174    iXLen %1,4175    iXLen %2)4176 4177  ret <vscale x 32 x bfloat> %a4178}4179 4180define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vx_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {4181; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32bf16_nxv32bf16:4182; CHECK:       # %bb.0: # %entry4183; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, mu4184; CHECK-NEXT:    vrgather.vx v8, v16, a0, v0.t4185; CHECK-NEXT:    ret4186entry:4187  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv32bf16.iXLen(4188    <vscale x 32 x bfloat> %0,4189    <vscale x 32 x bfloat> %1,4190    iXLen %2,4191    <vscale x 32 x i1> %3,4192    iXLen %4, iXLen 1)4193 4194  ret <vscale x 32 x bfloat> %a4195}4196 4197define <vscale x 1 x bfloat> @intrinsic_vrgather_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, iXLen %1) nounwind {4198; CHECK-LABEL: intrinsic_vrgather_vi_nxv1bf16_nxv1bf16:4199; CHECK:       # %bb.0: # %entry4200; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma4201; CHECK-NEXT:    vrgather.vi v9, v8, 94202; CHECK-NEXT:    vmv1r.v v8, v94203; CHECK-NEXT:    ret4204entry:4205  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.nxv1bf16.iXLen(4206    <vscale x 1 x bfloat> poison,4207    <vscale x 1 x bfloat> %0,4208    iXLen 9,4209    iXLen %1)4210 4211  ret <vscale x 1 x bfloat> %a4212}4213 4214define <vscale x 1 x bfloat> @intrinsic_vrgather_mask_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {4215; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1bf16_nxv1bf16:4216; CHECK:       # %bb.0: # %entry4217; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, mu4218; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t4219; CHECK-NEXT:    ret4220entry:4221  %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv1bf16.iXLen(4222    <vscale x 1 x bfloat> %0,4223    <vscale x 1 x bfloat> %1,4224    iXLen 9,4225    <vscale x 1 x i1> %2,4226    iXLen %3, iXLen 1)4227 4228  ret <vscale x 1 x bfloat> %a4229}4230 4231define <vscale x 2 x bfloat> @intrinsic_vrgather_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, iXLen %1) nounwind {4232; CHECK-LABEL: intrinsic_vrgather_vi_nxv2bf16_nxv2bf16:4233; CHECK:       # %bb.0: # %entry4234; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma4235; CHECK-NEXT:    vrgather.vi v9, v8, 94236; CHECK-NEXT:    vmv1r.v v8, v94237; CHECK-NEXT:    ret4238entry:4239  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.nxv2bf16.iXLen(4240    <vscale x 2 x bfloat> poison,4241    <vscale x 2 x bfloat> %0,4242    iXLen 9,4243    iXLen %1)4244 4245  ret <vscale x 2 x bfloat> %a4246}4247 4248define <vscale x 2 x bfloat> @intrinsic_vrgather_mask_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {4249; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2bf16_nxv2bf16:4250; CHECK:       # %bb.0: # %entry4251; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, mu4252; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t4253; CHECK-NEXT:    ret4254entry:4255  %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv2bf16.iXLen(4256    <vscale x 2 x bfloat> %0,4257    <vscale x 2 x bfloat> %1,4258    iXLen 9,4259    <vscale x 2 x i1> %2,4260    iXLen %3, iXLen 1)4261 4262  ret <vscale x 2 x bfloat> %a4263}4264 4265define <vscale x 4 x bfloat> @intrinsic_vrgather_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, iXLen %1) nounwind {4266; CHECK-LABEL: intrinsic_vrgather_vi_nxv4bf16_nxv4bf16:4267; CHECK:       # %bb.0: # %entry4268; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma4269; CHECK-NEXT:    vrgather.vi v9, v8, 94270; CHECK-NEXT:    vmv.v.v v8, v94271; CHECK-NEXT:    ret4272entry:4273  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.nxv4bf16.iXLen(4274    <vscale x 4 x bfloat> poison,4275    <vscale x 4 x bfloat> %0,4276    iXLen 9,4277    iXLen %1)4278 4279  ret <vscale x 4 x bfloat> %a4280}4281 4282define <vscale x 4 x bfloat> @intrinsic_vrgather_mask_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {4283; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4bf16_nxv4bf16:4284; CHECK:       # %bb.0: # %entry4285; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, mu4286; CHECK-NEXT:    vrgather.vi v8, v9, 9, v0.t4287; CHECK-NEXT:    ret4288entry:4289  %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv4bf16.iXLen(4290    <vscale x 4 x bfloat> %0,4291    <vscale x 4 x bfloat> %1,4292    iXLen 9,4293    <vscale x 4 x i1> %2,4294    iXLen %3, iXLen 1)4295 4296  ret <vscale x 4 x bfloat> %a4297}4298 4299define <vscale x 8 x bfloat> @intrinsic_vrgather_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, iXLen %1) nounwind {4300; CHECK-LABEL: intrinsic_vrgather_vi_nxv8bf16_nxv8bf16:4301; CHECK:       # %bb.0: # %entry4302; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma4303; CHECK-NEXT:    vrgather.vi v10, v8, 94304; CHECK-NEXT:    vmv.v.v v8, v104305; CHECK-NEXT:    ret4306entry:4307  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.nxv8bf16.iXLen(4308    <vscale x 8 x bfloat> poison,4309    <vscale x 8 x bfloat> %0,4310    iXLen 9,4311    iXLen %1)4312 4313  ret <vscale x 8 x bfloat> %a4314}4315 4316define <vscale x 8 x bfloat> @intrinsic_vrgather_mask_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {4317; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8bf16_nxv8bf16:4318; CHECK:       # %bb.0: # %entry4319; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, mu4320; CHECK-NEXT:    vrgather.vi v8, v10, 9, v0.t4321; CHECK-NEXT:    ret4322entry:4323  %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv8bf16.iXLen(4324    <vscale x 8 x bfloat> %0,4325    <vscale x 8 x bfloat> %1,4326    iXLen 9,4327    <vscale x 8 x i1> %2,4328    iXLen %3, iXLen 1)4329 4330  ret <vscale x 8 x bfloat> %a4331}4332 4333define <vscale x 16 x bfloat> @intrinsic_vrgather_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, iXLen %1) nounwind {4334; CHECK-LABEL: intrinsic_vrgather_vi_nxv16bf16_nxv16bf16:4335; CHECK:       # %bb.0: # %entry4336; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma4337; CHECK-NEXT:    vrgather.vi v12, v8, 94338; CHECK-NEXT:    vmv.v.v v8, v124339; CHECK-NEXT:    ret4340entry:4341  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.nxv16bf16.iXLen(4342    <vscale x 16 x bfloat> poison,4343    <vscale x 16 x bfloat> %0,4344    iXLen 9,4345    iXLen %1)4346 4347  ret <vscale x 16 x bfloat> %a4348}4349 4350define <vscale x 16 x bfloat> @intrinsic_vrgather_mask_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {4351; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16bf16_nxv16bf16:4352; CHECK:       # %bb.0: # %entry4353; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, mu4354; CHECK-NEXT:    vrgather.vi v8, v12, 9, v0.t4355; CHECK-NEXT:    ret4356entry:4357  %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv16bf16.iXLen(4358    <vscale x 16 x bfloat> %0,4359    <vscale x 16 x bfloat> %1,4360    iXLen 9,4361    <vscale x 16 x i1> %2,4362    iXLen %3, iXLen 1)4363 4364  ret <vscale x 16 x bfloat> %a4365}4366 4367define <vscale x 32 x bfloat> @intrinsic_vrgather_vi_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, iXLen %1) nounwind {4368; CHECK-LABEL: intrinsic_vrgather_vi_nxv32bf16_nxv32bf16:4369; CHECK:       # %bb.0: # %entry4370; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma4371; CHECK-NEXT:    vrgather.vi v16, v8, 94372; CHECK-NEXT:    vmv.v.v v8, v164373; CHECK-NEXT:    ret4374entry:4375  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.nxv32bf16.iXLen(4376    <vscale x 32 x bfloat> poison,4377    <vscale x 32 x bfloat> %0,4378    iXLen 9,4379    iXLen %1)4380 4381  ret <vscale x 32 x bfloat> %a4382}4383 4384define <vscale x 32 x bfloat> @intrinsic_vrgather_mask_vi_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {4385; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32bf16_nxv32bf16:4386; CHECK:       # %bb.0: # %entry4387; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, mu4388; CHECK-NEXT:    vrgather.vi v8, v16, 9, v0.t4389; CHECK-NEXT:    ret4390entry:4391  %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgather.vx.mask.nxv32bf16.iXLen(4392    <vscale x 32 x bfloat> %0,4393    <vscale x 32 x bfloat> %1,4394    iXLen 9,4395    <vscale x 32 x i1> %2,4396    iXLen %3, iXLen 1)4397 4398  ret <vscale x 32 x bfloat> %a4399}4400 4401