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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefix NOSUBREG3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s -enable-subreg-liveness=true | FileCheck %s --check-prefix SUBREG4 5; This test checks that vrgatherei16 instructions are correctly6; register-allocated. The LMUL=1 destination register groups may not overlap7; with the EMUL=2 source vector register groups.8 9; FIXME: enabling subregister liveness results in incorrect register10; allocation!11 12define internal void @foo(<vscale x 1 x i16> %v15, <vscale x 1 x i16> %0, <vscale x 1 x i16> %vs12.i.i.i, <vscale x 1 x i16> %1, <vscale x 8 x i8> %v37) {13; NOSUBREG-LABEL: foo:14; NOSUBREG: # %bb.0: # %loopIR.preheader.i.i15; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma16; NOSUBREG-NEXT: vmv.v.i v9, 017; NOSUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma18; NOSUBREG-NEXT: vmv.v.i v14, 019; NOSUBREG-NEXT: vmv1r.v v8, v920; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma21; NOSUBREG-NEXT: vrgatherei16.vv v8, v9, v1422; NOSUBREG-NEXT: .LBB0_1: # %loopIR3.i.i23; NOSUBREG-NEXT: # =>This Inner Loop Header: Depth=124; NOSUBREG-NEXT: vl1r.v v9, (zero)25; NOSUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma26; NOSUBREG-NEXT: vmv1r.v v13, v1227; NOSUBREG-NEXT: vrgatherei16.vv v13, v9, v1028; NOSUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma29; NOSUBREG-NEXT: vand.vv v9, v8, v1330; NOSUBREG-NEXT: vs1r.v v9, (zero)31; NOSUBREG-NEXT: j .LBB0_132;33; SUBREG-LABEL: foo:34; SUBREG: # %bb.0: # %loopIR.preheader.i.i35; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma36; SUBREG-NEXT: vmv.v.i v9, 037; SUBREG-NEXT: vsetvli zero, zero, e16, m2, ta, ma38; SUBREG-NEXT: vmv.v.i v14, 039; SUBREG-NEXT: vmv1r.v v8, v940; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma41; SUBREG-NEXT: vrgatherei16.vv v8, v9, v1442; SUBREG-NEXT: .LBB0_1: # %loopIR3.i.i43; SUBREG-NEXT: # =>This Inner Loop Header: Depth=144; SUBREG-NEXT: vl1r.v v9, (zero)45; SUBREG-NEXT: vsetivli zero, 4, e8, m1, tu, ma46; SUBREG-NEXT: vmv1r.v v13, v1247; SUBREG-NEXT: vrgatherei16.vv v13, v9, v1048; SUBREG-NEXT: vsetvli a0, zero, e8, m1, ta, ma49; SUBREG-NEXT: vand.vv v9, v8, v1350; SUBREG-NEXT: vs1r.v v9, (zero)51; SUBREG-NEXT: j .LBB0_152loopIR.preheader.i.i:53 %v18 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %vs12.i.i.i, i64 0)54 br label %loopIR3.i.i55 56loopIR3.i.i: ; preds = %loopIR3.i.i, %loopIR.preheader.i.i57 %v376 = load <vscale x 8 x i8>, ptr addrspace(1) null, align 858 %v38 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> zeroinitializer, <vscale x 8 x i8> zeroinitializer, <vscale x 8 x i16> zeroinitializer, i64 4)59 %v40 = tail call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8> %v37, <vscale x 8 x i8> %v376, <vscale x 8 x i16> %v18, i64 4)60 %v42 = and <vscale x 8 x i8> %v38, %v4061 store <vscale x 8 x i8> %v42, ptr addrspace(1) null, align 462 br label %loopIR3.i.i63}64 65