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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vrgatherei16.vv v10, v8, v912; CHECK-NEXT: vmv1r.v v8, v1013; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.nxv1i8(16 <vscale x 1 x i8> poison,17 <vscale x 1 x i8> %0,18 <vscale x 1 x i16> %1,19 iXLen %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i8_nxv1i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu28; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(32 <vscale x 1 x i8> %0,33 <vscale x 1 x i8> %1,34 <vscale x 1 x i16> %2,35 <vscale x 1 x i1> %3,36 iXLen %4, iXLen 1)37 38 ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i8_nxv2i8:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma45; CHECK-NEXT: vrgatherei16.vv v10, v8, v946; CHECK-NEXT: vmv1r.v v8, v1047; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.nxv2i8(50 <vscale x 2 x i8> poison,51 <vscale x 2 x i8> %0,52 <vscale x 2 x i16> %1,53 iXLen %2)54 55 ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i8_nxv2i8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu62; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv2i8(66 <vscale x 2 x i8> %0,67 <vscale x 2 x i8> %1,68 <vscale x 2 x i16> %2,69 <vscale x 2 x i1> %3,70 iXLen %4, iXLen 1)71 72 ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i8_nxv4i8:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma79; CHECK-NEXT: vrgatherei16.vv v10, v8, v980; CHECK-NEXT: vmv1r.v v8, v1081; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.nxv4i8(84 <vscale x 4 x i8> poison,85 <vscale x 4 x i8> %0,86 <vscale x 4 x i16> %1,87 iXLen %2)88 89 ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i8_nxv4i8:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu96; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv4i8(100 <vscale x 4 x i8> %0,101 <vscale x 4 x i8> %1,102 <vscale x 4 x i16> %2,103 <vscale x 4 x i1> %3,104 iXLen %4, iXLen 1)105 106 ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i8_nxv8i8:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma113; CHECK-NEXT: vrgatherei16.vv v9, v8, v10114; CHECK-NEXT: vmv.v.v v8, v9115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8(118 <vscale x 8 x i8> poison,119 <vscale x 8 x i8> %0,120 <vscale x 8 x i16> %1,121 iXLen %2)122 123 ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i8_nxv8i8:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu130; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv8i8(134 <vscale x 8 x i8> %0,135 <vscale x 8 x i8> %1,136 <vscale x 8 x i16> %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i8_nxv16i8:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma147; CHECK-NEXT: vrgatherei16.vv v10, v8, v12148; CHECK-NEXT: vmv.v.v v8, v10149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.nxv16i8(152 <vscale x 16 x i8> poison,153 <vscale x 16 x i8> %0,154 <vscale x 16 x i16> %1,155 iXLen %2)156 157 ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i8_nxv16i8:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu164; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 16 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv16i8(168 <vscale x 16 x i8> %0,169 <vscale x 16 x i8> %1,170 <vscale x 16 x i16> %2,171 <vscale x 16 x i1> %3,172 iXLen %4, iXLen 1)173 174 ret <vscale x 16 x i8> %a175}176 177define <vscale x 32 x i8> @intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i8_nxv32i8:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma181; CHECK-NEXT: vrgatherei16.vv v12, v8, v16182; CHECK-NEXT: vmv.v.v v8, v12183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.nxv32i8(186 <vscale x 32 x i8> poison,187 <vscale x 32 x i8> %0,188 <vscale x 32 x i16> %1,189 iXLen %2)190 191 ret <vscale x 32 x i8> %a192}193 194define <vscale x 32 x i8> @intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i8_nxv32i8:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu198; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv32i8(202 <vscale x 32 x i8> %0,203 <vscale x 32 x i8> %1,204 <vscale x 32 x i16> %2,205 <vscale x 32 x i1> %3,206 iXLen %4, iXLen 1)207 208 ret <vscale x 32 x i8> %a209}210 211define <vscale x 1 x i16> @intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i16_nxv1i16:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma215; CHECK-NEXT: vrgatherei16.vv v10, v8, v9216; CHECK-NEXT: vmv1r.v v8, v10217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.nxv1i16(220 <vscale x 1 x i16> poison,221 <vscale x 1 x i16> %0,222 <vscale x 1 x i16> %1,223 iXLen %2)224 225 ret <vscale x 1 x i16> %a226}227 228define <vscale x 1 x i16> @intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i16_nxv1i16:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu232; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 1 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv1i16(236 <vscale x 1 x i16> %0,237 <vscale x 1 x i16> %1,238 <vscale x 1 x i16> %2,239 <vscale x 1 x i1> %3,240 iXLen %4, iXLen 1)241 242 ret <vscale x 1 x i16> %a243}244 245define <vscale x 2 x i16> @intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2i16_nxv2i16:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma249; CHECK-NEXT: vrgatherei16.vv v10, v8, v9250; CHECK-NEXT: vmv1r.v v8, v10251; CHECK-NEXT: ret252entry:253 %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.nxv2i16(254 <vscale x 2 x i16> poison,255 <vscale x 2 x i16> %0,256 <vscale x 2 x i16> %1,257 iXLen %2)258 259 ret <vscale x 2 x i16> %a260}261 262define <vscale x 2 x i16> @intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2i16_nxv2i16:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu266; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 2 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv2i16(270 <vscale x 2 x i16> %0,271 <vscale x 2 x i16> %1,272 <vscale x 2 x i16> %2,273 <vscale x 2 x i1> %3,274 iXLen %4, iXLen 1)275 276 ret <vscale x 2 x i16> %a277}278 279define <vscale x 4 x i16> @intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i16_nxv4i16:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma283; CHECK-NEXT: vrgatherei16.vv v10, v8, v9284; CHECK-NEXT: vmv.v.v v8, v10285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.nxv4i16(288 <vscale x 4 x i16> poison,289 <vscale x 4 x i16> %0,290 <vscale x 4 x i16> %1,291 iXLen %2)292 293 ret <vscale x 4 x i16> %a294}295 296define <vscale x 4 x i16> @intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i16_nxv4i16:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu300; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 4 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv4i16(304 <vscale x 4 x i16> %0,305 <vscale x 4 x i16> %1,306 <vscale x 4 x i16> %2,307 <vscale x 4 x i1> %3,308 iXLen %4, iXLen 1)309 310 ret <vscale x 4 x i16> %a311}312 313define <vscale x 8 x i16> @intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i16_nxv8i16:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma317; CHECK-NEXT: vrgatherei16.vv v12, v8, v10318; CHECK-NEXT: vmv.v.v v8, v12319; CHECK-NEXT: ret320entry:321 %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.nxv8i16(322 <vscale x 8 x i16> poison,323 <vscale x 8 x i16> %0,324 <vscale x 8 x i16> %1,325 iXLen %2)326 327 ret <vscale x 8 x i16> %a328}329 330define <vscale x 8 x i16> @intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i16_nxv8i16:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu334; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 8 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv8i16(338 <vscale x 8 x i16> %0,339 <vscale x 8 x i16> %1,340 <vscale x 8 x i16> %2,341 <vscale x 8 x i1> %3,342 iXLen %4, iXLen 1)343 344 ret <vscale x 8 x i16> %a345}346 347define <vscale x 16 x i16> @intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i16_nxv16i16:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma351; CHECK-NEXT: vrgatherei16.vv v16, v8, v12352; CHECK-NEXT: vmv.v.v v8, v16353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.nxv16i16(356 <vscale x 16 x i16> poison,357 <vscale x 16 x i16> %0,358 <vscale x 16 x i16> %1,359 iXLen %2)360 361 ret <vscale x 16 x i16> %a362}363 364define <vscale x 16 x i16> @intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {365; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i16_nxv16i16:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu368; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 16 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv16i16(372 <vscale x 16 x i16> %0,373 <vscale x 16 x i16> %1,374 <vscale x 16 x i16> %2,375 <vscale x 16 x i1> %3,376 iXLen %4, iXLen 1)377 378 ret <vscale x 16 x i16> %a379}380 381define <vscale x 32 x i16> @intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {382; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32i16_nxv32i16:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma385; CHECK-NEXT: vrgatherei16.vv v24, v8, v16386; CHECK-NEXT: vmv.v.v v8, v24387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.nxv32i16(390 <vscale x 32 x i16> poison,391 <vscale x 32 x i16> %0,392 <vscale x 32 x i16> %1,393 iXLen %2)394 395 ret <vscale x 32 x i16> %a396}397 398define <vscale x 32 x i16> @intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {399; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32i16_nxv32i16:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vl8re16.v v24, (a0)402; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu403; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t404; CHECK-NEXT: ret405entry:406 %a = call <vscale x 32 x i16> @llvm.riscv.vrgatherei16.vv.mask.nxv32i16(407 <vscale x 32 x i16> %0,408 <vscale x 32 x i16> %1,409 <vscale x 32 x i16> %2,410 <vscale x 32 x i1> %3,411 iXLen %4, iXLen 1)412 413 ret <vscale x 32 x i16> %a414}415 416define <vscale x 1 x i32> @intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {417; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1i32_nxv1i32:418; CHECK: # %bb.0: # %entry419; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma420; CHECK-NEXT: vrgatherei16.vv v10, v8, v9421; CHECK-NEXT: vmv1r.v v8, v10422; CHECK-NEXT: ret423entry:424 %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.nxv1i32(425 <vscale x 1 x i32> poison,426 <vscale x 1 x i32> %0,427 <vscale x 1 x i16> %1,428 iXLen %2)429 430 ret <vscale x 1 x i32> %a431}432 433define <vscale x 1 x i32> @intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {434; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1i32_nxv1i32:435; CHECK: # %bb.0: # %entry436; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu437; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t438; CHECK-NEXT: ret439entry:440 %a = call <vscale x 1 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv1i32(441 <vscale x 1 x i32> %0,442 <vscale x 1 x i32> %1,443 <vscale x 1 x i16> %2,444 <vscale x 1 x i1> %3,445 iXLen %4, iXLen 1)446 447 ret <vscale x 1 x i32> %a448}449 450define <vscale x 4 x i32> @intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {451; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i32_nxv4i32:452; CHECK: # %bb.0: # %entry453; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma454; CHECK-NEXT: vrgatherei16.vv v12, v8, v10455; CHECK-NEXT: vmv.v.v v8, v12456; CHECK-NEXT: ret457entry:458 %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(459 <vscale x 4 x i32> poison,460 <vscale x 4 x i32> %0,461 <vscale x 4 x i16> %1,462 iXLen %2)463 464 ret <vscale x 4 x i32> %a465}466 467define <vscale x 4 x i32> @intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {468; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i32_nxv4i32:469; CHECK: # %bb.0: # %entry470; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu471; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t472; CHECK-NEXT: ret473entry:474 %a = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv4i32(475 <vscale x 4 x i32> %0,476 <vscale x 4 x i32> %1,477 <vscale x 4 x i16> %2,478 <vscale x 4 x i1> %3,479 iXLen %4, iXLen 1)480 481 ret <vscale x 4 x i32> %a482}483 484define <vscale x 8 x i32> @intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {485; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i32_nxv8i32:486; CHECK: # %bb.0: # %entry487; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma488; CHECK-NEXT: vrgatherei16.vv v16, v8, v12489; CHECK-NEXT: vmv.v.v v8, v16490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.nxv8i32(493 <vscale x 8 x i32> poison,494 <vscale x 8 x i32> %0,495 <vscale x 8 x i16> %1,496 iXLen %2)497 498 ret <vscale x 8 x i32> %a499}500 501define <vscale x 8 x i32> @intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {502; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i32_nxv8i32:503; CHECK: # %bb.0: # %entry504; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu505; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t506; CHECK-NEXT: ret507entry:508 %a = call <vscale x 8 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv8i32(509 <vscale x 8 x i32> %0,510 <vscale x 8 x i32> %1,511 <vscale x 8 x i16> %2,512 <vscale x 8 x i1> %3,513 iXLen %4, iXLen 1)514 515 ret <vscale x 8 x i32> %a516}517 518define <vscale x 16 x i32> @intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {519; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16i32_nxv16i32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma522; CHECK-NEXT: vrgatherei16.vv v24, v8, v16523; CHECK-NEXT: vmv.v.v v8, v24524; CHECK-NEXT: ret525entry:526 %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.nxv16i32(527 <vscale x 16 x i32> poison,528 <vscale x 16 x i32> %0,529 <vscale x 16 x i16> %1,530 iXLen %2)531 532 ret <vscale x 16 x i32> %a533}534 535define <vscale x 16 x i32> @intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {536; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16i32_nxv16i32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vl4re16.v v24, (a0)539; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu540; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t541; CHECK-NEXT: ret542entry:543 %a = call <vscale x 16 x i32> @llvm.riscv.vrgatherei16.vv.mask.nxv16i32(544 <vscale x 16 x i32> %0,545 <vscale x 16 x i32> %1,546 <vscale x 16 x i16> %2,547 <vscale x 16 x i1> %3,548 iXLen %4, iXLen 1)549 550 ret <vscale x 16 x i32> %a551}552 553define <vscale x 4 x i64> @intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {554; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4i64_nxv4i64:555; CHECK: # %bb.0: # %entry556; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma557; CHECK-NEXT: vrgatherei16.vv v16, v8, v12558; CHECK-NEXT: vmv.v.v v8, v16559; CHECK-NEXT: ret560entry:561 %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.nxv4i64(562 <vscale x 4 x i64> poison,563 <vscale x 4 x i64> %0,564 <vscale x 4 x i16> %1,565 iXLen %2)566 567 ret <vscale x 4 x i64> %a568}569 570define <vscale x 4 x i64> @intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {571; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4i64_nxv4i64:572; CHECK: # %bb.0: # %entry573; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu574; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t575; CHECK-NEXT: ret576entry:577 %a = call <vscale x 4 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv4i64(578 <vscale x 4 x i64> %0,579 <vscale x 4 x i64> %1,580 <vscale x 4 x i16> %2,581 <vscale x 4 x i1> %3,582 iXLen %4, iXLen 1)583 584 ret <vscale x 4 x i64> %a585}586 587define <vscale x 8 x i64> @intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {588; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8i64_nxv8i64:589; CHECK: # %bb.0: # %entry590; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma591; CHECK-NEXT: vrgatherei16.vv v24, v8, v16592; CHECK-NEXT: vmv.v.v v8, v24593; CHECK-NEXT: ret594entry:595 %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.nxv8i64(596 <vscale x 8 x i64> poison,597 <vscale x 8 x i64> %0,598 <vscale x 8 x i16> %1,599 iXLen %2)600 601 ret <vscale x 8 x i64> %a602}603 604define <vscale x 8 x i64> @intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {605; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8i64_nxv8i64:606; CHECK: # %bb.0: # %entry607; CHECK-NEXT: vl2re16.v v24, (a0)608; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu609; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t610; CHECK-NEXT: ret611entry:612 %a = call <vscale x 8 x i64> @llvm.riscv.vrgatherei16.vv.mask.nxv8i64(613 <vscale x 8 x i64> %0,614 <vscale x 8 x i64> %1,615 <vscale x 8 x i16> %2,616 <vscale x 8 x i1> %3,617 iXLen %4, iXLen 1)618 619 ret <vscale x 8 x i64> %a620}621 622define <vscale x 1 x half> @intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {623; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f16_nxv1f16:624; CHECK: # %bb.0: # %entry625; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma626; CHECK-NEXT: vrgatherei16.vv v10, v8, v9627; CHECK-NEXT: vmv1r.v v8, v10628; CHECK-NEXT: ret629entry:630 %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.nxv1f16(631 <vscale x 1 x half> poison,632 <vscale x 1 x half> %0,633 <vscale x 1 x i16> %1,634 iXLen %2)635 636 ret <vscale x 1 x half> %a637}638 639define <vscale x 1 x half> @intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {640; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f16_nxv1f16:641; CHECK: # %bb.0: # %entry642; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu643; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t644; CHECK-NEXT: ret645entry:646 %a = call <vscale x 1 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv1f16(647 <vscale x 1 x half> %0,648 <vscale x 1 x half> %1,649 <vscale x 1 x i16> %2,650 <vscale x 1 x i1> %3,651 iXLen %4, iXLen 1)652 653 ret <vscale x 1 x half> %a654}655 656define <vscale x 2 x half> @intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {657; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2f16_nxv2f16:658; CHECK: # %bb.0: # %entry659; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma660; CHECK-NEXT: vrgatherei16.vv v10, v8, v9661; CHECK-NEXT: vmv1r.v v8, v10662; CHECK-NEXT: ret663entry:664 %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.nxv2f16(665 <vscale x 2 x half> poison,666 <vscale x 2 x half> %0,667 <vscale x 2 x i16> %1,668 iXLen %2)669 670 ret <vscale x 2 x half> %a671}672 673define <vscale x 2 x half> @intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {674; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2f16_nxv2f16:675; CHECK: # %bb.0: # %entry676; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu677; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t678; CHECK-NEXT: ret679entry:680 %a = call <vscale x 2 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv2f16(681 <vscale x 2 x half> %0,682 <vscale x 2 x half> %1,683 <vscale x 2 x i16> %2,684 <vscale x 2 x i1> %3,685 iXLen %4, iXLen 1)686 687 ret <vscale x 2 x half> %a688}689 690define <vscale x 4 x half> @intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {691; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f16_nxv4f16:692; CHECK: # %bb.0: # %entry693; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma694; CHECK-NEXT: vrgatherei16.vv v10, v8, v9695; CHECK-NEXT: vmv.v.v v8, v10696; CHECK-NEXT: ret697entry:698 %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.nxv4f16(699 <vscale x 4 x half> poison,700 <vscale x 4 x half> %0,701 <vscale x 4 x i16> %1,702 iXLen %2)703 704 ret <vscale x 4 x half> %a705}706 707define <vscale x 4 x half> @intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {708; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f16_nxv4f16:709; CHECK: # %bb.0: # %entry710; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu711; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t712; CHECK-NEXT: ret713entry:714 %a = call <vscale x 4 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv4f16(715 <vscale x 4 x half> %0,716 <vscale x 4 x half> %1,717 <vscale x 4 x i16> %2,718 <vscale x 4 x i1> %3,719 iXLen %4, iXLen 1)720 721 ret <vscale x 4 x half> %a722}723 724define <vscale x 8 x half> @intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {725; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f16_nxv8f16:726; CHECK: # %bb.0: # %entry727; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma728; CHECK-NEXT: vrgatherei16.vv v12, v8, v10729; CHECK-NEXT: vmv.v.v v8, v12730; CHECK-NEXT: ret731entry:732 %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.nxv8f16(733 <vscale x 8 x half> poison,734 <vscale x 8 x half> %0,735 <vscale x 8 x i16> %1,736 iXLen %2)737 738 ret <vscale x 8 x half> %a739}740 741define <vscale x 8 x half> @intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {742; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f16_nxv8f16:743; CHECK: # %bb.0: # %entry744; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu745; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t746; CHECK-NEXT: ret747entry:748 %a = call <vscale x 8 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv8f16(749 <vscale x 8 x half> %0,750 <vscale x 8 x half> %1,751 <vscale x 8 x i16> %2,752 <vscale x 8 x i1> %3,753 iXLen %4, iXLen 1)754 755 ret <vscale x 8 x half> %a756}757 758define <vscale x 16 x half> @intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {759; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f16_nxv16f16:760; CHECK: # %bb.0: # %entry761; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma762; CHECK-NEXT: vrgatherei16.vv v16, v8, v12763; CHECK-NEXT: vmv.v.v v8, v16764; CHECK-NEXT: ret765entry:766 %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.nxv16f16(767 <vscale x 16 x half> poison,768 <vscale x 16 x half> %0,769 <vscale x 16 x i16> %1,770 iXLen %2)771 772 ret <vscale x 16 x half> %a773}774 775define <vscale x 16 x half> @intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {776; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f16_nxv16f16:777; CHECK: # %bb.0: # %entry778; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu779; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t780; CHECK-NEXT: ret781entry:782 %a = call <vscale x 16 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv16f16(783 <vscale x 16 x half> %0,784 <vscale x 16 x half> %1,785 <vscale x 16 x i16> %2,786 <vscale x 16 x i1> %3,787 iXLen %4, iXLen 1)788 789 ret <vscale x 16 x half> %a790}791 792define <vscale x 32 x half> @intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {793; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32f16_nxv32f16:794; CHECK: # %bb.0: # %entry795; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma796; CHECK-NEXT: vrgatherei16.vv v24, v8, v16797; CHECK-NEXT: vmv.v.v v8, v24798; CHECK-NEXT: ret799entry:800 %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.nxv32f16(801 <vscale x 32 x half> poison,802 <vscale x 32 x half> %0,803 <vscale x 32 x i16> %1,804 iXLen %2)805 806 ret <vscale x 32 x half> %a807}808 809define <vscale x 32 x half> @intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {810; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32f16_nxv32f16:811; CHECK: # %bb.0: # %entry812; CHECK-NEXT: vl8re16.v v24, (a0)813; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu814; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t815; CHECK-NEXT: ret816entry:817 %a = call <vscale x 32 x half> @llvm.riscv.vrgatherei16.vv.mask.nxv32f16(818 <vscale x 32 x half> %0,819 <vscale x 32 x half> %1,820 <vscale x 32 x i16> %2,821 <vscale x 32 x i1> %3,822 iXLen %4, iXLen 1)823 824 ret <vscale x 32 x half> %a825}826 827define <vscale x 1 x float> @intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {828; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1f32_nxv1f32:829; CHECK: # %bb.0: # %entry830; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma831; CHECK-NEXT: vrgatherei16.vv v10, v8, v9832; CHECK-NEXT: vmv1r.v v8, v10833; CHECK-NEXT: ret834entry:835 %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.nxv1f32(836 <vscale x 1 x float> poison,837 <vscale x 1 x float> %0,838 <vscale x 1 x i16> %1,839 iXLen %2)840 841 ret <vscale x 1 x float> %a842}843 844define <vscale x 1 x float> @intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {845; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1f32_nxv1f32:846; CHECK: # %bb.0: # %entry847; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu848; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t849; CHECK-NEXT: ret850entry:851 %a = call <vscale x 1 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv1f32(852 <vscale x 1 x float> %0,853 <vscale x 1 x float> %1,854 <vscale x 1 x i16> %2,855 <vscale x 1 x i1> %3,856 iXLen %4, iXLen 1)857 858 ret <vscale x 1 x float> %a859}860 861define <vscale x 4 x float> @intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {862; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f32_nxv4f32:863; CHECK: # %bb.0: # %entry864; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma865; CHECK-NEXT: vrgatherei16.vv v12, v8, v10866; CHECK-NEXT: vmv.v.v v8, v12867; CHECK-NEXT: ret868entry:869 %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.nxv4f32(870 <vscale x 4 x float> poison,871 <vscale x 4 x float> %0,872 <vscale x 4 x i16> %1,873 iXLen %2)874 875 ret <vscale x 4 x float> %a876}877 878define <vscale x 4 x float> @intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {879; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f32_nxv4f32:880; CHECK: # %bb.0: # %entry881; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu882; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t883; CHECK-NEXT: ret884entry:885 %a = call <vscale x 4 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv4f32(886 <vscale x 4 x float> %0,887 <vscale x 4 x float> %1,888 <vscale x 4 x i16> %2,889 <vscale x 4 x i1> %3,890 iXLen %4, iXLen 1)891 892 ret <vscale x 4 x float> %a893}894 895define <vscale x 8 x float> @intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {896; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f32_nxv8f32:897; CHECK: # %bb.0: # %entry898; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma899; CHECK-NEXT: vrgatherei16.vv v16, v8, v12900; CHECK-NEXT: vmv.v.v v8, v16901; CHECK-NEXT: ret902entry:903 %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.nxv8f32(904 <vscale x 8 x float> poison,905 <vscale x 8 x float> %0,906 <vscale x 8 x i16> %1,907 iXLen %2)908 909 ret <vscale x 8 x float> %a910}911 912define <vscale x 8 x float> @intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {913; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f32_nxv8f32:914; CHECK: # %bb.0: # %entry915; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu916; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t917; CHECK-NEXT: ret918entry:919 %a = call <vscale x 8 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv8f32(920 <vscale x 8 x float> %0,921 <vscale x 8 x float> %1,922 <vscale x 8 x i16> %2,923 <vscale x 8 x i1> %3,924 iXLen %4, iXLen 1)925 926 ret <vscale x 8 x float> %a927}928 929define <vscale x 16 x float> @intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {930; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16f32_nxv16f32:931; CHECK: # %bb.0: # %entry932; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma933; CHECK-NEXT: vrgatherei16.vv v24, v8, v16934; CHECK-NEXT: vmv.v.v v8, v24935; CHECK-NEXT: ret936entry:937 %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.nxv16f32(938 <vscale x 16 x float> poison,939 <vscale x 16 x float> %0,940 <vscale x 16 x i16> %1,941 iXLen %2)942 943 ret <vscale x 16 x float> %a944}945 946define <vscale x 16 x float> @intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {947; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16f32_nxv16f32:948; CHECK: # %bb.0: # %entry949; CHECK-NEXT: vl4re16.v v24, (a0)950; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu951; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t952; CHECK-NEXT: ret953entry:954 %a = call <vscale x 16 x float> @llvm.riscv.vrgatherei16.vv.mask.nxv16f32(955 <vscale x 16 x float> %0,956 <vscale x 16 x float> %1,957 <vscale x 16 x i16> %2,958 <vscale x 16 x i1> %3,959 iXLen %4, iXLen 1)960 961 ret <vscale x 16 x float> %a962}963 964define <vscale x 4 x double> @intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {965; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4f64_nxv4f64:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma968; CHECK-NEXT: vrgatherei16.vv v16, v8, v12969; CHECK-NEXT: vmv.v.v v8, v16970; CHECK-NEXT: ret971entry:972 %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.nxv4f64(973 <vscale x 4 x double> poison,974 <vscale x 4 x double> %0,975 <vscale x 4 x i16> %1,976 iXLen %2)977 978 ret <vscale x 4 x double> %a979}980 981define <vscale x 4 x double> @intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {982; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4f64_nxv4f64:983; CHECK: # %bb.0: # %entry984; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu985; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t986; CHECK-NEXT: ret987entry:988 %a = call <vscale x 4 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv4f64(989 <vscale x 4 x double> %0,990 <vscale x 4 x double> %1,991 <vscale x 4 x i16> %2,992 <vscale x 4 x i1> %3,993 iXLen %4, iXLen 1)994 995 ret <vscale x 4 x double> %a996}997 998define <vscale x 8 x double> @intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {999; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8f64_nxv8f64:1000; CHECK: # %bb.0: # %entry1001; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1002; CHECK-NEXT: vrgatherei16.vv v24, v8, v161003; CHECK-NEXT: vmv.v.v v8, v241004; CHECK-NEXT: ret1005entry:1006 %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.nxv8f64(1007 <vscale x 8 x double> poison,1008 <vscale x 8 x double> %0,1009 <vscale x 8 x i16> %1,1010 iXLen %2)1011 1012 ret <vscale x 8 x double> %a1013}1014 1015define <vscale x 8 x double> @intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1016; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8f64_nxv8f64:1017; CHECK: # %bb.0: # %entry1018; CHECK-NEXT: vl2re16.v v24, (a0)1019; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu1020; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t1021; CHECK-NEXT: ret1022entry:1023 %a = call <vscale x 8 x double> @llvm.riscv.vrgatherei16.vv.mask.nxv8f64(1024 <vscale x 8 x double> %0,1025 <vscale x 8 x double> %1,1026 <vscale x 8 x i16> %2,1027 <vscale x 8 x i1> %3,1028 iXLen %4, iXLen 1)1029 1030 ret <vscale x 8 x double> %a1031}1032 1033define <vscale x 1 x bfloat> @intrinsic_vrgatherei16_vv_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {1034; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv1bf16_nxv1bf16:1035; CHECK: # %bb.0: # %entry1036; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1037; CHECK-NEXT: vrgatherei16.vv v10, v8, v91038; CHECK-NEXT: vmv1r.v v8, v101039; CHECK-NEXT: ret1040entry:1041 %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv1bf16(1042 <vscale x 1 x bfloat> poison,1043 <vscale x 1 x bfloat> %0,1044 <vscale x 1 x i16> %1,1045 iXLen %2)1046 1047 ret <vscale x 1 x bfloat> %a1048}1049 1050define <vscale x 1 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1051; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv1bf16_nxv1bf16:1052; CHECK: # %bb.0: # %entry1053; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1054; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t1055; CHECK-NEXT: ret1056entry:1057 %a = call <vscale x 1 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv1bf16(1058 <vscale x 1 x bfloat> %0,1059 <vscale x 1 x bfloat> %1,1060 <vscale x 1 x i16> %2,1061 <vscale x 1 x i1> %3,1062 iXLen %4, iXLen 1)1063 1064 ret <vscale x 1 x bfloat> %a1065}1066 1067define <vscale x 2 x bfloat> @intrinsic_vrgatherei16_vv_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {1068; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv2bf16_nxv2bf16:1069; CHECK: # %bb.0: # %entry1070; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1071; CHECK-NEXT: vrgatherei16.vv v10, v8, v91072; CHECK-NEXT: vmv1r.v v8, v101073; CHECK-NEXT: ret1074entry:1075 %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv2bf16(1076 <vscale x 2 x bfloat> poison,1077 <vscale x 2 x bfloat> %0,1078 <vscale x 2 x i16> %1,1079 iXLen %2)1080 1081 ret <vscale x 2 x bfloat> %a1082}1083 1084define <vscale x 2 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1085; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv2bf16_nxv2bf16:1086; CHECK: # %bb.0: # %entry1087; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1088; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t1089; CHECK-NEXT: ret1090entry:1091 %a = call <vscale x 2 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv2bf16(1092 <vscale x 2 x bfloat> %0,1093 <vscale x 2 x bfloat> %1,1094 <vscale x 2 x i16> %2,1095 <vscale x 2 x i1> %3,1096 iXLen %4, iXLen 1)1097 1098 ret <vscale x 2 x bfloat> %a1099}1100 1101define <vscale x 4 x bfloat> @intrinsic_vrgatherei16_vv_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {1102; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv4bf16_nxv4bf16:1103; CHECK: # %bb.0: # %entry1104; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1105; CHECK-NEXT: vrgatherei16.vv v10, v8, v91106; CHECK-NEXT: vmv.v.v v8, v101107; CHECK-NEXT: ret1108entry:1109 %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv4bf16(1110 <vscale x 4 x bfloat> poison,1111 <vscale x 4 x bfloat> %0,1112 <vscale x 4 x i16> %1,1113 iXLen %2)1114 1115 ret <vscale x 4 x bfloat> %a1116}1117 1118define <vscale x 4 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1119; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv4bf16_nxv4bf16:1120; CHECK: # %bb.0: # %entry1121; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1122; CHECK-NEXT: vrgatherei16.vv v8, v9, v10, v0.t1123; CHECK-NEXT: ret1124entry:1125 %a = call <vscale x 4 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv4bf16(1126 <vscale x 4 x bfloat> %0,1127 <vscale x 4 x bfloat> %1,1128 <vscale x 4 x i16> %2,1129 <vscale x 4 x i1> %3,1130 iXLen %4, iXLen 1)1131 1132 ret <vscale x 4 x bfloat> %a1133}1134 1135define <vscale x 8 x bfloat> @intrinsic_vrgatherei16_vv_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {1136; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv8bf16_nxv8bf16:1137; CHECK: # %bb.0: # %entry1138; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1139; CHECK-NEXT: vrgatherei16.vv v12, v8, v101140; CHECK-NEXT: vmv.v.v v8, v121141; CHECK-NEXT: ret1142entry:1143 %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv8bf16(1144 <vscale x 8 x bfloat> poison,1145 <vscale x 8 x bfloat> %0,1146 <vscale x 8 x i16> %1,1147 iXLen %2)1148 1149 ret <vscale x 8 x bfloat> %a1150}1151 1152define <vscale x 8 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1153; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv8bf16_nxv8bf16:1154; CHECK: # %bb.0: # %entry1155; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1156; CHECK-NEXT: vrgatherei16.vv v8, v10, v12, v0.t1157; CHECK-NEXT: ret1158entry:1159 %a = call <vscale x 8 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv8bf16(1160 <vscale x 8 x bfloat> %0,1161 <vscale x 8 x bfloat> %1,1162 <vscale x 8 x i16> %2,1163 <vscale x 8 x i1> %3,1164 iXLen %4, iXLen 1)1165 1166 ret <vscale x 8 x bfloat> %a1167}1168 1169define <vscale x 16 x bfloat> @intrinsic_vrgatherei16_vv_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {1170; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv16bf16_nxv16bf16:1171; CHECK: # %bb.0: # %entry1172; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1173; CHECK-NEXT: vrgatherei16.vv v16, v8, v121174; CHECK-NEXT: vmv.v.v v8, v161175; CHECK-NEXT: ret1176entry:1177 %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv16bf16(1178 <vscale x 16 x bfloat> poison,1179 <vscale x 16 x bfloat> %0,1180 <vscale x 16 x i16> %1,1181 iXLen %2)1182 1183 ret <vscale x 16 x bfloat> %a1184}1185 1186define <vscale x 16 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1187; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv16bf16_nxv16bf16:1188; CHECK: # %bb.0: # %entry1189; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1190; CHECK-NEXT: vrgatherei16.vv v8, v12, v16, v0.t1191; CHECK-NEXT: ret1192entry:1193 %a = call <vscale x 16 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv16bf16(1194 <vscale x 16 x bfloat> %0,1195 <vscale x 16 x bfloat> %1,1196 <vscale x 16 x i16> %2,1197 <vscale x 16 x i1> %3,1198 iXLen %4, iXLen 1)1199 1200 ret <vscale x 16 x bfloat> %a1201}1202 1203define <vscale x 32 x bfloat> @intrinsic_vrgatherei16_vv_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {1204; CHECK-LABEL: intrinsic_vrgatherei16_vv_nxv32bf16_nxv32bf16:1205; CHECK: # %bb.0: # %entry1206; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1207; CHECK-NEXT: vrgatherei16.vv v24, v8, v161208; CHECK-NEXT: vmv.v.v v8, v241209; CHECK-NEXT: ret1210entry:1211 %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.nxv32bf16(1212 <vscale x 32 x bfloat> poison,1213 <vscale x 32 x bfloat> %0,1214 <vscale x 32 x i16> %1,1215 iXLen %2)1216 1217 ret <vscale x 32 x bfloat> %a1218}1219 1220define <vscale x 32 x bfloat> @intrinsic_vrgatherei16_mask_vv_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, <vscale x 32 x bfloat> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1221; CHECK-LABEL: intrinsic_vrgatherei16_mask_vv_nxv32bf16_nxv32bf16:1222; CHECK: # %bb.0: # %entry1223; CHECK-NEXT: vl8re16.v v24, (a0)1224; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1225; CHECK-NEXT: vrgatherei16.vv v8, v16, v24, v0.t1226; CHECK-NEXT: ret1227entry:1228 %a = call <vscale x 32 x bfloat> @llvm.riscv.vrgatherei16.vv.mask.nxv32bf16(1229 <vscale x 32 x bfloat> %0,1230 <vscale x 32 x bfloat> %1,1231 <vscale x 32 x i16> %2,1232 <vscale x 32 x i1> %3,1233 iXLen %4, iXLen 1)1234 1235 ret <vscale x 32 x bfloat> %a1236}1237