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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB6 7define <vscale x 1 x i8> @vrol_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {8; CHECK-LABEL: vrol_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vand.vi v10, v9, 712; CHECK-NEXT: vrsub.vi v9, v9, 013; CHECK-NEXT: vsll.vv v10, v8, v1014; CHECK-NEXT: vand.vi v9, v9, 715; CHECK-NEXT: vsrl.vv v8, v8, v916; CHECK-NEXT: vor.vv v8, v10, v817; CHECK-NEXT: ret18;19; CHECK-ZVKB-LABEL: vrol_vv_nxv1i8:20; CHECK-ZVKB: # %bb.0:21; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma22; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v923; CHECK-ZVKB-NEXT: ret24 %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)25 ret <vscale x 1 x i8> %x26}27 28define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {29; CHECK-LABEL: vrol_vx_nxv1i8:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma32; CHECK-NEXT: vmv.v.x v9, a033; CHECK-NEXT: vand.vi v10, v9, 734; CHECK-NEXT: vrsub.vi v9, v9, 035; CHECK-NEXT: vsll.vv v10, v8, v1036; CHECK-NEXT: vand.vi v9, v9, 737; CHECK-NEXT: vsrl.vv v8, v8, v938; CHECK-NEXT: vor.vv v8, v10, v839; CHECK-NEXT: ret40;41; CHECK-ZVKB-LABEL: vrol_vx_nxv1i8:42; CHECK-ZVKB: # %bb.0:43; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma44; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a045; CHECK-ZVKB-NEXT: ret46 %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 047 %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer48 %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)49 ret <vscale x 1 x i8> %x50}51 52define <vscale x 2 x i8> @vrol_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {53; CHECK-LABEL: vrol_vv_nxv2i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma56; CHECK-NEXT: vand.vi v10, v9, 757; CHECK-NEXT: vrsub.vi v9, v9, 058; CHECK-NEXT: vsll.vv v10, v8, v1059; CHECK-NEXT: vand.vi v9, v9, 760; CHECK-NEXT: vsrl.vv v8, v8, v961; CHECK-NEXT: vor.vv v8, v10, v862; CHECK-NEXT: ret63;64; CHECK-ZVKB-LABEL: vrol_vv_nxv2i8:65; CHECK-ZVKB: # %bb.0:66; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma67; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v968; CHECK-ZVKB-NEXT: ret69 %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)70 ret <vscale x 2 x i8> %x71}72 73define <vscale x 2 x i8> @vrol_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {74; CHECK-LABEL: vrol_vx_nxv2i8:75; CHECK: # %bb.0:76; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma77; CHECK-NEXT: vmv.v.x v9, a078; CHECK-NEXT: vand.vi v10, v9, 779; CHECK-NEXT: vrsub.vi v9, v9, 080; CHECK-NEXT: vsll.vv v10, v8, v1081; CHECK-NEXT: vand.vi v9, v9, 782; CHECK-NEXT: vsrl.vv v8, v8, v983; CHECK-NEXT: vor.vv v8, v10, v884; CHECK-NEXT: ret85;86; CHECK-ZVKB-LABEL: vrol_vx_nxv2i8:87; CHECK-ZVKB: # %bb.0:88; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma89; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a090; CHECK-ZVKB-NEXT: ret91 %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 092 %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer93 %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)94 ret <vscale x 2 x i8> %x95}96 97define <vscale x 4 x i8> @vrol_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {98; CHECK-LABEL: vrol_vv_nxv4i8:99; CHECK: # %bb.0:100; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma101; CHECK-NEXT: vand.vi v10, v9, 7102; CHECK-NEXT: vrsub.vi v9, v9, 0103; CHECK-NEXT: vsll.vv v10, v8, v10104; CHECK-NEXT: vand.vi v9, v9, 7105; CHECK-NEXT: vsrl.vv v8, v8, v9106; CHECK-NEXT: vor.vv v8, v10, v8107; CHECK-NEXT: ret108;109; CHECK-ZVKB-LABEL: vrol_vv_nxv4i8:110; CHECK-ZVKB: # %bb.0:111; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma112; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9113; CHECK-ZVKB-NEXT: ret114 %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)115 ret <vscale x 4 x i8> %x116}117 118define <vscale x 4 x i8> @vrol_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {119; CHECK-LABEL: vrol_vx_nxv4i8:120; CHECK: # %bb.0:121; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma122; CHECK-NEXT: vmv.v.x v9, a0123; CHECK-NEXT: vand.vi v10, v9, 7124; CHECK-NEXT: vrsub.vi v9, v9, 0125; CHECK-NEXT: vsll.vv v10, v8, v10126; CHECK-NEXT: vand.vi v9, v9, 7127; CHECK-NEXT: vsrl.vv v8, v8, v9128; CHECK-NEXT: vor.vv v8, v10, v8129; CHECK-NEXT: ret130;131; CHECK-ZVKB-LABEL: vrol_vx_nxv4i8:132; CHECK-ZVKB: # %bb.0:133; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma134; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0135; CHECK-ZVKB-NEXT: ret136 %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0137 %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer138 %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)139 ret <vscale x 4 x i8> %x140}141 142define <vscale x 8 x i8> @vrol_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {143; CHECK-LABEL: vrol_vv_nxv8i8:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma146; CHECK-NEXT: vand.vi v10, v9, 7147; CHECK-NEXT: vrsub.vi v9, v9, 0148; CHECK-NEXT: vsll.vv v10, v8, v10149; CHECK-NEXT: vand.vi v9, v9, 7150; CHECK-NEXT: vsrl.vv v8, v8, v9151; CHECK-NEXT: vor.vv v8, v10, v8152; CHECK-NEXT: ret153;154; CHECK-ZVKB-LABEL: vrol_vv_nxv8i8:155; CHECK-ZVKB: # %bb.0:156; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma157; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9158; CHECK-ZVKB-NEXT: ret159 %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)160 ret <vscale x 8 x i8> %x161}162 163define <vscale x 8 x i8> @vrol_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {164; CHECK-LABEL: vrol_vx_nxv8i8:165; CHECK: # %bb.0:166; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma167; CHECK-NEXT: vmv.v.x v9, a0168; CHECK-NEXT: vand.vi v10, v9, 7169; CHECK-NEXT: vrsub.vi v9, v9, 0170; CHECK-NEXT: vsll.vv v10, v8, v10171; CHECK-NEXT: vand.vi v9, v9, 7172; CHECK-NEXT: vsrl.vv v8, v8, v9173; CHECK-NEXT: vor.vv v8, v10, v8174; CHECK-NEXT: ret175;176; CHECK-ZVKB-LABEL: vrol_vx_nxv8i8:177; CHECK-ZVKB: # %bb.0:178; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma179; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0180; CHECK-ZVKB-NEXT: ret181 %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0182 %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer183 %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)184 ret <vscale x 8 x i8> %x185}186 187define <vscale x 16 x i8> @vrol_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {188; CHECK-LABEL: vrol_vv_nxv16i8:189; CHECK: # %bb.0:190; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma191; CHECK-NEXT: vand.vi v12, v10, 7192; CHECK-NEXT: vrsub.vi v10, v10, 0193; CHECK-NEXT: vsll.vv v12, v8, v12194; CHECK-NEXT: vand.vi v10, v10, 7195; CHECK-NEXT: vsrl.vv v8, v8, v10196; CHECK-NEXT: vor.vv v8, v12, v8197; CHECK-NEXT: ret198;199; CHECK-ZVKB-LABEL: vrol_vv_nxv16i8:200; CHECK-ZVKB: # %bb.0:201; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma202; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10203; CHECK-ZVKB-NEXT: ret204 %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)205 ret <vscale x 16 x i8> %x206}207 208define <vscale x 16 x i8> @vrol_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {209; CHECK-LABEL: vrol_vx_nxv16i8:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma212; CHECK-NEXT: vmv.v.x v10, a0213; CHECK-NEXT: vand.vi v12, v10, 7214; CHECK-NEXT: vrsub.vi v10, v10, 0215; CHECK-NEXT: vsll.vv v12, v8, v12216; CHECK-NEXT: vand.vi v10, v10, 7217; CHECK-NEXT: vsrl.vv v8, v8, v10218; CHECK-NEXT: vor.vv v8, v12, v8219; CHECK-NEXT: ret220;221; CHECK-ZVKB-LABEL: vrol_vx_nxv16i8:222; CHECK-ZVKB: # %bb.0:223; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma224; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0225; CHECK-ZVKB-NEXT: ret226 %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0227 %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer228 %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)229 ret <vscale x 16 x i8> %x230}231 232define <vscale x 32 x i8> @vrol_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {233; CHECK-LABEL: vrol_vv_nxv32i8:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma236; CHECK-NEXT: vand.vi v16, v12, 7237; CHECK-NEXT: vrsub.vi v12, v12, 0238; CHECK-NEXT: vsll.vv v16, v8, v16239; CHECK-NEXT: vand.vi v12, v12, 7240; CHECK-NEXT: vsrl.vv v8, v8, v12241; CHECK-NEXT: vor.vv v8, v16, v8242; CHECK-NEXT: ret243;244; CHECK-ZVKB-LABEL: vrol_vv_nxv32i8:245; CHECK-ZVKB: # %bb.0:246; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma247; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12248; CHECK-ZVKB-NEXT: ret249 %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)250 ret <vscale x 32 x i8> %x251}252 253define <vscale x 32 x i8> @vrol_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {254; CHECK-LABEL: vrol_vx_nxv32i8:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma257; CHECK-NEXT: vmv.v.x v12, a0258; CHECK-NEXT: vand.vi v16, v12, 7259; CHECK-NEXT: vrsub.vi v12, v12, 0260; CHECK-NEXT: vsll.vv v16, v8, v16261; CHECK-NEXT: vand.vi v12, v12, 7262; CHECK-NEXT: vsrl.vv v8, v8, v12263; CHECK-NEXT: vor.vv v8, v16, v8264; CHECK-NEXT: ret265;266; CHECK-ZVKB-LABEL: vrol_vx_nxv32i8:267; CHECK-ZVKB: # %bb.0:268; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma269; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0270; CHECK-ZVKB-NEXT: ret271 %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0272 %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer273 %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)274 ret <vscale x 32 x i8> %x275}276 277define <vscale x 64 x i8> @vrol_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {278; CHECK-LABEL: vrol_vv_nxv64i8:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma281; CHECK-NEXT: vand.vi v24, v16, 7282; CHECK-NEXT: vrsub.vi v16, v16, 0283; CHECK-NEXT: vsll.vv v24, v8, v24284; CHECK-NEXT: vand.vi v16, v16, 7285; CHECK-NEXT: vsrl.vv v8, v8, v16286; CHECK-NEXT: vor.vv v8, v24, v8287; CHECK-NEXT: ret288;289; CHECK-ZVKB-LABEL: vrol_vv_nxv64i8:290; CHECK-ZVKB: # %bb.0:291; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma292; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v16293; CHECK-ZVKB-NEXT: ret294 %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)295 ret <vscale x 64 x i8> %x296}297 298define <vscale x 64 x i8> @vrol_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {299; CHECK-LABEL: vrol_vx_nxv64i8:300; CHECK: # %bb.0:301; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma302; CHECK-NEXT: vmv.v.x v16, a0303; CHECK-NEXT: vand.vi v24, v16, 7304; CHECK-NEXT: vrsub.vi v16, v16, 0305; CHECK-NEXT: vsll.vv v24, v8, v24306; CHECK-NEXT: vand.vi v16, v16, 7307; CHECK-NEXT: vsrl.vv v8, v8, v16308; CHECK-NEXT: vor.vv v8, v24, v8309; CHECK-NEXT: ret310;311; CHECK-ZVKB-LABEL: vrol_vx_nxv64i8:312; CHECK-ZVKB: # %bb.0:313; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma314; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0315; CHECK-ZVKB-NEXT: ret316 %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0317 %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer318 %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)319 ret <vscale x 64 x i8> %x320}321 322define <vscale x 1 x i16> @vrol_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {323; CHECK-LABEL: vrol_vv_nxv1i16:324; CHECK: # %bb.0:325; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma326; CHECK-NEXT: vand.vi v10, v9, 15327; CHECK-NEXT: vrsub.vi v9, v9, 0328; CHECK-NEXT: vsll.vv v10, v8, v10329; CHECK-NEXT: vand.vi v9, v9, 15330; CHECK-NEXT: vsrl.vv v8, v8, v9331; CHECK-NEXT: vor.vv v8, v10, v8332; CHECK-NEXT: ret333;334; CHECK-ZVKB-LABEL: vrol_vv_nxv1i16:335; CHECK-ZVKB: # %bb.0:336; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma337; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9338; CHECK-ZVKB-NEXT: ret339 %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)340 ret <vscale x 1 x i16> %x341}342 343define <vscale x 1 x i16> @vrol_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {344; CHECK-LABEL: vrol_vx_nxv1i16:345; CHECK: # %bb.0:346; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma347; CHECK-NEXT: vmv.v.x v9, a0348; CHECK-NEXT: vand.vi v10, v9, 15349; CHECK-NEXT: vrsub.vi v9, v9, 0350; CHECK-NEXT: vsll.vv v10, v8, v10351; CHECK-NEXT: vand.vi v9, v9, 15352; CHECK-NEXT: vsrl.vv v8, v8, v9353; CHECK-NEXT: vor.vv v8, v10, v8354; CHECK-NEXT: ret355;356; CHECK-ZVKB-LABEL: vrol_vx_nxv1i16:357; CHECK-ZVKB: # %bb.0:358; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma359; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0360; CHECK-ZVKB-NEXT: ret361 %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0362 %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer363 %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)364 ret <vscale x 1 x i16> %x365}366 367define <vscale x 2 x i16> @vrol_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {368; CHECK-LABEL: vrol_vv_nxv2i16:369; CHECK: # %bb.0:370; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma371; CHECK-NEXT: vand.vi v10, v9, 15372; CHECK-NEXT: vrsub.vi v9, v9, 0373; CHECK-NEXT: vsll.vv v10, v8, v10374; CHECK-NEXT: vand.vi v9, v9, 15375; CHECK-NEXT: vsrl.vv v8, v8, v9376; CHECK-NEXT: vor.vv v8, v10, v8377; CHECK-NEXT: ret378;379; CHECK-ZVKB-LABEL: vrol_vv_nxv2i16:380; CHECK-ZVKB: # %bb.0:381; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma382; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9383; CHECK-ZVKB-NEXT: ret384 %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)385 ret <vscale x 2 x i16> %x386}387 388define <vscale x 2 x i16> @vrol_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {389; CHECK-LABEL: vrol_vx_nxv2i16:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma392; CHECK-NEXT: vmv.v.x v9, a0393; CHECK-NEXT: vand.vi v10, v9, 15394; CHECK-NEXT: vrsub.vi v9, v9, 0395; CHECK-NEXT: vsll.vv v10, v8, v10396; CHECK-NEXT: vand.vi v9, v9, 15397; CHECK-NEXT: vsrl.vv v8, v8, v9398; CHECK-NEXT: vor.vv v8, v10, v8399; CHECK-NEXT: ret400;401; CHECK-ZVKB-LABEL: vrol_vx_nxv2i16:402; CHECK-ZVKB: # %bb.0:403; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma404; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0405; CHECK-ZVKB-NEXT: ret406 %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0407 %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer408 %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)409 ret <vscale x 2 x i16> %x410}411 412define <vscale x 4 x i16> @vrol_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {413; CHECK-LABEL: vrol_vv_nxv4i16:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma416; CHECK-NEXT: vand.vi v10, v9, 15417; CHECK-NEXT: vrsub.vi v9, v9, 0418; CHECK-NEXT: vsll.vv v10, v8, v10419; CHECK-NEXT: vand.vi v9, v9, 15420; CHECK-NEXT: vsrl.vv v8, v8, v9421; CHECK-NEXT: vor.vv v8, v10, v8422; CHECK-NEXT: ret423;424; CHECK-ZVKB-LABEL: vrol_vv_nxv4i16:425; CHECK-ZVKB: # %bb.0:426; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma427; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9428; CHECK-ZVKB-NEXT: ret429 %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)430 ret <vscale x 4 x i16> %x431}432 433define <vscale x 4 x i16> @vrol_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {434; CHECK-LABEL: vrol_vx_nxv4i16:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma437; CHECK-NEXT: vmv.v.x v9, a0438; CHECK-NEXT: vand.vi v10, v9, 15439; CHECK-NEXT: vrsub.vi v9, v9, 0440; CHECK-NEXT: vsll.vv v10, v8, v10441; CHECK-NEXT: vand.vi v9, v9, 15442; CHECK-NEXT: vsrl.vv v8, v8, v9443; CHECK-NEXT: vor.vv v8, v10, v8444; CHECK-NEXT: ret445;446; CHECK-ZVKB-LABEL: vrol_vx_nxv4i16:447; CHECK-ZVKB: # %bb.0:448; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma449; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0450; CHECK-ZVKB-NEXT: ret451 %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0452 %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer453 %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)454 ret <vscale x 4 x i16> %x455}456 457define <vscale x 8 x i16> @vrol_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {458; CHECK-LABEL: vrol_vv_nxv8i16:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma461; CHECK-NEXT: vand.vi v12, v10, 15462; CHECK-NEXT: vrsub.vi v10, v10, 0463; CHECK-NEXT: vsll.vv v12, v8, v12464; CHECK-NEXT: vand.vi v10, v10, 15465; CHECK-NEXT: vsrl.vv v8, v8, v10466; CHECK-NEXT: vor.vv v8, v12, v8467; CHECK-NEXT: ret468;469; CHECK-ZVKB-LABEL: vrol_vv_nxv8i16:470; CHECK-ZVKB: # %bb.0:471; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma472; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10473; CHECK-ZVKB-NEXT: ret474 %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)475 ret <vscale x 8 x i16> %x476}477 478define <vscale x 8 x i16> @vrol_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {479; CHECK-LABEL: vrol_vx_nxv8i16:480; CHECK: # %bb.0:481; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma482; CHECK-NEXT: vmv.v.x v10, a0483; CHECK-NEXT: vand.vi v12, v10, 15484; CHECK-NEXT: vrsub.vi v10, v10, 0485; CHECK-NEXT: vsll.vv v12, v8, v12486; CHECK-NEXT: vand.vi v10, v10, 15487; CHECK-NEXT: vsrl.vv v8, v8, v10488; CHECK-NEXT: vor.vv v8, v12, v8489; CHECK-NEXT: ret490;491; CHECK-ZVKB-LABEL: vrol_vx_nxv8i16:492; CHECK-ZVKB: # %bb.0:493; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma494; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0495; CHECK-ZVKB-NEXT: ret496 %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0497 %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer498 %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)499 ret <vscale x 8 x i16> %x500}501 502define <vscale x 16 x i16> @vrol_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {503; CHECK-LABEL: vrol_vv_nxv16i16:504; CHECK: # %bb.0:505; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma506; CHECK-NEXT: vand.vi v16, v12, 15507; CHECK-NEXT: vrsub.vi v12, v12, 0508; CHECK-NEXT: vsll.vv v16, v8, v16509; CHECK-NEXT: vand.vi v12, v12, 15510; CHECK-NEXT: vsrl.vv v8, v8, v12511; CHECK-NEXT: vor.vv v8, v16, v8512; CHECK-NEXT: ret513;514; CHECK-ZVKB-LABEL: vrol_vv_nxv16i16:515; CHECK-ZVKB: # %bb.0:516; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma517; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12518; CHECK-ZVKB-NEXT: ret519 %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)520 ret <vscale x 16 x i16> %x521}522 523define <vscale x 16 x i16> @vrol_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {524; CHECK-LABEL: vrol_vx_nxv16i16:525; CHECK: # %bb.0:526; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma527; CHECK-NEXT: vmv.v.x v12, a0528; CHECK-NEXT: vand.vi v16, v12, 15529; CHECK-NEXT: vrsub.vi v12, v12, 0530; CHECK-NEXT: vsll.vv v16, v8, v16531; CHECK-NEXT: vand.vi v12, v12, 15532; CHECK-NEXT: vsrl.vv v8, v8, v12533; CHECK-NEXT: vor.vv v8, v16, v8534; CHECK-NEXT: ret535;536; CHECK-ZVKB-LABEL: vrol_vx_nxv16i16:537; CHECK-ZVKB: # %bb.0:538; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma539; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0540; CHECK-ZVKB-NEXT: ret541 %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0542 %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer543 %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)544 ret <vscale x 16 x i16> %x545}546 547define <vscale x 32 x i16> @vrol_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {548; CHECK-LABEL: vrol_vv_nxv32i16:549; CHECK: # %bb.0:550; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma551; CHECK-NEXT: vand.vi v24, v16, 15552; CHECK-NEXT: vrsub.vi v16, v16, 0553; CHECK-NEXT: vsll.vv v24, v8, v24554; CHECK-NEXT: vand.vi v16, v16, 15555; CHECK-NEXT: vsrl.vv v8, v8, v16556; CHECK-NEXT: vor.vv v8, v24, v8557; CHECK-NEXT: ret558;559; CHECK-ZVKB-LABEL: vrol_vv_nxv32i16:560; CHECK-ZVKB: # %bb.0:561; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma562; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v16563; CHECK-ZVKB-NEXT: ret564 %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)565 ret <vscale x 32 x i16> %x566}567 568define <vscale x 32 x i16> @vrol_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {569; CHECK-LABEL: vrol_vx_nxv32i16:570; CHECK: # %bb.0:571; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma572; CHECK-NEXT: vmv.v.x v16, a0573; CHECK-NEXT: vand.vi v24, v16, 15574; CHECK-NEXT: vrsub.vi v16, v16, 0575; CHECK-NEXT: vsll.vv v24, v8, v24576; CHECK-NEXT: vand.vi v16, v16, 15577; CHECK-NEXT: vsrl.vv v8, v8, v16578; CHECK-NEXT: vor.vv v8, v24, v8579; CHECK-NEXT: ret580;581; CHECK-ZVKB-LABEL: vrol_vx_nxv32i16:582; CHECK-ZVKB: # %bb.0:583; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma584; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0585; CHECK-ZVKB-NEXT: ret586 %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0587 %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer588 %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)589 ret <vscale x 32 x i16> %x590}591 592define <vscale x 1 x i32> @vrol_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {593; CHECK-LABEL: vrol_vv_nxv1i32:594; CHECK: # %bb.0:595; CHECK-NEXT: li a0, 31596; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma597; CHECK-NEXT: vrsub.vi v10, v9, 0598; CHECK-NEXT: vand.vx v9, v9, a0599; CHECK-NEXT: vand.vx v10, v10, a0600; CHECK-NEXT: vsll.vv v9, v8, v9601; CHECK-NEXT: vsrl.vv v8, v8, v10602; CHECK-NEXT: vor.vv v8, v9, v8603; CHECK-NEXT: ret604;605; CHECK-ZVKB-LABEL: vrol_vv_nxv1i32:606; CHECK-ZVKB: # %bb.0:607; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma608; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9609; CHECK-ZVKB-NEXT: ret610 %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)611 ret <vscale x 1 x i32> %x612}613 614define <vscale x 1 x i32> @vrol_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {615; CHECK-RV32-LABEL: vrol_vx_nxv1i32:616; CHECK-RV32: # %bb.0:617; CHECK-RV32-NEXT: andi a1, a0, 31618; CHECK-RV32-NEXT: neg a0, a0619; CHECK-RV32-NEXT: vsetvli a2, zero, e32, mf2, ta, ma620; CHECK-RV32-NEXT: vsll.vx v9, v8, a1621; CHECK-RV32-NEXT: andi a0, a0, 31622; CHECK-RV32-NEXT: vsrl.vx v8, v8, a0623; CHECK-RV32-NEXT: vor.vv v8, v9, v8624; CHECK-RV32-NEXT: ret625;626; CHECK-RV64-LABEL: vrol_vx_nxv1i32:627; CHECK-RV64: # %bb.0:628; CHECK-RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma629; CHECK-RV64-NEXT: vmv.v.x v9, a0630; CHECK-RV64-NEXT: li a0, 31631; CHECK-RV64-NEXT: vand.vx v10, v9, a0632; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0633; CHECK-RV64-NEXT: vsll.vv v10, v8, v10634; CHECK-RV64-NEXT: vand.vx v9, v9, a0635; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9636; CHECK-RV64-NEXT: vor.vv v8, v10, v8637; CHECK-RV64-NEXT: ret638;639; CHECK-ZVKB-LABEL: vrol_vx_nxv1i32:640; CHECK-ZVKB: # %bb.0:641; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma642; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0643; CHECK-ZVKB-NEXT: ret644 %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0645 %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer646 %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)647 ret <vscale x 1 x i32> %x648}649 650define <vscale x 2 x i32> @vrol_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {651; CHECK-LABEL: vrol_vv_nxv2i32:652; CHECK: # %bb.0:653; CHECK-NEXT: li a0, 31654; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma655; CHECK-NEXT: vrsub.vi v10, v9, 0656; CHECK-NEXT: vand.vx v9, v9, a0657; CHECK-NEXT: vand.vx v10, v10, a0658; CHECK-NEXT: vsll.vv v9, v8, v9659; CHECK-NEXT: vsrl.vv v8, v8, v10660; CHECK-NEXT: vor.vv v8, v9, v8661; CHECK-NEXT: ret662;663; CHECK-ZVKB-LABEL: vrol_vv_nxv2i32:664; CHECK-ZVKB: # %bb.0:665; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma666; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9667; CHECK-ZVKB-NEXT: ret668 %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)669 ret <vscale x 2 x i32> %x670}671 672define <vscale x 2 x i32> @vrol_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {673; CHECK-RV32-LABEL: vrol_vx_nxv2i32:674; CHECK-RV32: # %bb.0:675; CHECK-RV32-NEXT: andi a1, a0, 31676; CHECK-RV32-NEXT: neg a0, a0677; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma678; CHECK-RV32-NEXT: vsll.vx v9, v8, a1679; CHECK-RV32-NEXT: andi a0, a0, 31680; CHECK-RV32-NEXT: vsrl.vx v8, v8, a0681; CHECK-RV32-NEXT: vor.vv v8, v9, v8682; CHECK-RV32-NEXT: ret683;684; CHECK-RV64-LABEL: vrol_vx_nxv2i32:685; CHECK-RV64: # %bb.0:686; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma687; CHECK-RV64-NEXT: vmv.v.x v9, a0688; CHECK-RV64-NEXT: li a0, 31689; CHECK-RV64-NEXT: vand.vx v10, v9, a0690; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0691; CHECK-RV64-NEXT: vsll.vv v10, v8, v10692; CHECK-RV64-NEXT: vand.vx v9, v9, a0693; CHECK-RV64-NEXT: vsrl.vv v8, v8, v9694; CHECK-RV64-NEXT: vor.vv v8, v10, v8695; CHECK-RV64-NEXT: ret696;697; CHECK-ZVKB-LABEL: vrol_vx_nxv2i32:698; CHECK-ZVKB: # %bb.0:699; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma700; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0701; CHECK-ZVKB-NEXT: ret702 %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0703 %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer704 %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)705 ret <vscale x 2 x i32> %x706}707 708define <vscale x 4 x i32> @vrol_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {709; CHECK-LABEL: vrol_vv_nxv4i32:710; CHECK: # %bb.0:711; CHECK-NEXT: li a0, 31712; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma713; CHECK-NEXT: vrsub.vi v12, v10, 0714; CHECK-NEXT: vand.vx v10, v10, a0715; CHECK-NEXT: vand.vx v12, v12, a0716; CHECK-NEXT: vsll.vv v10, v8, v10717; CHECK-NEXT: vsrl.vv v8, v8, v12718; CHECK-NEXT: vor.vv v8, v10, v8719; CHECK-NEXT: ret720;721; CHECK-ZVKB-LABEL: vrol_vv_nxv4i32:722; CHECK-ZVKB: # %bb.0:723; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma724; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10725; CHECK-ZVKB-NEXT: ret726 %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)727 ret <vscale x 4 x i32> %x728}729 730define <vscale x 4 x i32> @vrol_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {731; CHECK-RV32-LABEL: vrol_vx_nxv4i32:732; CHECK-RV32: # %bb.0:733; CHECK-RV32-NEXT: andi a1, a0, 31734; CHECK-RV32-NEXT: neg a0, a0735; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma736; CHECK-RV32-NEXT: vsll.vx v10, v8, a1737; CHECK-RV32-NEXT: andi a0, a0, 31738; CHECK-RV32-NEXT: vsrl.vx v8, v8, a0739; CHECK-RV32-NEXT: vor.vv v8, v10, v8740; CHECK-RV32-NEXT: ret741;742; CHECK-RV64-LABEL: vrol_vx_nxv4i32:743; CHECK-RV64: # %bb.0:744; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma745; CHECK-RV64-NEXT: vmv.v.x v10, a0746; CHECK-RV64-NEXT: li a0, 31747; CHECK-RV64-NEXT: vand.vx v12, v10, a0748; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0749; CHECK-RV64-NEXT: vsll.vv v12, v8, v12750; CHECK-RV64-NEXT: vand.vx v10, v10, a0751; CHECK-RV64-NEXT: vsrl.vv v8, v8, v10752; CHECK-RV64-NEXT: vor.vv v8, v12, v8753; CHECK-RV64-NEXT: ret754;755; CHECK-ZVKB-LABEL: vrol_vx_nxv4i32:756; CHECK-ZVKB: # %bb.0:757; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma758; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0759; CHECK-ZVKB-NEXT: ret760 %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0761 %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer762 %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)763 ret <vscale x 4 x i32> %x764}765 766define <vscale x 8 x i32> @vrol_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {767; CHECK-LABEL: vrol_vv_nxv8i32:768; CHECK: # %bb.0:769; CHECK-NEXT: li a0, 31770; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma771; CHECK-NEXT: vrsub.vi v16, v12, 0772; CHECK-NEXT: vand.vx v12, v12, a0773; CHECK-NEXT: vand.vx v16, v16, a0774; CHECK-NEXT: vsll.vv v12, v8, v12775; CHECK-NEXT: vsrl.vv v8, v8, v16776; CHECK-NEXT: vor.vv v8, v12, v8777; CHECK-NEXT: ret778;779; CHECK-ZVKB-LABEL: vrol_vv_nxv8i32:780; CHECK-ZVKB: # %bb.0:781; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma782; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v12783; CHECK-ZVKB-NEXT: ret784 %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)785 ret <vscale x 8 x i32> %x786}787 788define <vscale x 8 x i32> @vrol_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {789; CHECK-RV32-LABEL: vrol_vx_nxv8i32:790; CHECK-RV32: # %bb.0:791; CHECK-RV32-NEXT: andi a1, a0, 31792; CHECK-RV32-NEXT: neg a0, a0793; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma794; CHECK-RV32-NEXT: vsll.vx v12, v8, a1795; CHECK-RV32-NEXT: andi a0, a0, 31796; CHECK-RV32-NEXT: vsrl.vx v8, v8, a0797; CHECK-RV32-NEXT: vor.vv v8, v12, v8798; CHECK-RV32-NEXT: ret799;800; CHECK-RV64-LABEL: vrol_vx_nxv8i32:801; CHECK-RV64: # %bb.0:802; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma803; CHECK-RV64-NEXT: vmv.v.x v12, a0804; CHECK-RV64-NEXT: li a0, 31805; CHECK-RV64-NEXT: vand.vx v16, v12, a0806; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0807; CHECK-RV64-NEXT: vsll.vv v16, v8, v16808; CHECK-RV64-NEXT: vand.vx v12, v12, a0809; CHECK-RV64-NEXT: vsrl.vv v8, v8, v12810; CHECK-RV64-NEXT: vor.vv v8, v16, v8811; CHECK-RV64-NEXT: ret812;813; CHECK-ZVKB-LABEL: vrol_vx_nxv8i32:814; CHECK-ZVKB: # %bb.0:815; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma816; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0817; CHECK-ZVKB-NEXT: ret818 %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0819 %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer820 %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)821 ret <vscale x 8 x i32> %x822}823 824define <vscale x 16 x i32> @vrol_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {825; CHECK-LABEL: vrol_vv_nxv16i32:826; CHECK: # %bb.0:827; CHECK-NEXT: li a0, 31828; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma829; CHECK-NEXT: vrsub.vi v24, v16, 0830; CHECK-NEXT: vand.vx v16, v16, a0831; CHECK-NEXT: vand.vx v24, v24, a0832; CHECK-NEXT: vsll.vv v16, v8, v16833; CHECK-NEXT: vsrl.vv v8, v8, v24834; CHECK-NEXT: vor.vv v8, v16, v8835; CHECK-NEXT: ret836;837; CHECK-ZVKB-LABEL: vrol_vv_nxv16i32:838; CHECK-ZVKB: # %bb.0:839; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma840; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v16841; CHECK-ZVKB-NEXT: ret842 %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)843 ret <vscale x 16 x i32> %x844}845 846define <vscale x 16 x i32> @vrol_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {847; CHECK-RV32-LABEL: vrol_vx_nxv16i32:848; CHECK-RV32: # %bb.0:849; CHECK-RV32-NEXT: andi a1, a0, 31850; CHECK-RV32-NEXT: neg a0, a0851; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma852; CHECK-RV32-NEXT: vsll.vx v16, v8, a1853; CHECK-RV32-NEXT: andi a0, a0, 31854; CHECK-RV32-NEXT: vsrl.vx v8, v8, a0855; CHECK-RV32-NEXT: vor.vv v8, v16, v8856; CHECK-RV32-NEXT: ret857;858; CHECK-RV64-LABEL: vrol_vx_nxv16i32:859; CHECK-RV64: # %bb.0:860; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma861; CHECK-RV64-NEXT: vmv.v.x v16, a0862; CHECK-RV64-NEXT: li a0, 31863; CHECK-RV64-NEXT: vand.vx v24, v16, a0864; CHECK-RV64-NEXT: vrsub.vi v16, v16, 0865; CHECK-RV64-NEXT: vsll.vv v24, v8, v24866; CHECK-RV64-NEXT: vand.vx v16, v16, a0867; CHECK-RV64-NEXT: vsrl.vv v8, v8, v16868; CHECK-RV64-NEXT: vor.vv v8, v24, v8869; CHECK-RV64-NEXT: ret870;871; CHECK-ZVKB-LABEL: vrol_vx_nxv16i32:872; CHECK-ZVKB: # %bb.0:873; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma874; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0875; CHECK-ZVKB-NEXT: ret876 %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0877 %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer878 %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)879 ret <vscale x 16 x i32> %x880}881 882define <vscale x 1 x i64> @vrol_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {883; CHECK-LABEL: vrol_vv_nxv1i64:884; CHECK: # %bb.0:885; CHECK-NEXT: li a0, 63886; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma887; CHECK-NEXT: vrsub.vi v10, v9, 0888; CHECK-NEXT: vand.vx v9, v9, a0889; CHECK-NEXT: vand.vx v10, v10, a0890; CHECK-NEXT: vsll.vv v9, v8, v9891; CHECK-NEXT: vsrl.vv v8, v8, v10892; CHECK-NEXT: vor.vv v8, v9, v8893; CHECK-NEXT: ret894;895; CHECK-ZVKB-LABEL: vrol_vv_nxv1i64:896; CHECK-ZVKB: # %bb.0:897; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma898; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v9899; CHECK-ZVKB-NEXT: ret900 %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)901 ret <vscale x 1 x i64> %x902}903 904define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {905; CHECK-RV32-LABEL: vrol_vx_nxv1i64:906; CHECK-RV32: # %bb.0:907; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma908; CHECK-RV32-NEXT: vmv.v.x v9, a0909; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma910; CHECK-RV32-NEXT: vmv.v.i v10, 0911; CHECK-RV32-NEXT: vwsub.vx v11, v10, a0912; CHECK-RV32-NEXT: li a0, 63913; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma914; CHECK-RV32-NEXT: vand.vx v9, v9, a0915; CHECK-RV32-NEXT: vand.vx v10, v11, a0916; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10917; CHECK-RV32-NEXT: vsll.vv v8, v8, v9918; CHECK-RV32-NEXT: vor.vv v8, v8, v10919; CHECK-RV32-NEXT: ret920;921; CHECK-RV64-LABEL: vrol_vx_nxv1i64:922; CHECK-RV64: # %bb.0:923; CHECK-RV64-NEXT: andi a1, a0, 63924; CHECK-RV64-NEXT: neg a0, a0925; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m1, ta, ma926; CHECK-RV64-NEXT: vsll.vx v9, v8, a1927; CHECK-RV64-NEXT: andi a0, a0, 63928; CHECK-RV64-NEXT: vsrl.vx v8, v8, a0929; CHECK-RV64-NEXT: vor.vv v8, v9, v8930; CHECK-RV64-NEXT: ret931;932; CHECK-ZVKB-LABEL: vrol_vx_nxv1i64:933; CHECK-ZVKB: # %bb.0:934; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m1, ta, ma935; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0936; CHECK-ZVKB-NEXT: ret937 %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0938 %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer939 %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)940 ret <vscale x 1 x i64> %x941}942 943define <vscale x 2 x i64> @vrol_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {944; CHECK-LABEL: vrol_vv_nxv2i64:945; CHECK: # %bb.0:946; CHECK-NEXT: li a0, 63947; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma948; CHECK-NEXT: vrsub.vi v12, v10, 0949; CHECK-NEXT: vand.vx v10, v10, a0950; CHECK-NEXT: vand.vx v12, v12, a0951; CHECK-NEXT: vsll.vv v10, v8, v10952; CHECK-NEXT: vsrl.vv v8, v8, v12953; CHECK-NEXT: vor.vv v8, v10, v8954; CHECK-NEXT: ret955;956; CHECK-ZVKB-LABEL: vrol_vv_nxv2i64:957; CHECK-ZVKB: # %bb.0:958; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma959; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v10960; CHECK-ZVKB-NEXT: ret961 %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)962 ret <vscale x 2 x i64> %x963}964 965define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {966; CHECK-RV32-LABEL: vrol_vx_nxv2i64:967; CHECK-RV32: # %bb.0:968; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma969; CHECK-RV32-NEXT: vmv.v.x v10, a0970; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma971; CHECK-RV32-NEXT: vmv.v.i v14, 0972; CHECK-RV32-NEXT: vwsub.vx v12, v14, a0973; CHECK-RV32-NEXT: li a0, 63974; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma975; CHECK-RV32-NEXT: vand.vx v10, v10, a0976; CHECK-RV32-NEXT: vand.vx v12, v12, a0977; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12978; CHECK-RV32-NEXT: vsll.vv v8, v8, v10979; CHECK-RV32-NEXT: vor.vv v8, v8, v12980; CHECK-RV32-NEXT: ret981;982; CHECK-RV64-LABEL: vrol_vx_nxv2i64:983; CHECK-RV64: # %bb.0:984; CHECK-RV64-NEXT: andi a1, a0, 63985; CHECK-RV64-NEXT: neg a0, a0986; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m2, ta, ma987; CHECK-RV64-NEXT: vsll.vx v10, v8, a1988; CHECK-RV64-NEXT: andi a0, a0, 63989; CHECK-RV64-NEXT: vsrl.vx v8, v8, a0990; CHECK-RV64-NEXT: vor.vv v8, v10, v8991; CHECK-RV64-NEXT: ret992;993; CHECK-ZVKB-LABEL: vrol_vx_nxv2i64:994; CHECK-ZVKB: # %bb.0:995; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m2, ta, ma996; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a0997; CHECK-ZVKB-NEXT: ret998 %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0999 %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1000 %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)1001 ret <vscale x 2 x i64> %x1002}1003 1004define <vscale x 4 x i64> @vrol_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {1005; CHECK-LABEL: vrol_vv_nxv4i64:1006; CHECK: # %bb.0:1007; CHECK-NEXT: li a0, 631008; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma1009; CHECK-NEXT: vrsub.vi v16, v12, 01010; CHECK-NEXT: vand.vx v12, v12, a01011; CHECK-NEXT: vand.vx v16, v16, a01012; CHECK-NEXT: vsll.vv v12, v8, v121013; CHECK-NEXT: vsrl.vv v8, v8, v161014; CHECK-NEXT: vor.vv v8, v12, v81015; CHECK-NEXT: ret1016;1017; CHECK-ZVKB-LABEL: vrol_vv_nxv4i64:1018; CHECK-ZVKB: # %bb.0:1019; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1020; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v121021; CHECK-ZVKB-NEXT: ret1022 %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)1023 ret <vscale x 4 x i64> %x1024}1025 1026define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {1027; CHECK-RV32-LABEL: vrol_vx_nxv4i64:1028; CHECK-RV32: # %bb.0:1029; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1030; CHECK-RV32-NEXT: vmv.v.x v12, a01031; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1032; CHECK-RV32-NEXT: vmv.v.i v20, 01033; CHECK-RV32-NEXT: vwsub.vx v16, v20, a01034; CHECK-RV32-NEXT: li a0, 631035; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1036; CHECK-RV32-NEXT: vand.vx v12, v12, a01037; CHECK-RV32-NEXT: vand.vx v16, v16, a01038; CHECK-RV32-NEXT: vsrl.vv v16, v8, v161039; CHECK-RV32-NEXT: vsll.vv v8, v8, v121040; CHECK-RV32-NEXT: vor.vv v8, v8, v161041; CHECK-RV32-NEXT: ret1042;1043; CHECK-RV64-LABEL: vrol_vx_nxv4i64:1044; CHECK-RV64: # %bb.0:1045; CHECK-RV64-NEXT: andi a1, a0, 631046; CHECK-RV64-NEXT: neg a0, a01047; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m4, ta, ma1048; CHECK-RV64-NEXT: vsll.vx v12, v8, a11049; CHECK-RV64-NEXT: andi a0, a0, 631050; CHECK-RV64-NEXT: vsrl.vx v8, v8, a01051; CHECK-RV64-NEXT: vor.vv v8, v12, v81052; CHECK-RV64-NEXT: ret1053;1054; CHECK-ZVKB-LABEL: vrol_vx_nxv4i64:1055; CHECK-ZVKB: # %bb.0:1056; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m4, ta, ma1057; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a01058; CHECK-ZVKB-NEXT: ret1059 %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01060 %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1061 %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)1062 ret <vscale x 4 x i64> %x1063}1064 1065define <vscale x 8 x i64> @vrol_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {1066; CHECK-LABEL: vrol_vv_nxv8i64:1067; CHECK: # %bb.0:1068; CHECK-NEXT: li a0, 631069; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1070; CHECK-NEXT: vrsub.vi v24, v16, 01071; CHECK-NEXT: vand.vx v16, v16, a01072; CHECK-NEXT: vand.vx v24, v24, a01073; CHECK-NEXT: vsll.vv v16, v8, v161074; CHECK-NEXT: vsrl.vv v8, v8, v241075; CHECK-NEXT: vor.vv v8, v16, v81076; CHECK-NEXT: ret1077;1078; CHECK-ZVKB-LABEL: vrol_vv_nxv8i64:1079; CHECK-ZVKB: # %bb.0:1080; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1081; CHECK-ZVKB-NEXT: vrol.vv v8, v8, v161082; CHECK-ZVKB-NEXT: ret1083 %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)1084 ret <vscale x 8 x i64> %x1085}1086 1087define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {1088; CHECK-RV32-LABEL: vrol_vx_nxv8i64:1089; CHECK-RV32: # %bb.0:1090; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1091; CHECK-RV32-NEXT: vmv.v.x v16, a01092; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma1093; CHECK-RV32-NEXT: vmv.v.i v4, 01094; CHECK-RV32-NEXT: vwsub.vx v24, v4, a01095; CHECK-RV32-NEXT: li a0, 631096; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1097; CHECK-RV32-NEXT: vand.vx v16, v16, a01098; CHECK-RV32-NEXT: vand.vx v24, v24, a01099; CHECK-RV32-NEXT: vsrl.vv v24, v8, v241100; CHECK-RV32-NEXT: vsll.vv v8, v8, v161101; CHECK-RV32-NEXT: vor.vv v8, v8, v241102; CHECK-RV32-NEXT: ret1103;1104; CHECK-RV64-LABEL: vrol_vx_nxv8i64:1105; CHECK-RV64: # %bb.0:1106; CHECK-RV64-NEXT: andi a1, a0, 631107; CHECK-RV64-NEXT: neg a0, a01108; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma1109; CHECK-RV64-NEXT: vsll.vx v16, v8, a11110; CHECK-RV64-NEXT: andi a0, a0, 631111; CHECK-RV64-NEXT: vsrl.vx v8, v8, a01112; CHECK-RV64-NEXT: vor.vv v8, v16, v81113; CHECK-RV64-NEXT: ret1114;1115; CHECK-ZVKB-LABEL: vrol_vx_nxv8i64:1116; CHECK-ZVKB: # %bb.0:1117; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m8, ta, ma1118; CHECK-ZVKB-NEXT: vrol.vx v8, v8, a01119; CHECK-ZVKB-NEXT: ret1120 %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01121 %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1122 %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)1123 ret <vscale x 8 x i64> %x1124}1125