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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV644; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB5; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-ZVKB6 7define <vscale x 1 x i8> @vror_vv_nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %b) {8; CHECK-LABEL: vror_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vand.vi v10, v9, 712; CHECK-NEXT: vrsub.vi v9, v9, 013; CHECK-NEXT: vsrl.vv v10, v8, v1014; CHECK-NEXT: vand.vi v9, v9, 715; CHECK-NEXT: vsll.vv v8, v8, v916; CHECK-NEXT: vor.vv v8, v10, v817; CHECK-NEXT: ret18;19; CHECK-ZVKB-LABEL: vror_vv_nxv1i8:20; CHECK-ZVKB: # %bb.0:21; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma22; CHECK-ZVKB-NEXT: vror.vv v8, v8, v923; CHECK-ZVKB-NEXT: ret24 %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b)25 ret <vscale x 1 x i8> %x26}27 28define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {29; CHECK-LABEL: vror_vx_nxv1i8:30; CHECK: # %bb.0:31; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma32; CHECK-NEXT: vmv.v.x v9, a033; CHECK-NEXT: vand.vi v10, v9, 734; CHECK-NEXT: vrsub.vi v9, v9, 035; CHECK-NEXT: vsrl.vv v10, v8, v1036; CHECK-NEXT: vand.vi v9, v9, 737; CHECK-NEXT: vsll.vv v8, v8, v938; CHECK-NEXT: vor.vv v8, v10, v839; CHECK-NEXT: ret40;41; CHECK-ZVKB-LABEL: vror_vx_nxv1i8:42; CHECK-ZVKB: # %bb.0:43; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf8, ta, ma44; CHECK-ZVKB-NEXT: vror.vx v8, v8, a045; CHECK-ZVKB-NEXT: ret46 %b.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 047 %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer48 %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)49 ret <vscale x 1 x i8> %x50}51 52define <vscale x 1 x i8> @vror_vi_nxv1i8(<vscale x 1 x i8> %a) {53; CHECK-LABEL: vror_vi_nxv1i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma56; CHECK-NEXT: vsll.vi v9, v8, 757; CHECK-NEXT: vsrl.vi v8, v8, 158; CHECK-NEXT: vor.vv v8, v8, v959; CHECK-NEXT: ret60;61; CHECK-ZVKB-LABEL: vror_vi_nxv1i8:62; CHECK-ZVKB: # %bb.0:63; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma64; CHECK-ZVKB-NEXT: vror.vi v8, v8, 165; CHECK-ZVKB-NEXT: ret66 %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> splat (i8 1))67 ret <vscale x 1 x i8> %x68}69 70define <vscale x 1 x i8> @vror_vi_rotl_nxv1i8(<vscale x 1 x i8> %a) {71; CHECK-LABEL: vror_vi_rotl_nxv1i8:72; CHECK: # %bb.0:73; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma74; CHECK-NEXT: vsrl.vi v9, v8, 775; CHECK-NEXT: vadd.vv v8, v8, v876; CHECK-NEXT: vor.vv v8, v8, v977; CHECK-NEXT: ret78;79; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i8:80; CHECK-ZVKB: # %bb.0:81; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma82; CHECK-ZVKB-NEXT: vror.vi v8, v8, 783; CHECK-ZVKB-NEXT: ret84 %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> splat (i8 1))85 ret <vscale x 1 x i8> %x86}87 88define <vscale x 2 x i8> @vror_vv_nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {89; CHECK-LABEL: vror_vv_nxv2i8:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma92; CHECK-NEXT: vand.vi v10, v9, 793; CHECK-NEXT: vrsub.vi v9, v9, 094; CHECK-NEXT: vsrl.vv v10, v8, v1095; CHECK-NEXT: vand.vi v9, v9, 796; CHECK-NEXT: vsll.vv v8, v8, v997; CHECK-NEXT: vor.vv v8, v10, v898; CHECK-NEXT: ret99;100; CHECK-ZVKB-LABEL: vror_vv_nxv2i8:101; CHECK-ZVKB: # %bb.0:102; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma103; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9104; CHECK-ZVKB-NEXT: ret105 %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b)106 ret <vscale x 2 x i8> %x107}108 109define <vscale x 2 x i8> @vror_vx_nxv2i8(<vscale x 2 x i8> %a, i8 %b) {110; CHECK-LABEL: vror_vx_nxv2i8:111; CHECK: # %bb.0:112; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma113; CHECK-NEXT: vmv.v.x v9, a0114; CHECK-NEXT: vand.vi v10, v9, 7115; CHECK-NEXT: vrsub.vi v9, v9, 0116; CHECK-NEXT: vsrl.vv v10, v8, v10117; CHECK-NEXT: vand.vi v9, v9, 7118; CHECK-NEXT: vsll.vv v8, v8, v9119; CHECK-NEXT: vor.vv v8, v10, v8120; CHECK-NEXT: ret121;122; CHECK-ZVKB-LABEL: vror_vx_nxv2i8:123; CHECK-ZVKB: # %bb.0:124; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma125; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0126; CHECK-ZVKB-NEXT: ret127 %b.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0128 %b.splat = shufflevector <vscale x 2 x i8> %b.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer129 %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> %b.splat)130 ret <vscale x 2 x i8> %x131}132 133define <vscale x 2 x i8> @vror_vi_nxv2i8(<vscale x 2 x i8> %a) {134; CHECK-LABEL: vror_vi_nxv2i8:135; CHECK: # %bb.0:136; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma137; CHECK-NEXT: vsll.vi v9, v8, 7138; CHECK-NEXT: vsrl.vi v8, v8, 1139; CHECK-NEXT: vor.vv v8, v8, v9140; CHECK-NEXT: ret141;142; CHECK-ZVKB-LABEL: vror_vi_nxv2i8:143; CHECK-ZVKB: # %bb.0:144; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma145; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1146; CHECK-ZVKB-NEXT: ret147 %x = call <vscale x 2 x i8> @llvm.fshr.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> splat (i8 1))148 ret <vscale x 2 x i8> %x149}150 151define <vscale x 2 x i8> @vror_vi_rotl_nxv2i8(<vscale x 2 x i8> %a) {152; CHECK-LABEL: vror_vi_rotl_nxv2i8:153; CHECK: # %bb.0:154; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma155; CHECK-NEXT: vsrl.vi v9, v8, 7156; CHECK-NEXT: vadd.vv v8, v8, v8157; CHECK-NEXT: vor.vv v8, v8, v9158; CHECK-NEXT: ret159;160; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i8:161; CHECK-ZVKB: # %bb.0:162; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma163; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7164; CHECK-ZVKB-NEXT: ret165 %x = call <vscale x 2 x i8> @llvm.fshl.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i8> %a, <vscale x 2 x i8> splat (i8 1))166 ret <vscale x 2 x i8> %x167}168 169define <vscale x 4 x i8> @vror_vv_nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {170; CHECK-LABEL: vror_vv_nxv4i8:171; CHECK: # %bb.0:172; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma173; CHECK-NEXT: vand.vi v10, v9, 7174; CHECK-NEXT: vrsub.vi v9, v9, 0175; CHECK-NEXT: vsrl.vv v10, v8, v10176; CHECK-NEXT: vand.vi v9, v9, 7177; CHECK-NEXT: vsll.vv v8, v8, v9178; CHECK-NEXT: vor.vv v8, v10, v8179; CHECK-NEXT: ret180;181; CHECK-ZVKB-LABEL: vror_vv_nxv4i8:182; CHECK-ZVKB: # %bb.0:183; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma184; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9185; CHECK-ZVKB-NEXT: ret186 %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b)187 ret <vscale x 4 x i8> %x188}189 190define <vscale x 4 x i8> @vror_vx_nxv4i8(<vscale x 4 x i8> %a, i8 %b) {191; CHECK-LABEL: vror_vx_nxv4i8:192; CHECK: # %bb.0:193; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma194; CHECK-NEXT: vmv.v.x v9, a0195; CHECK-NEXT: vand.vi v10, v9, 7196; CHECK-NEXT: vrsub.vi v9, v9, 0197; CHECK-NEXT: vsrl.vv v10, v8, v10198; CHECK-NEXT: vand.vi v9, v9, 7199; CHECK-NEXT: vsll.vv v8, v8, v9200; CHECK-NEXT: vor.vv v8, v10, v8201; CHECK-NEXT: ret202;203; CHECK-ZVKB-LABEL: vror_vx_nxv4i8:204; CHECK-ZVKB: # %bb.0:205; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, mf2, ta, ma206; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0207; CHECK-ZVKB-NEXT: ret208 %b.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0209 %b.splat = shufflevector <vscale x 4 x i8> %b.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer210 %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> %b.splat)211 ret <vscale x 4 x i8> %x212}213 214define <vscale x 4 x i8> @vror_vi_nxv4i8(<vscale x 4 x i8> %a) {215; CHECK-LABEL: vror_vi_nxv4i8:216; CHECK: # %bb.0:217; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma218; CHECK-NEXT: vsll.vi v9, v8, 7219; CHECK-NEXT: vsrl.vi v8, v8, 1220; CHECK-NEXT: vor.vv v8, v8, v9221; CHECK-NEXT: ret222;223; CHECK-ZVKB-LABEL: vror_vi_nxv4i8:224; CHECK-ZVKB: # %bb.0:225; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma226; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1227; CHECK-ZVKB-NEXT: ret228 %x = call <vscale x 4 x i8> @llvm.fshr.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> splat (i8 1))229 ret <vscale x 4 x i8> %x230}231 232define <vscale x 4 x i8> @vror_vi_rotl_nxv4i8(<vscale x 4 x i8> %a) {233; CHECK-LABEL: vror_vi_rotl_nxv4i8:234; CHECK: # %bb.0:235; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma236; CHECK-NEXT: vsrl.vi v9, v8, 7237; CHECK-NEXT: vadd.vv v8, v8, v8238; CHECK-NEXT: vor.vv v8, v8, v9239; CHECK-NEXT: ret240;241; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i8:242; CHECK-ZVKB: # %bb.0:243; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma244; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7245; CHECK-ZVKB-NEXT: ret246 %x = call <vscale x 4 x i8> @llvm.fshl.nxv4i8(<vscale x 4 x i8> %a, <vscale x 4 x i8> %a, <vscale x 4 x i8> splat (i8 1))247 ret <vscale x 4 x i8> %x248}249 250define <vscale x 8 x i8> @vror_vv_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {251; CHECK-LABEL: vror_vv_nxv8i8:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma254; CHECK-NEXT: vand.vi v10, v9, 7255; CHECK-NEXT: vrsub.vi v9, v9, 0256; CHECK-NEXT: vsrl.vv v10, v8, v10257; CHECK-NEXT: vand.vi v9, v9, 7258; CHECK-NEXT: vsll.vv v8, v8, v9259; CHECK-NEXT: vor.vv v8, v10, v8260; CHECK-NEXT: ret261;262; CHECK-ZVKB-LABEL: vror_vv_nxv8i8:263; CHECK-ZVKB: # %bb.0:264; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma265; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9266; CHECK-ZVKB-NEXT: ret267 %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b)268 ret <vscale x 8 x i8> %x269}270 271define <vscale x 8 x i8> @vror_vx_nxv8i8(<vscale x 8 x i8> %a, i8 %b) {272; CHECK-LABEL: vror_vx_nxv8i8:273; CHECK: # %bb.0:274; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma275; CHECK-NEXT: vmv.v.x v9, a0276; CHECK-NEXT: vand.vi v10, v9, 7277; CHECK-NEXT: vrsub.vi v9, v9, 0278; CHECK-NEXT: vsrl.vv v10, v8, v10279; CHECK-NEXT: vand.vi v9, v9, 7280; CHECK-NEXT: vsll.vv v8, v8, v9281; CHECK-NEXT: vor.vv v8, v10, v8282; CHECK-NEXT: ret283;284; CHECK-ZVKB-LABEL: vror_vx_nxv8i8:285; CHECK-ZVKB: # %bb.0:286; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m1, ta, ma287; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0288; CHECK-ZVKB-NEXT: ret289 %b.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0290 %b.splat = shufflevector <vscale x 8 x i8> %b.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer291 %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> %b.splat)292 ret <vscale x 8 x i8> %x293}294 295define <vscale x 8 x i8> @vror_vi_nxv8i8(<vscale x 8 x i8> %a) {296; CHECK-LABEL: vror_vi_nxv8i8:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma299; CHECK-NEXT: vsll.vi v9, v8, 7300; CHECK-NEXT: vsrl.vi v8, v8, 1301; CHECK-NEXT: vor.vv v8, v8, v9302; CHECK-NEXT: ret303;304; CHECK-ZVKB-LABEL: vror_vi_nxv8i8:305; CHECK-ZVKB: # %bb.0:306; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma307; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1308; CHECK-ZVKB-NEXT: ret309 %x = call <vscale x 8 x i8> @llvm.fshr.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> splat (i8 1))310 ret <vscale x 8 x i8> %x311}312 313define <vscale x 8 x i8> @vror_vi_rotl_nxv8i8(<vscale x 8 x i8> %a) {314; CHECK-LABEL: vror_vi_rotl_nxv8i8:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma317; CHECK-NEXT: vsrl.vi v9, v8, 7318; CHECK-NEXT: vadd.vv v8, v8, v8319; CHECK-NEXT: vor.vv v8, v8, v9320; CHECK-NEXT: ret321;322; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i8:323; CHECK-ZVKB: # %bb.0:324; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m1, ta, ma325; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7326; CHECK-ZVKB-NEXT: ret327 %x = call <vscale x 8 x i8> @llvm.fshl.nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %a, <vscale x 8 x i8> splat (i8 1))328 ret <vscale x 8 x i8> %x329}330 331define <vscale x 16 x i8> @vror_vv_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {332; CHECK-LABEL: vror_vv_nxv16i8:333; CHECK: # %bb.0:334; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma335; CHECK-NEXT: vand.vi v12, v10, 7336; CHECK-NEXT: vrsub.vi v10, v10, 0337; CHECK-NEXT: vsrl.vv v12, v8, v12338; CHECK-NEXT: vand.vi v10, v10, 7339; CHECK-NEXT: vsll.vv v8, v8, v10340; CHECK-NEXT: vor.vv v8, v12, v8341; CHECK-NEXT: ret342;343; CHECK-ZVKB-LABEL: vror_vv_nxv16i8:344; CHECK-ZVKB: # %bb.0:345; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma346; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10347; CHECK-ZVKB-NEXT: ret348 %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)349 ret <vscale x 16 x i8> %x350}351 352define <vscale x 16 x i8> @vror_vx_nxv16i8(<vscale x 16 x i8> %a, i8 %b) {353; CHECK-LABEL: vror_vx_nxv16i8:354; CHECK: # %bb.0:355; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma356; CHECK-NEXT: vmv.v.x v10, a0357; CHECK-NEXT: vand.vi v12, v10, 7358; CHECK-NEXT: vrsub.vi v10, v10, 0359; CHECK-NEXT: vsrl.vv v12, v8, v12360; CHECK-NEXT: vand.vi v10, v10, 7361; CHECK-NEXT: vsll.vv v8, v8, v10362; CHECK-NEXT: vor.vv v8, v12, v8363; CHECK-NEXT: ret364;365; CHECK-ZVKB-LABEL: vror_vx_nxv16i8:366; CHECK-ZVKB: # %bb.0:367; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m2, ta, ma368; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0369; CHECK-ZVKB-NEXT: ret370 %b.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0371 %b.splat = shufflevector <vscale x 16 x i8> %b.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer372 %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b.splat)373 ret <vscale x 16 x i8> %x374}375 376define <vscale x 16 x i8> @vror_vi_nxv16i8(<vscale x 16 x i8> %a) {377; CHECK-LABEL: vror_vi_nxv16i8:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma380; CHECK-NEXT: vsll.vi v10, v8, 7381; CHECK-NEXT: vsrl.vi v8, v8, 1382; CHECK-NEXT: vor.vv v8, v8, v10383; CHECK-NEXT: ret384;385; CHECK-ZVKB-LABEL: vror_vi_nxv16i8:386; CHECK-ZVKB: # %bb.0:387; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma388; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1389; CHECK-ZVKB-NEXT: ret390 %x = call <vscale x 16 x i8> @llvm.fshr.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat (i8 1))391 ret <vscale x 16 x i8> %x392}393 394define <vscale x 16 x i8> @vror_vi_rotl_nxv16i8(<vscale x 16 x i8> %a) {395; CHECK-LABEL: vror_vi_rotl_nxv16i8:396; CHECK: # %bb.0:397; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma398; CHECK-NEXT: vsrl.vi v10, v8, 7399; CHECK-NEXT: vadd.vv v8, v8, v8400; CHECK-NEXT: vor.vv v8, v8, v10401; CHECK-NEXT: ret402;403; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i8:404; CHECK-ZVKB: # %bb.0:405; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m2, ta, ma406; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7407; CHECK-ZVKB-NEXT: ret408 %x = call <vscale x 16 x i8> @llvm.fshl.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %a, <vscale x 16 x i8> splat (i8 1))409 ret <vscale x 16 x i8> %x410}411 412define <vscale x 32 x i8> @vror_vv_nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %b) {413; CHECK-LABEL: vror_vv_nxv32i8:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma416; CHECK-NEXT: vand.vi v16, v12, 7417; CHECK-NEXT: vrsub.vi v12, v12, 0418; CHECK-NEXT: vsrl.vv v16, v8, v16419; CHECK-NEXT: vand.vi v12, v12, 7420; CHECK-NEXT: vsll.vv v8, v8, v12421; CHECK-NEXT: vor.vv v8, v16, v8422; CHECK-NEXT: ret423;424; CHECK-ZVKB-LABEL: vror_vv_nxv32i8:425; CHECK-ZVKB: # %bb.0:426; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma427; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12428; CHECK-ZVKB-NEXT: ret429 %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b)430 ret <vscale x 32 x i8> %x431}432 433define <vscale x 32 x i8> @vror_vx_nxv32i8(<vscale x 32 x i8> %a, i8 %b) {434; CHECK-LABEL: vror_vx_nxv32i8:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma437; CHECK-NEXT: vmv.v.x v12, a0438; CHECK-NEXT: vand.vi v16, v12, 7439; CHECK-NEXT: vrsub.vi v12, v12, 0440; CHECK-NEXT: vsrl.vv v16, v8, v16441; CHECK-NEXT: vand.vi v12, v12, 7442; CHECK-NEXT: vsll.vv v8, v8, v12443; CHECK-NEXT: vor.vv v8, v16, v8444; CHECK-NEXT: ret445;446; CHECK-ZVKB-LABEL: vror_vx_nxv32i8:447; CHECK-ZVKB: # %bb.0:448; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m4, ta, ma449; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0450; CHECK-ZVKB-NEXT: ret451 %b.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0452 %b.splat = shufflevector <vscale x 32 x i8> %b.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer453 %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> %b.splat)454 ret <vscale x 32 x i8> %x455}456 457define <vscale x 32 x i8> @vror_vi_nxv32i8(<vscale x 32 x i8> %a) {458; CHECK-LABEL: vror_vi_nxv32i8:459; CHECK: # %bb.0:460; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma461; CHECK-NEXT: vsll.vi v12, v8, 7462; CHECK-NEXT: vsrl.vi v8, v8, 1463; CHECK-NEXT: vor.vv v8, v8, v12464; CHECK-NEXT: ret465;466; CHECK-ZVKB-LABEL: vror_vi_nxv32i8:467; CHECK-ZVKB: # %bb.0:468; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma469; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1470; CHECK-ZVKB-NEXT: ret471 %x = call <vscale x 32 x i8> @llvm.fshr.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> splat (i8 1))472 ret <vscale x 32 x i8> %x473}474 475define <vscale x 32 x i8> @vror_vi_rotl_nxv32i8(<vscale x 32 x i8> %a) {476; CHECK-LABEL: vror_vi_rotl_nxv32i8:477; CHECK: # %bb.0:478; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma479; CHECK-NEXT: vsrl.vi v12, v8, 7480; CHECK-NEXT: vadd.vv v8, v8, v8481; CHECK-NEXT: vor.vv v8, v8, v12482; CHECK-NEXT: ret483;484; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i8:485; CHECK-ZVKB: # %bb.0:486; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m4, ta, ma487; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7488; CHECK-ZVKB-NEXT: ret489 %x = call <vscale x 32 x i8> @llvm.fshl.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i8> %a, <vscale x 32 x i8> splat (i8 1))490 ret <vscale x 32 x i8> %x491}492 493define <vscale x 64 x i8> @vror_vv_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {494; CHECK-LABEL: vror_vv_nxv64i8:495; CHECK: # %bb.0:496; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma497; CHECK-NEXT: vand.vi v24, v16, 7498; CHECK-NEXT: vrsub.vi v16, v16, 0499; CHECK-NEXT: vsrl.vv v24, v8, v24500; CHECK-NEXT: vand.vi v16, v16, 7501; CHECK-NEXT: vsll.vv v8, v8, v16502; CHECK-NEXT: vor.vv v8, v24, v8503; CHECK-NEXT: ret504;505; CHECK-ZVKB-LABEL: vror_vv_nxv64i8:506; CHECK-ZVKB: # %bb.0:507; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma508; CHECK-ZVKB-NEXT: vror.vv v8, v8, v16509; CHECK-ZVKB-NEXT: ret510 %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b)511 ret <vscale x 64 x i8> %x512}513 514define <vscale x 64 x i8> @vror_vx_nxv64i8(<vscale x 64 x i8> %a, i8 %b) {515; CHECK-LABEL: vror_vx_nxv64i8:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma518; CHECK-NEXT: vmv.v.x v16, a0519; CHECK-NEXT: vand.vi v24, v16, 7520; CHECK-NEXT: vrsub.vi v16, v16, 0521; CHECK-NEXT: vsrl.vv v24, v8, v24522; CHECK-NEXT: vand.vi v16, v16, 7523; CHECK-NEXT: vsll.vv v8, v8, v16524; CHECK-NEXT: vor.vv v8, v24, v8525; CHECK-NEXT: ret526;527; CHECK-ZVKB-LABEL: vror_vx_nxv64i8:528; CHECK-ZVKB: # %bb.0:529; CHECK-ZVKB-NEXT: vsetvli a1, zero, e8, m8, ta, ma530; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0531; CHECK-ZVKB-NEXT: ret532 %b.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0533 %b.splat = shufflevector <vscale x 64 x i8> %b.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer534 %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b.splat)535 ret <vscale x 64 x i8> %x536}537 538define <vscale x 64 x i8> @vror_vi_nxv64i8(<vscale x 64 x i8> %a) {539; CHECK-LABEL: vror_vi_nxv64i8:540; CHECK: # %bb.0:541; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma542; CHECK-NEXT: vsll.vi v16, v8, 7543; CHECK-NEXT: vsrl.vi v8, v8, 1544; CHECK-NEXT: vor.vv v8, v8, v16545; CHECK-NEXT: ret546;547; CHECK-ZVKB-LABEL: vror_vi_nxv64i8:548; CHECK-ZVKB: # %bb.0:549; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma550; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1551; CHECK-ZVKB-NEXT: ret552 %x = call <vscale x 64 x i8> @llvm.fshr.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> splat (i8 1))553 ret <vscale x 64 x i8> %x554}555 556define <vscale x 64 x i8> @vror_vi_rotl_nxv64i8(<vscale x 64 x i8> %a) {557; CHECK-LABEL: vror_vi_rotl_nxv64i8:558; CHECK: # %bb.0:559; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma560; CHECK-NEXT: vsrl.vi v16, v8, 7561; CHECK-NEXT: vadd.vv v8, v8, v8562; CHECK-NEXT: vor.vv v8, v8, v16563; CHECK-NEXT: ret564;565; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv64i8:566; CHECK-ZVKB: # %bb.0:567; CHECK-ZVKB-NEXT: vsetvli a0, zero, e8, m8, ta, ma568; CHECK-ZVKB-NEXT: vror.vi v8, v8, 7569; CHECK-ZVKB-NEXT: ret570 %x = call <vscale x 64 x i8> @llvm.fshl.nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %a, <vscale x 64 x i8> splat (i8 1))571 ret <vscale x 64 x i8> %x572}573 574define <vscale x 1 x i16> @vror_vv_nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %b) {575; CHECK-LABEL: vror_vv_nxv1i16:576; CHECK: # %bb.0:577; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma578; CHECK-NEXT: vand.vi v10, v9, 15579; CHECK-NEXT: vrsub.vi v9, v9, 0580; CHECK-NEXT: vsrl.vv v10, v8, v10581; CHECK-NEXT: vand.vi v9, v9, 15582; CHECK-NEXT: vsll.vv v8, v8, v9583; CHECK-NEXT: vor.vv v8, v10, v8584; CHECK-NEXT: ret585;586; CHECK-ZVKB-LABEL: vror_vv_nxv1i16:587; CHECK-ZVKB: # %bb.0:588; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma589; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9590; CHECK-ZVKB-NEXT: ret591 %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b)592 ret <vscale x 1 x i16> %x593}594 595define <vscale x 1 x i16> @vror_vx_nxv1i16(<vscale x 1 x i16> %a, i16 %b) {596; CHECK-LABEL: vror_vx_nxv1i16:597; CHECK: # %bb.0:598; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma599; CHECK-NEXT: vmv.v.x v9, a0600; CHECK-NEXT: vand.vi v10, v9, 15601; CHECK-NEXT: vrsub.vi v9, v9, 0602; CHECK-NEXT: vsrl.vv v10, v8, v10603; CHECK-NEXT: vand.vi v9, v9, 15604; CHECK-NEXT: vsll.vv v8, v8, v9605; CHECK-NEXT: vor.vv v8, v10, v8606; CHECK-NEXT: ret607;608; CHECK-ZVKB-LABEL: vror_vx_nxv1i16:609; CHECK-ZVKB: # %bb.0:610; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf4, ta, ma611; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0612; CHECK-ZVKB-NEXT: ret613 %b.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0614 %b.splat = shufflevector <vscale x 1 x i16> %b.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer615 %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> %b.splat)616 ret <vscale x 1 x i16> %x617}618 619define <vscale x 1 x i16> @vror_vi_nxv1i16(<vscale x 1 x i16> %a) {620; CHECK-LABEL: vror_vi_nxv1i16:621; CHECK: # %bb.0:622; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma623; CHECK-NEXT: vsll.vi v9, v8, 15624; CHECK-NEXT: vsrl.vi v8, v8, 1625; CHECK-NEXT: vor.vv v8, v8, v9626; CHECK-NEXT: ret627;628; CHECK-ZVKB-LABEL: vror_vi_nxv1i16:629; CHECK-ZVKB: # %bb.0:630; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma631; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1632; CHECK-ZVKB-NEXT: ret633 %x = call <vscale x 1 x i16> @llvm.fshr.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> splat (i16 1))634 ret <vscale x 1 x i16> %x635}636 637define <vscale x 1 x i16> @vror_vi_rotl_nxv1i16(<vscale x 1 x i16> %a) {638; CHECK-LABEL: vror_vi_rotl_nxv1i16:639; CHECK: # %bb.0:640; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma641; CHECK-NEXT: vsrl.vi v9, v8, 15642; CHECK-NEXT: vadd.vv v8, v8, v8643; CHECK-NEXT: vor.vv v8, v8, v9644; CHECK-NEXT: ret645;646; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i16:647; CHECK-ZVKB: # %bb.0:648; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma649; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15650; CHECK-ZVKB-NEXT: ret651 %x = call <vscale x 1 x i16> @llvm.fshl.nxv1i16(<vscale x 1 x i16> %a, <vscale x 1 x i16> %a, <vscale x 1 x i16> splat (i16 1))652 ret <vscale x 1 x i16> %x653}654 655define <vscale x 2 x i16> @vror_vv_nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %b) {656; CHECK-LABEL: vror_vv_nxv2i16:657; CHECK: # %bb.0:658; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma659; CHECK-NEXT: vand.vi v10, v9, 15660; CHECK-NEXT: vrsub.vi v9, v9, 0661; CHECK-NEXT: vsrl.vv v10, v8, v10662; CHECK-NEXT: vand.vi v9, v9, 15663; CHECK-NEXT: vsll.vv v8, v8, v9664; CHECK-NEXT: vor.vv v8, v10, v8665; CHECK-NEXT: ret666;667; CHECK-ZVKB-LABEL: vror_vv_nxv2i16:668; CHECK-ZVKB: # %bb.0:669; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma670; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9671; CHECK-ZVKB-NEXT: ret672 %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b)673 ret <vscale x 2 x i16> %x674}675 676define <vscale x 2 x i16> @vror_vx_nxv2i16(<vscale x 2 x i16> %a, i16 %b) {677; CHECK-LABEL: vror_vx_nxv2i16:678; CHECK: # %bb.0:679; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma680; CHECK-NEXT: vmv.v.x v9, a0681; CHECK-NEXT: vand.vi v10, v9, 15682; CHECK-NEXT: vrsub.vi v9, v9, 0683; CHECK-NEXT: vsrl.vv v10, v8, v10684; CHECK-NEXT: vand.vi v9, v9, 15685; CHECK-NEXT: vsll.vv v8, v8, v9686; CHECK-NEXT: vor.vv v8, v10, v8687; CHECK-NEXT: ret688;689; CHECK-ZVKB-LABEL: vror_vx_nxv2i16:690; CHECK-ZVKB: # %bb.0:691; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma692; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0693; CHECK-ZVKB-NEXT: ret694 %b.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0695 %b.splat = shufflevector <vscale x 2 x i16> %b.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer696 %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> %b.splat)697 ret <vscale x 2 x i16> %x698}699 700define <vscale x 2 x i16> @vror_vi_nxv2i16(<vscale x 2 x i16> %a) {701; CHECK-LABEL: vror_vi_nxv2i16:702; CHECK: # %bb.0:703; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma704; CHECK-NEXT: vsll.vi v9, v8, 15705; CHECK-NEXT: vsrl.vi v8, v8, 1706; CHECK-NEXT: vor.vv v8, v8, v9707; CHECK-NEXT: ret708;709; CHECK-ZVKB-LABEL: vror_vi_nxv2i16:710; CHECK-ZVKB: # %bb.0:711; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma712; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1713; CHECK-ZVKB-NEXT: ret714 %x = call <vscale x 2 x i16> @llvm.fshr.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> splat (i16 1))715 ret <vscale x 2 x i16> %x716}717 718define <vscale x 2 x i16> @vror_vi_rotl_nxv2i16(<vscale x 2 x i16> %a) {719; CHECK-LABEL: vror_vi_rotl_nxv2i16:720; CHECK: # %bb.0:721; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma722; CHECK-NEXT: vsrl.vi v9, v8, 15723; CHECK-NEXT: vadd.vv v8, v8, v8724; CHECK-NEXT: vor.vv v8, v8, v9725; CHECK-NEXT: ret726;727; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i16:728; CHECK-ZVKB: # %bb.0:729; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma730; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15731; CHECK-ZVKB-NEXT: ret732 %x = call <vscale x 2 x i16> @llvm.fshl.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i16> %a, <vscale x 2 x i16> splat (i16 1))733 ret <vscale x 2 x i16> %x734}735 736define <vscale x 4 x i16> @vror_vv_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {737; CHECK-LABEL: vror_vv_nxv4i16:738; CHECK: # %bb.0:739; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma740; CHECK-NEXT: vand.vi v10, v9, 15741; CHECK-NEXT: vrsub.vi v9, v9, 0742; CHECK-NEXT: vsrl.vv v10, v8, v10743; CHECK-NEXT: vand.vi v9, v9, 15744; CHECK-NEXT: vsll.vv v8, v8, v9745; CHECK-NEXT: vor.vv v8, v10, v8746; CHECK-NEXT: ret747;748; CHECK-ZVKB-LABEL: vror_vv_nxv4i16:749; CHECK-ZVKB: # %bb.0:750; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma751; CHECK-ZVKB-NEXT: vror.vv v8, v8, v9752; CHECK-ZVKB-NEXT: ret753 %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b)754 ret <vscale x 4 x i16> %x755}756 757define <vscale x 4 x i16> @vror_vx_nxv4i16(<vscale x 4 x i16> %a, i16 %b) {758; CHECK-LABEL: vror_vx_nxv4i16:759; CHECK: # %bb.0:760; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma761; CHECK-NEXT: vmv.v.x v9, a0762; CHECK-NEXT: vand.vi v10, v9, 15763; CHECK-NEXT: vrsub.vi v9, v9, 0764; CHECK-NEXT: vsrl.vv v10, v8, v10765; CHECK-NEXT: vand.vi v9, v9, 15766; CHECK-NEXT: vsll.vv v8, v8, v9767; CHECK-NEXT: vor.vv v8, v10, v8768; CHECK-NEXT: ret769;770; CHECK-ZVKB-LABEL: vror_vx_nxv4i16:771; CHECK-ZVKB: # %bb.0:772; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m1, ta, ma773; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0774; CHECK-ZVKB-NEXT: ret775 %b.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0776 %b.splat = shufflevector <vscale x 4 x i16> %b.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer777 %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> %b.splat)778 ret <vscale x 4 x i16> %x779}780 781define <vscale x 4 x i16> @vror_vi_nxv4i16(<vscale x 4 x i16> %a) {782; CHECK-LABEL: vror_vi_nxv4i16:783; CHECK: # %bb.0:784; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma785; CHECK-NEXT: vsll.vi v9, v8, 15786; CHECK-NEXT: vsrl.vi v8, v8, 1787; CHECK-NEXT: vor.vv v8, v8, v9788; CHECK-NEXT: ret789;790; CHECK-ZVKB-LABEL: vror_vi_nxv4i16:791; CHECK-ZVKB: # %bb.0:792; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma793; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1794; CHECK-ZVKB-NEXT: ret795 %x = call <vscale x 4 x i16> @llvm.fshr.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> splat (i16 1))796 ret <vscale x 4 x i16> %x797}798 799define <vscale x 4 x i16> @vror_vi_rotl_nxv4i16(<vscale x 4 x i16> %a) {800; CHECK-LABEL: vror_vi_rotl_nxv4i16:801; CHECK: # %bb.0:802; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma803; CHECK-NEXT: vsrl.vi v9, v8, 15804; CHECK-NEXT: vadd.vv v8, v8, v8805; CHECK-NEXT: vor.vv v8, v8, v9806; CHECK-NEXT: ret807;808; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i16:809; CHECK-ZVKB: # %bb.0:810; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m1, ta, ma811; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15812; CHECK-ZVKB-NEXT: ret813 %x = call <vscale x 4 x i16> @llvm.fshl.nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %a, <vscale x 4 x i16> splat (i16 1))814 ret <vscale x 4 x i16> %x815}816 817define <vscale x 8 x i16> @vror_vv_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {818; CHECK-LABEL: vror_vv_nxv8i16:819; CHECK: # %bb.0:820; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma821; CHECK-NEXT: vand.vi v12, v10, 15822; CHECK-NEXT: vrsub.vi v10, v10, 0823; CHECK-NEXT: vsrl.vv v12, v8, v12824; CHECK-NEXT: vand.vi v10, v10, 15825; CHECK-NEXT: vsll.vv v8, v8, v10826; CHECK-NEXT: vor.vv v8, v12, v8827; CHECK-NEXT: ret828;829; CHECK-ZVKB-LABEL: vror_vv_nxv8i16:830; CHECK-ZVKB: # %bb.0:831; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma832; CHECK-ZVKB-NEXT: vror.vv v8, v8, v10833; CHECK-ZVKB-NEXT: ret834 %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)835 ret <vscale x 8 x i16> %x836}837 838define <vscale x 8 x i16> @vror_vx_nxv8i16(<vscale x 8 x i16> %a, i16 %b) {839; CHECK-LABEL: vror_vx_nxv8i16:840; CHECK: # %bb.0:841; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma842; CHECK-NEXT: vmv.v.x v10, a0843; CHECK-NEXT: vand.vi v12, v10, 15844; CHECK-NEXT: vrsub.vi v10, v10, 0845; CHECK-NEXT: vsrl.vv v12, v8, v12846; CHECK-NEXT: vand.vi v10, v10, 15847; CHECK-NEXT: vsll.vv v8, v8, v10848; CHECK-NEXT: vor.vv v8, v12, v8849; CHECK-NEXT: ret850;851; CHECK-ZVKB-LABEL: vror_vx_nxv8i16:852; CHECK-ZVKB: # %bb.0:853; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m2, ta, ma854; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0855; CHECK-ZVKB-NEXT: ret856 %b.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0857 %b.splat = shufflevector <vscale x 8 x i16> %b.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer858 %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b.splat)859 ret <vscale x 8 x i16> %x860}861 862define <vscale x 8 x i16> @vror_vi_nxv8i16(<vscale x 8 x i16> %a) {863; CHECK-LABEL: vror_vi_nxv8i16:864; CHECK: # %bb.0:865; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma866; CHECK-NEXT: vsll.vi v10, v8, 15867; CHECK-NEXT: vsrl.vi v8, v8, 1868; CHECK-NEXT: vor.vv v8, v8, v10869; CHECK-NEXT: ret870;871; CHECK-ZVKB-LABEL: vror_vi_nxv8i16:872; CHECK-ZVKB: # %bb.0:873; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma874; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1875; CHECK-ZVKB-NEXT: ret876 %x = call <vscale x 8 x i16> @llvm.fshr.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat (i16 1))877 ret <vscale x 8 x i16> %x878}879 880define <vscale x 8 x i16> @vror_vi_rotl_nxv8i16(<vscale x 8 x i16> %a) {881; CHECK-LABEL: vror_vi_rotl_nxv8i16:882; CHECK: # %bb.0:883; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma884; CHECK-NEXT: vsrl.vi v10, v8, 15885; CHECK-NEXT: vadd.vv v8, v8, v8886; CHECK-NEXT: vor.vv v8, v8, v10887; CHECK-NEXT: ret888;889; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i16:890; CHECK-ZVKB: # %bb.0:891; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m2, ta, ma892; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15893; CHECK-ZVKB-NEXT: ret894 %x = call <vscale x 8 x i16> @llvm.fshl.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %a, <vscale x 8 x i16> splat (i16 1))895 ret <vscale x 8 x i16> %x896}897 898define <vscale x 16 x i16> @vror_vv_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {899; CHECK-LABEL: vror_vv_nxv16i16:900; CHECK: # %bb.0:901; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma902; CHECK-NEXT: vand.vi v16, v12, 15903; CHECK-NEXT: vrsub.vi v12, v12, 0904; CHECK-NEXT: vsrl.vv v16, v8, v16905; CHECK-NEXT: vand.vi v12, v12, 15906; CHECK-NEXT: vsll.vv v8, v8, v12907; CHECK-NEXT: vor.vv v8, v16, v8908; CHECK-NEXT: ret909;910; CHECK-ZVKB-LABEL: vror_vv_nxv16i16:911; CHECK-ZVKB: # %bb.0:912; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma913; CHECK-ZVKB-NEXT: vror.vv v8, v8, v12914; CHECK-ZVKB-NEXT: ret915 %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b)916 ret <vscale x 16 x i16> %x917}918 919define <vscale x 16 x i16> @vror_vx_nxv16i16(<vscale x 16 x i16> %a, i16 %b) {920; CHECK-LABEL: vror_vx_nxv16i16:921; CHECK: # %bb.0:922; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma923; CHECK-NEXT: vmv.v.x v12, a0924; CHECK-NEXT: vand.vi v16, v12, 15925; CHECK-NEXT: vrsub.vi v12, v12, 0926; CHECK-NEXT: vsrl.vv v16, v8, v16927; CHECK-NEXT: vand.vi v12, v12, 15928; CHECK-NEXT: vsll.vv v8, v8, v12929; CHECK-NEXT: vor.vv v8, v16, v8930; CHECK-NEXT: ret931;932; CHECK-ZVKB-LABEL: vror_vx_nxv16i16:933; CHECK-ZVKB: # %bb.0:934; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m4, ta, ma935; CHECK-ZVKB-NEXT: vror.vx v8, v8, a0936; CHECK-ZVKB-NEXT: ret937 %b.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0938 %b.splat = shufflevector <vscale x 16 x i16> %b.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer939 %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> %b.splat)940 ret <vscale x 16 x i16> %x941}942 943define <vscale x 16 x i16> @vror_vi_nxv16i16(<vscale x 16 x i16> %a) {944; CHECK-LABEL: vror_vi_nxv16i16:945; CHECK: # %bb.0:946; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma947; CHECK-NEXT: vsll.vi v12, v8, 15948; CHECK-NEXT: vsrl.vi v8, v8, 1949; CHECK-NEXT: vor.vv v8, v8, v12950; CHECK-NEXT: ret951;952; CHECK-ZVKB-LABEL: vror_vi_nxv16i16:953; CHECK-ZVKB: # %bb.0:954; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma955; CHECK-ZVKB-NEXT: vror.vi v8, v8, 1956; CHECK-ZVKB-NEXT: ret957 %x = call <vscale x 16 x i16> @llvm.fshr.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> splat (i16 1))958 ret <vscale x 16 x i16> %x959}960 961define <vscale x 16 x i16> @vror_vi_rotl_nxv16i16(<vscale x 16 x i16> %a) {962; CHECK-LABEL: vror_vi_rotl_nxv16i16:963; CHECK: # %bb.0:964; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma965; CHECK-NEXT: vsrl.vi v12, v8, 15966; CHECK-NEXT: vadd.vv v8, v8, v8967; CHECK-NEXT: vor.vv v8, v8, v12968; CHECK-NEXT: ret969;970; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i16:971; CHECK-ZVKB: # %bb.0:972; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m4, ta, ma973; CHECK-ZVKB-NEXT: vror.vi v8, v8, 15974; CHECK-ZVKB-NEXT: ret975 %x = call <vscale x 16 x i16> @llvm.fshl.nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %a, <vscale x 16 x i16> splat (i16 1))976 ret <vscale x 16 x i16> %x977}978 979define <vscale x 32 x i16> @vror_vv_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {980; CHECK-LABEL: vror_vv_nxv32i16:981; CHECK: # %bb.0:982; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma983; CHECK-NEXT: vand.vi v24, v16, 15984; CHECK-NEXT: vrsub.vi v16, v16, 0985; CHECK-NEXT: vsrl.vv v24, v8, v24986; CHECK-NEXT: vand.vi v16, v16, 15987; CHECK-NEXT: vsll.vv v8, v8, v16988; CHECK-NEXT: vor.vv v8, v24, v8989; CHECK-NEXT: ret990;991; CHECK-ZVKB-LABEL: vror_vv_nxv32i16:992; CHECK-ZVKB: # %bb.0:993; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma994; CHECK-ZVKB-NEXT: vror.vv v8, v8, v16995; CHECK-ZVKB-NEXT: ret996 %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b)997 ret <vscale x 32 x i16> %x998}999 1000define <vscale x 32 x i16> @vror_vx_nxv32i16(<vscale x 32 x i16> %a, i16 %b) {1001; CHECK-LABEL: vror_vx_nxv32i16:1002; CHECK: # %bb.0:1003; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma1004; CHECK-NEXT: vmv.v.x v16, a01005; CHECK-NEXT: vand.vi v24, v16, 151006; CHECK-NEXT: vrsub.vi v16, v16, 01007; CHECK-NEXT: vsrl.vv v24, v8, v241008; CHECK-NEXT: vand.vi v16, v16, 151009; CHECK-NEXT: vsll.vv v8, v8, v161010; CHECK-NEXT: vor.vv v8, v24, v81011; CHECK-NEXT: ret1012;1013; CHECK-ZVKB-LABEL: vror_vx_nxv32i16:1014; CHECK-ZVKB: # %bb.0:1015; CHECK-ZVKB-NEXT: vsetvli a1, zero, e16, m8, ta, ma1016; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01017; CHECK-ZVKB-NEXT: ret1018 %b.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 01019 %b.splat = shufflevector <vscale x 32 x i16> %b.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer1020 %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b.splat)1021 ret <vscale x 32 x i16> %x1022}1023 1024define <vscale x 32 x i16> @vror_vi_nxv32i16(<vscale x 32 x i16> %a) {1025; CHECK-LABEL: vror_vi_nxv32i16:1026; CHECK: # %bb.0:1027; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma1028; CHECK-NEXT: vsll.vi v16, v8, 151029; CHECK-NEXT: vsrl.vi v8, v8, 11030; CHECK-NEXT: vor.vv v8, v8, v161031; CHECK-NEXT: ret1032;1033; CHECK-ZVKB-LABEL: vror_vi_nxv32i16:1034; CHECK-ZVKB: # %bb.0:1035; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma1036; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11037; CHECK-ZVKB-NEXT: ret1038 %x = call <vscale x 32 x i16> @llvm.fshr.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> splat (i16 1))1039 ret <vscale x 32 x i16> %x1040}1041 1042define <vscale x 32 x i16> @vror_vi_rotl_nxv32i16(<vscale x 32 x i16> %a) {1043; CHECK-LABEL: vror_vi_rotl_nxv32i16:1044; CHECK: # %bb.0:1045; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma1046; CHECK-NEXT: vsrl.vi v16, v8, 151047; CHECK-NEXT: vadd.vv v8, v8, v81048; CHECK-NEXT: vor.vv v8, v8, v161049; CHECK-NEXT: ret1050;1051; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv32i16:1052; CHECK-ZVKB: # %bb.0:1053; CHECK-ZVKB-NEXT: vsetvli a0, zero, e16, m8, ta, ma1054; CHECK-ZVKB-NEXT: vror.vi v8, v8, 151055; CHECK-ZVKB-NEXT: ret1056 %x = call <vscale x 32 x i16> @llvm.fshl.nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %a, <vscale x 32 x i16> splat (i16 1))1057 ret <vscale x 32 x i16> %x1058}1059 1060define <vscale x 1 x i32> @vror_vv_nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %b) {1061; CHECK-LABEL: vror_vv_nxv1i32:1062; CHECK: # %bb.0:1063; CHECK-NEXT: li a0, 311064; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1065; CHECK-NEXT: vrsub.vi v10, v9, 01066; CHECK-NEXT: vand.vx v9, v9, a01067; CHECK-NEXT: vand.vx v10, v10, a01068; CHECK-NEXT: vsrl.vv v9, v8, v91069; CHECK-NEXT: vsll.vv v8, v8, v101070; CHECK-NEXT: vor.vv v8, v9, v81071; CHECK-NEXT: ret1072;1073; CHECK-ZVKB-LABEL: vror_vv_nxv1i32:1074; CHECK-ZVKB: # %bb.0:1075; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1076; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91077; CHECK-ZVKB-NEXT: ret1078 %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b)1079 ret <vscale x 1 x i32> %x1080}1081 1082define <vscale x 1 x i32> @vror_vx_nxv1i32(<vscale x 1 x i32> %a, i32 %b) {1083; CHECK-RV32-LABEL: vror_vx_nxv1i32:1084; CHECK-RV32: # %bb.0:1085; CHECK-RV32-NEXT: andi a1, a0, 311086; CHECK-RV32-NEXT: neg a0, a01087; CHECK-RV32-NEXT: vsetvli a2, zero, e32, mf2, ta, ma1088; CHECK-RV32-NEXT: vsrl.vx v9, v8, a11089; CHECK-RV32-NEXT: andi a0, a0, 311090; CHECK-RV32-NEXT: vsll.vx v8, v8, a01091; CHECK-RV32-NEXT: vor.vv v8, v9, v81092; CHECK-RV32-NEXT: ret1093;1094; CHECK-RV64-LABEL: vror_vx_nxv1i32:1095; CHECK-RV64: # %bb.0:1096; CHECK-RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1097; CHECK-RV64-NEXT: vmv.v.x v9, a01098; CHECK-RV64-NEXT: li a0, 311099; CHECK-RV64-NEXT: vand.vx v10, v9, a01100; CHECK-RV64-NEXT: vrsub.vi v9, v9, 01101; CHECK-RV64-NEXT: vsrl.vv v10, v8, v101102; CHECK-RV64-NEXT: vand.vx v9, v9, a01103; CHECK-RV64-NEXT: vsll.vv v8, v8, v91104; CHECK-RV64-NEXT: vor.vv v8, v10, v81105; CHECK-RV64-NEXT: ret1106;1107; CHECK-ZVKB-LABEL: vror_vx_nxv1i32:1108; CHECK-ZVKB: # %bb.0:1109; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, mf2, ta, ma1110; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01111; CHECK-ZVKB-NEXT: ret1112 %b.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01113 %b.splat = shufflevector <vscale x 1 x i32> %b.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1114 %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> %b.splat)1115 ret <vscale x 1 x i32> %x1116}1117 1118define <vscale x 1 x i32> @vror_vi_nxv1i32(<vscale x 1 x i32> %a) {1119; CHECK-LABEL: vror_vi_nxv1i32:1120; CHECK: # %bb.0:1121; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1122; CHECK-NEXT: vsll.vi v9, v8, 311123; CHECK-NEXT: vsrl.vi v8, v8, 11124; CHECK-NEXT: vor.vv v8, v8, v91125; CHECK-NEXT: ret1126;1127; CHECK-ZVKB-LABEL: vror_vi_nxv1i32:1128; CHECK-ZVKB: # %bb.0:1129; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1130; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11131; CHECK-ZVKB-NEXT: ret1132 %x = call <vscale x 1 x i32> @llvm.fshr.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> splat (i32 1))1133 ret <vscale x 1 x i32> %x1134}1135 1136define <vscale x 1 x i32> @vror_vi_rotl_nxv1i32(<vscale x 1 x i32> %a) {1137; CHECK-LABEL: vror_vi_rotl_nxv1i32:1138; CHECK: # %bb.0:1139; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1140; CHECK-NEXT: vsrl.vi v9, v8, 311141; CHECK-NEXT: vadd.vv v8, v8, v81142; CHECK-NEXT: vor.vv v8, v8, v91143; CHECK-NEXT: ret1144;1145; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i32:1146; CHECK-ZVKB: # %bb.0:1147; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma1148; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311149; CHECK-ZVKB-NEXT: ret1150 %x = call <vscale x 1 x i32> @llvm.fshl.nxv1i32(<vscale x 1 x i32> %a, <vscale x 1 x i32> %a, <vscale x 1 x i32> splat (i32 1))1151 ret <vscale x 1 x i32> %x1152}1153 1154define <vscale x 2 x i32> @vror_vv_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {1155; CHECK-LABEL: vror_vv_nxv2i32:1156; CHECK: # %bb.0:1157; CHECK-NEXT: li a0, 311158; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma1159; CHECK-NEXT: vrsub.vi v10, v9, 01160; CHECK-NEXT: vand.vx v9, v9, a01161; CHECK-NEXT: vand.vx v10, v10, a01162; CHECK-NEXT: vsrl.vv v9, v8, v91163; CHECK-NEXT: vsll.vv v8, v8, v101164; CHECK-NEXT: vor.vv v8, v9, v81165; CHECK-NEXT: ret1166;1167; CHECK-ZVKB-LABEL: vror_vv_nxv2i32:1168; CHECK-ZVKB: # %bb.0:1169; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma1170; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91171; CHECK-ZVKB-NEXT: ret1172 %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b)1173 ret <vscale x 2 x i32> %x1174}1175 1176define <vscale x 2 x i32> @vror_vx_nxv2i32(<vscale x 2 x i32> %a, i32 %b) {1177; CHECK-RV32-LABEL: vror_vx_nxv2i32:1178; CHECK-RV32: # %bb.0:1179; CHECK-RV32-NEXT: andi a1, a0, 311180; CHECK-RV32-NEXT: neg a0, a01181; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m1, ta, ma1182; CHECK-RV32-NEXT: vsrl.vx v9, v8, a11183; CHECK-RV32-NEXT: andi a0, a0, 311184; CHECK-RV32-NEXT: vsll.vx v8, v8, a01185; CHECK-RV32-NEXT: vor.vv v8, v9, v81186; CHECK-RV32-NEXT: ret1187;1188; CHECK-RV64-LABEL: vror_vx_nxv2i32:1189; CHECK-RV64: # %bb.0:1190; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m1, ta, ma1191; CHECK-RV64-NEXT: vmv.v.x v9, a01192; CHECK-RV64-NEXT: li a0, 311193; CHECK-RV64-NEXT: vand.vx v10, v9, a01194; CHECK-RV64-NEXT: vrsub.vi v9, v9, 01195; CHECK-RV64-NEXT: vsrl.vv v10, v8, v101196; CHECK-RV64-NEXT: vand.vx v9, v9, a01197; CHECK-RV64-NEXT: vsll.vv v8, v8, v91198; CHECK-RV64-NEXT: vor.vv v8, v10, v81199; CHECK-RV64-NEXT: ret1200;1201; CHECK-ZVKB-LABEL: vror_vx_nxv2i32:1202; CHECK-ZVKB: # %bb.0:1203; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m1, ta, ma1204; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01205; CHECK-ZVKB-NEXT: ret1206 %b.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01207 %b.splat = shufflevector <vscale x 2 x i32> %b.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1208 %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> %b.splat)1209 ret <vscale x 2 x i32> %x1210}1211 1212define <vscale x 2 x i32> @vror_vi_nxv2i32(<vscale x 2 x i32> %a) {1213; CHECK-LABEL: vror_vi_nxv2i32:1214; CHECK: # %bb.0:1215; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1216; CHECK-NEXT: vsll.vi v9, v8, 311217; CHECK-NEXT: vsrl.vi v8, v8, 11218; CHECK-NEXT: vor.vv v8, v8, v91219; CHECK-NEXT: ret1220;1221; CHECK-ZVKB-LABEL: vror_vi_nxv2i32:1222; CHECK-ZVKB: # %bb.0:1223; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma1224; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11225; CHECK-ZVKB-NEXT: ret1226 %x = call <vscale x 2 x i32> @llvm.fshr.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> splat (i32 1))1227 ret <vscale x 2 x i32> %x1228}1229 1230define <vscale x 2 x i32> @vror_vi_rotl_nxv2i32(<vscale x 2 x i32> %a) {1231; CHECK-LABEL: vror_vi_rotl_nxv2i32:1232; CHECK: # %bb.0:1233; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma1234; CHECK-NEXT: vsrl.vi v9, v8, 311235; CHECK-NEXT: vadd.vv v8, v8, v81236; CHECK-NEXT: vor.vv v8, v8, v91237; CHECK-NEXT: ret1238;1239; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i32:1240; CHECK-ZVKB: # %bb.0:1241; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m1, ta, ma1242; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311243; CHECK-ZVKB-NEXT: ret1244 %x = call <vscale x 2 x i32> @llvm.fshl.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %a, <vscale x 2 x i32> splat (i32 1))1245 ret <vscale x 2 x i32> %x1246}1247 1248define <vscale x 4 x i32> @vror_vv_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {1249; CHECK-LABEL: vror_vv_nxv4i32:1250; CHECK: # %bb.0:1251; CHECK-NEXT: li a0, 311252; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma1253; CHECK-NEXT: vrsub.vi v12, v10, 01254; CHECK-NEXT: vand.vx v10, v10, a01255; CHECK-NEXT: vand.vx v12, v12, a01256; CHECK-NEXT: vsrl.vv v10, v8, v101257; CHECK-NEXT: vsll.vv v8, v8, v121258; CHECK-NEXT: vor.vv v8, v10, v81259; CHECK-NEXT: ret1260;1261; CHECK-ZVKB-LABEL: vror_vv_nxv4i32:1262; CHECK-ZVKB: # %bb.0:1263; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma1264; CHECK-ZVKB-NEXT: vror.vv v8, v8, v101265; CHECK-ZVKB-NEXT: ret1266 %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)1267 ret <vscale x 4 x i32> %x1268}1269 1270define <vscale x 4 x i32> @vror_vx_nxv4i32(<vscale x 4 x i32> %a, i32 %b) {1271; CHECK-RV32-LABEL: vror_vx_nxv4i32:1272; CHECK-RV32: # %bb.0:1273; CHECK-RV32-NEXT: andi a1, a0, 311274; CHECK-RV32-NEXT: neg a0, a01275; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m2, ta, ma1276; CHECK-RV32-NEXT: vsrl.vx v10, v8, a11277; CHECK-RV32-NEXT: andi a0, a0, 311278; CHECK-RV32-NEXT: vsll.vx v8, v8, a01279; CHECK-RV32-NEXT: vor.vv v8, v10, v81280; CHECK-RV32-NEXT: ret1281;1282; CHECK-RV64-LABEL: vror_vx_nxv4i32:1283; CHECK-RV64: # %bb.0:1284; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma1285; CHECK-RV64-NEXT: vmv.v.x v10, a01286; CHECK-RV64-NEXT: li a0, 311287; CHECK-RV64-NEXT: vand.vx v12, v10, a01288; CHECK-RV64-NEXT: vrsub.vi v10, v10, 01289; CHECK-RV64-NEXT: vsrl.vv v12, v8, v121290; CHECK-RV64-NEXT: vand.vx v10, v10, a01291; CHECK-RV64-NEXT: vsll.vv v8, v8, v101292; CHECK-RV64-NEXT: vor.vv v8, v12, v81293; CHECK-RV64-NEXT: ret1294;1295; CHECK-ZVKB-LABEL: vror_vx_nxv4i32:1296; CHECK-ZVKB: # %bb.0:1297; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m2, ta, ma1298; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01299; CHECK-ZVKB-NEXT: ret1300 %b.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01301 %b.splat = shufflevector <vscale x 4 x i32> %b.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1302 %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b.splat)1303 ret <vscale x 4 x i32> %x1304}1305 1306define <vscale x 4 x i32> @vror_vi_nxv4i32(<vscale x 4 x i32> %a) {1307; CHECK-LABEL: vror_vi_nxv4i32:1308; CHECK: # %bb.0:1309; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1310; CHECK-NEXT: vsll.vi v10, v8, 311311; CHECK-NEXT: vsrl.vi v8, v8, 11312; CHECK-NEXT: vor.vv v8, v8, v101313; CHECK-NEXT: ret1314;1315; CHECK-ZVKB-LABEL: vror_vi_nxv4i32:1316; CHECK-ZVKB: # %bb.0:1317; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma1318; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11319; CHECK-ZVKB-NEXT: ret1320 %x = call <vscale x 4 x i32> @llvm.fshr.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))1321 ret <vscale x 4 x i32> %x1322}1323 1324define <vscale x 4 x i32> @vror_vi_rotl_nxv4i32(<vscale x 4 x i32> %a) {1325; CHECK-LABEL: vror_vi_rotl_nxv4i32:1326; CHECK: # %bb.0:1327; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma1328; CHECK-NEXT: vsrl.vi v10, v8, 311329; CHECK-NEXT: vadd.vv v8, v8, v81330; CHECK-NEXT: vor.vv v8, v8, v101331; CHECK-NEXT: ret1332;1333; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i32:1334; CHECK-ZVKB: # %bb.0:1335; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m2, ta, ma1336; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311337; CHECK-ZVKB-NEXT: ret1338 %x = call <vscale x 4 x i32> @llvm.fshl.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %a, <vscale x 4 x i32> splat (i32 1))1339 ret <vscale x 4 x i32> %x1340}1341 1342define <vscale x 8 x i32> @vror_vv_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {1343; CHECK-LABEL: vror_vv_nxv8i32:1344; CHECK: # %bb.0:1345; CHECK-NEXT: li a0, 311346; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma1347; CHECK-NEXT: vrsub.vi v16, v12, 01348; CHECK-NEXT: vand.vx v12, v12, a01349; CHECK-NEXT: vand.vx v16, v16, a01350; CHECK-NEXT: vsrl.vv v12, v8, v121351; CHECK-NEXT: vsll.vv v8, v8, v161352; CHECK-NEXT: vor.vv v8, v12, v81353; CHECK-NEXT: ret1354;1355; CHECK-ZVKB-LABEL: vror_vv_nxv8i32:1356; CHECK-ZVKB: # %bb.0:1357; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma1358; CHECK-ZVKB-NEXT: vror.vv v8, v8, v121359; CHECK-ZVKB-NEXT: ret1360 %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b)1361 ret <vscale x 8 x i32> %x1362}1363 1364define <vscale x 8 x i32> @vror_vx_nxv8i32(<vscale x 8 x i32> %a, i32 %b) {1365; CHECK-RV32-LABEL: vror_vx_nxv8i32:1366; CHECK-RV32: # %bb.0:1367; CHECK-RV32-NEXT: andi a1, a0, 311368; CHECK-RV32-NEXT: neg a0, a01369; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m4, ta, ma1370; CHECK-RV32-NEXT: vsrl.vx v12, v8, a11371; CHECK-RV32-NEXT: andi a0, a0, 311372; CHECK-RV32-NEXT: vsll.vx v8, v8, a01373; CHECK-RV32-NEXT: vor.vv v8, v12, v81374; CHECK-RV32-NEXT: ret1375;1376; CHECK-RV64-LABEL: vror_vx_nxv8i32:1377; CHECK-RV64: # %bb.0:1378; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma1379; CHECK-RV64-NEXT: vmv.v.x v12, a01380; CHECK-RV64-NEXT: li a0, 311381; CHECK-RV64-NEXT: vand.vx v16, v12, a01382; CHECK-RV64-NEXT: vrsub.vi v12, v12, 01383; CHECK-RV64-NEXT: vsrl.vv v16, v8, v161384; CHECK-RV64-NEXT: vand.vx v12, v12, a01385; CHECK-RV64-NEXT: vsll.vv v8, v8, v121386; CHECK-RV64-NEXT: vor.vv v8, v16, v81387; CHECK-RV64-NEXT: ret1388;1389; CHECK-ZVKB-LABEL: vror_vx_nxv8i32:1390; CHECK-ZVKB: # %bb.0:1391; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m4, ta, ma1392; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01393; CHECK-ZVKB-NEXT: ret1394 %b.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01395 %b.splat = shufflevector <vscale x 8 x i32> %b.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1396 %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> %b.splat)1397 ret <vscale x 8 x i32> %x1398}1399 1400define <vscale x 8 x i32> @vror_vi_nxv8i32(<vscale x 8 x i32> %a) {1401; CHECK-LABEL: vror_vi_nxv8i32:1402; CHECK: # %bb.0:1403; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1404; CHECK-NEXT: vsll.vi v12, v8, 311405; CHECK-NEXT: vsrl.vi v8, v8, 11406; CHECK-NEXT: vor.vv v8, v8, v121407; CHECK-NEXT: ret1408;1409; CHECK-ZVKB-LABEL: vror_vi_nxv8i32:1410; CHECK-ZVKB: # %bb.0:1411; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma1412; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11413; CHECK-ZVKB-NEXT: ret1414 %x = call <vscale x 8 x i32> @llvm.fshr.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> splat (i32 1))1415 ret <vscale x 8 x i32> %x1416}1417 1418define <vscale x 8 x i32> @vror_vi_rotl_nxv8i32(<vscale x 8 x i32> %a) {1419; CHECK-LABEL: vror_vi_rotl_nxv8i32:1420; CHECK: # %bb.0:1421; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma1422; CHECK-NEXT: vsrl.vi v12, v8, 311423; CHECK-NEXT: vadd.vv v8, v8, v81424; CHECK-NEXT: vor.vv v8, v8, v121425; CHECK-NEXT: ret1426;1427; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i32:1428; CHECK-ZVKB: # %bb.0:1429; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m4, ta, ma1430; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311431; CHECK-ZVKB-NEXT: ret1432 %x = call <vscale x 8 x i32> @llvm.fshl.nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %a, <vscale x 8 x i32> splat (i32 1))1433 ret <vscale x 8 x i32> %x1434}1435 1436define <vscale x 16 x i32> @vror_vv_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {1437; CHECK-LABEL: vror_vv_nxv16i32:1438; CHECK: # %bb.0:1439; CHECK-NEXT: li a0, 311440; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma1441; CHECK-NEXT: vrsub.vi v24, v16, 01442; CHECK-NEXT: vand.vx v16, v16, a01443; CHECK-NEXT: vand.vx v24, v24, a01444; CHECK-NEXT: vsrl.vv v16, v8, v161445; CHECK-NEXT: vsll.vv v8, v8, v241446; CHECK-NEXT: vor.vv v8, v16, v81447; CHECK-NEXT: ret1448;1449; CHECK-ZVKB-LABEL: vror_vv_nxv16i32:1450; CHECK-ZVKB: # %bb.0:1451; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma1452; CHECK-ZVKB-NEXT: vror.vv v8, v8, v161453; CHECK-ZVKB-NEXT: ret1454 %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b)1455 ret <vscale x 16 x i32> %x1456}1457 1458define <vscale x 16 x i32> @vror_vx_nxv16i32(<vscale x 16 x i32> %a, i32 %b) {1459; CHECK-RV32-LABEL: vror_vx_nxv16i32:1460; CHECK-RV32: # %bb.0:1461; CHECK-RV32-NEXT: andi a1, a0, 311462; CHECK-RV32-NEXT: neg a0, a01463; CHECK-RV32-NEXT: vsetvli a2, zero, e32, m8, ta, ma1464; CHECK-RV32-NEXT: vsrl.vx v16, v8, a11465; CHECK-RV32-NEXT: andi a0, a0, 311466; CHECK-RV32-NEXT: vsll.vx v8, v8, a01467; CHECK-RV32-NEXT: vor.vv v8, v16, v81468; CHECK-RV32-NEXT: ret1469;1470; CHECK-RV64-LABEL: vror_vx_nxv16i32:1471; CHECK-RV64: # %bb.0:1472; CHECK-RV64-NEXT: vsetvli a1, zero, e32, m8, ta, ma1473; CHECK-RV64-NEXT: vmv.v.x v16, a01474; CHECK-RV64-NEXT: li a0, 311475; CHECK-RV64-NEXT: vand.vx v24, v16, a01476; CHECK-RV64-NEXT: vrsub.vi v16, v16, 01477; CHECK-RV64-NEXT: vsrl.vv v24, v8, v241478; CHECK-RV64-NEXT: vand.vx v16, v16, a01479; CHECK-RV64-NEXT: vsll.vv v8, v8, v161480; CHECK-RV64-NEXT: vor.vv v8, v24, v81481; CHECK-RV64-NEXT: ret1482;1483; CHECK-ZVKB-LABEL: vror_vx_nxv16i32:1484; CHECK-ZVKB: # %bb.0:1485; CHECK-ZVKB-NEXT: vsetvli a1, zero, e32, m8, ta, ma1486; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01487; CHECK-ZVKB-NEXT: ret1488 %b.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01489 %b.splat = shufflevector <vscale x 16 x i32> %b.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1490 %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> %b.splat)1491 ret <vscale x 16 x i32> %x1492}1493 1494define <vscale x 16 x i32> @vror_vi_nxv16i32(<vscale x 16 x i32> %a) {1495; CHECK-LABEL: vror_vi_nxv16i32:1496; CHECK: # %bb.0:1497; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1498; CHECK-NEXT: vsll.vi v16, v8, 311499; CHECK-NEXT: vsrl.vi v8, v8, 11500; CHECK-NEXT: vor.vv v8, v8, v161501; CHECK-NEXT: ret1502;1503; CHECK-ZVKB-LABEL: vror_vi_nxv16i32:1504; CHECK-ZVKB: # %bb.0:1505; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma1506; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11507; CHECK-ZVKB-NEXT: ret1508 %x = call <vscale x 16 x i32> @llvm.fshr.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> splat (i32 1))1509 ret <vscale x 16 x i32> %x1510}1511 1512define <vscale x 16 x i32> @vror_vi_rotl_nxv16i32(<vscale x 16 x i32> %a) {1513; CHECK-LABEL: vror_vi_rotl_nxv16i32:1514; CHECK: # %bb.0:1515; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma1516; CHECK-NEXT: vsrl.vi v16, v8, 311517; CHECK-NEXT: vadd.vv v8, v8, v81518; CHECK-NEXT: vor.vv v8, v8, v161519; CHECK-NEXT: ret1520;1521; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv16i32:1522; CHECK-ZVKB: # %bb.0:1523; CHECK-ZVKB-NEXT: vsetvli a0, zero, e32, m8, ta, ma1524; CHECK-ZVKB-NEXT: vror.vi v8, v8, 311525; CHECK-ZVKB-NEXT: ret1526 %x = call <vscale x 16 x i32> @llvm.fshl.nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %a, <vscale x 16 x i32> splat (i32 1))1527 ret <vscale x 16 x i32> %x1528}1529 1530define <vscale x 1 x i64> @vror_vv_nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %b) {1531; CHECK-LABEL: vror_vv_nxv1i64:1532; CHECK: # %bb.0:1533; CHECK-NEXT: li a0, 631534; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1535; CHECK-NEXT: vrsub.vi v10, v9, 01536; CHECK-NEXT: vand.vx v9, v9, a01537; CHECK-NEXT: vand.vx v10, v10, a01538; CHECK-NEXT: vsrl.vv v9, v8, v91539; CHECK-NEXT: vsll.vv v8, v8, v101540; CHECK-NEXT: vor.vv v8, v9, v81541; CHECK-NEXT: ret1542;1543; CHECK-ZVKB-LABEL: vror_vv_nxv1i64:1544; CHECK-ZVKB: # %bb.0:1545; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma1546; CHECK-ZVKB-NEXT: vror.vv v8, v8, v91547; CHECK-ZVKB-NEXT: ret1548 %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b)1549 ret <vscale x 1 x i64> %x1550}1551 1552define <vscale x 1 x i64> @vror_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {1553; CHECK-RV32-LABEL: vror_vx_nxv1i64:1554; CHECK-RV32: # %bb.0:1555; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma1556; CHECK-RV32-NEXT: vmv.v.x v9, a01557; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma1558; CHECK-RV32-NEXT: vmv.v.i v10, 01559; CHECK-RV32-NEXT: vwsub.vx v11, v10, a01560; CHECK-RV32-NEXT: li a0, 631561; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma1562; CHECK-RV32-NEXT: vand.vx v9, v9, a01563; CHECK-RV32-NEXT: vand.vx v10, v11, a01564; CHECK-RV32-NEXT: vsll.vv v10, v8, v101565; CHECK-RV32-NEXT: vsrl.vv v8, v8, v91566; CHECK-RV32-NEXT: vor.vv v8, v8, v101567; CHECK-RV32-NEXT: ret1568;1569; CHECK-RV64-LABEL: vror_vx_nxv1i64:1570; CHECK-RV64: # %bb.0:1571; CHECK-RV64-NEXT: andi a1, a0, 631572; CHECK-RV64-NEXT: neg a0, a01573; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m1, ta, ma1574; CHECK-RV64-NEXT: vsrl.vx v9, v8, a11575; CHECK-RV64-NEXT: andi a0, a0, 631576; CHECK-RV64-NEXT: vsll.vx v8, v8, a01577; CHECK-RV64-NEXT: vor.vv v8, v9, v81578; CHECK-RV64-NEXT: ret1579;1580; CHECK-ZVKB-LABEL: vror_vx_nxv1i64:1581; CHECK-ZVKB: # %bb.0:1582; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m1, ta, ma1583; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01584; CHECK-ZVKB-NEXT: ret1585 %b.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01586 %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1587 %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)1588 ret <vscale x 1 x i64> %x1589}1590 1591define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) {1592; CHECK-LABEL: vror_vi_nxv1i64:1593; CHECK: # %bb.0:1594; CHECK-NEXT: li a0, 631595; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1596; CHECK-NEXT: vsll.vx v9, v8, a01597; CHECK-NEXT: vsrl.vi v8, v8, 11598; CHECK-NEXT: vor.vv v8, v8, v91599; CHECK-NEXT: ret1600;1601; CHECK-ZVKB-LABEL: vror_vi_nxv1i64:1602; CHECK-ZVKB: # %bb.0:1603; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma1604; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11605; CHECK-ZVKB-NEXT: ret1606 %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> splat (i64 1))1607 ret <vscale x 1 x i64> %x1608}1609 1610define <vscale x 1 x i64> @vror_vi_rotl_nxv1i64(<vscale x 1 x i64> %a) {1611; CHECK-LABEL: vror_vi_rotl_nxv1i64:1612; CHECK: # %bb.0:1613; CHECK-NEXT: li a0, 631614; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma1615; CHECK-NEXT: vsrl.vx v9, v8, a01616; CHECK-NEXT: vadd.vv v8, v8, v81617; CHECK-NEXT: vor.vv v8, v8, v91618; CHECK-NEXT: ret1619;1620; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv1i64:1621; CHECK-ZVKB: # %bb.0:1622; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m1, ta, ma1623; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631624; CHECK-ZVKB-NEXT: ret1625 %x = call <vscale x 1 x i64> @llvm.fshl.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> splat (i64 1))1626 ret <vscale x 1 x i64> %x1627}1628 1629define <vscale x 2 x i64> @vror_vv_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {1630; CHECK-LABEL: vror_vv_nxv2i64:1631; CHECK: # %bb.0:1632; CHECK-NEXT: li a0, 631633; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma1634; CHECK-NEXT: vrsub.vi v12, v10, 01635; CHECK-NEXT: vand.vx v10, v10, a01636; CHECK-NEXT: vand.vx v12, v12, a01637; CHECK-NEXT: vsrl.vv v10, v8, v101638; CHECK-NEXT: vsll.vv v8, v8, v121639; CHECK-NEXT: vor.vv v8, v10, v81640; CHECK-NEXT: ret1641;1642; CHECK-ZVKB-LABEL: vror_vv_nxv2i64:1643; CHECK-ZVKB: # %bb.0:1644; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma1645; CHECK-ZVKB-NEXT: vror.vv v8, v8, v101646; CHECK-ZVKB-NEXT: ret1647 %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b)1648 ret <vscale x 2 x i64> %x1649}1650 1651define <vscale x 2 x i64> @vror_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {1652; CHECK-RV32-LABEL: vror_vx_nxv2i64:1653; CHECK-RV32: # %bb.0:1654; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma1655; CHECK-RV32-NEXT: vmv.v.x v10, a01656; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma1657; CHECK-RV32-NEXT: vmv.v.i v14, 01658; CHECK-RV32-NEXT: vwsub.vx v12, v14, a01659; CHECK-RV32-NEXT: li a0, 631660; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma1661; CHECK-RV32-NEXT: vand.vx v10, v10, a01662; CHECK-RV32-NEXT: vand.vx v12, v12, a01663; CHECK-RV32-NEXT: vsll.vv v12, v8, v121664; CHECK-RV32-NEXT: vsrl.vv v8, v8, v101665; CHECK-RV32-NEXT: vor.vv v8, v8, v121666; CHECK-RV32-NEXT: ret1667;1668; CHECK-RV64-LABEL: vror_vx_nxv2i64:1669; CHECK-RV64: # %bb.0:1670; CHECK-RV64-NEXT: andi a1, a0, 631671; CHECK-RV64-NEXT: neg a0, a01672; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m2, ta, ma1673; CHECK-RV64-NEXT: vsrl.vx v10, v8, a11674; CHECK-RV64-NEXT: andi a0, a0, 631675; CHECK-RV64-NEXT: vsll.vx v8, v8, a01676; CHECK-RV64-NEXT: vor.vv v8, v10, v81677; CHECK-RV64-NEXT: ret1678;1679; CHECK-ZVKB-LABEL: vror_vx_nxv2i64:1680; CHECK-ZVKB: # %bb.0:1681; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m2, ta, ma1682; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01683; CHECK-ZVKB-NEXT: ret1684 %b.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01685 %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1686 %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)1687 ret <vscale x 2 x i64> %x1688}1689 1690define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) {1691; CHECK-LABEL: vror_vi_nxv2i64:1692; CHECK: # %bb.0:1693; CHECK-NEXT: li a0, 631694; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma1695; CHECK-NEXT: vsll.vx v10, v8, a01696; CHECK-NEXT: vsrl.vi v8, v8, 11697; CHECK-NEXT: vor.vv v8, v8, v101698; CHECK-NEXT: ret1699;1700; CHECK-ZVKB-LABEL: vror_vi_nxv2i64:1701; CHECK-ZVKB: # %bb.0:1702; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma1703; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11704; CHECK-ZVKB-NEXT: ret1705 %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat (i64 1))1706 ret <vscale x 2 x i64> %x1707}1708 1709define <vscale x 2 x i64> @vror_vi_rotl_nxv2i64(<vscale x 2 x i64> %a) {1710; CHECK-LABEL: vror_vi_rotl_nxv2i64:1711; CHECK: # %bb.0:1712; CHECK-NEXT: li a0, 631713; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma1714; CHECK-NEXT: vsrl.vx v10, v8, a01715; CHECK-NEXT: vadd.vv v8, v8, v81716; CHECK-NEXT: vor.vv v8, v8, v101717; CHECK-NEXT: ret1718;1719; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv2i64:1720; CHECK-ZVKB: # %bb.0:1721; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m2, ta, ma1722; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631723; CHECK-ZVKB-NEXT: ret1724 %x = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> splat (i64 1))1725 ret <vscale x 2 x i64> %x1726}1727 1728define <vscale x 4 x i64> @vror_vv_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {1729; CHECK-LABEL: vror_vv_nxv4i64:1730; CHECK: # %bb.0:1731; CHECK-NEXT: li a0, 631732; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma1733; CHECK-NEXT: vrsub.vi v16, v12, 01734; CHECK-NEXT: vand.vx v12, v12, a01735; CHECK-NEXT: vand.vx v16, v16, a01736; CHECK-NEXT: vsrl.vv v12, v8, v121737; CHECK-NEXT: vsll.vv v8, v8, v161738; CHECK-NEXT: vor.vv v8, v12, v81739; CHECK-NEXT: ret1740;1741; CHECK-ZVKB-LABEL: vror_vv_nxv4i64:1742; CHECK-ZVKB: # %bb.0:1743; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1744; CHECK-ZVKB-NEXT: vror.vv v8, v8, v121745; CHECK-ZVKB-NEXT: ret1746 %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b)1747 ret <vscale x 4 x i64> %x1748}1749 1750define <vscale x 4 x i64> @vror_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {1751; CHECK-RV32-LABEL: vror_vx_nxv4i64:1752; CHECK-RV32: # %bb.0:1753; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma1754; CHECK-RV32-NEXT: vmv.v.x v12, a01755; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma1756; CHECK-RV32-NEXT: vmv.v.i v20, 01757; CHECK-RV32-NEXT: vwsub.vx v16, v20, a01758; CHECK-RV32-NEXT: li a0, 631759; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma1760; CHECK-RV32-NEXT: vand.vx v12, v12, a01761; CHECK-RV32-NEXT: vand.vx v16, v16, a01762; CHECK-RV32-NEXT: vsll.vv v16, v8, v161763; CHECK-RV32-NEXT: vsrl.vv v8, v8, v121764; CHECK-RV32-NEXT: vor.vv v8, v8, v161765; CHECK-RV32-NEXT: ret1766;1767; CHECK-RV64-LABEL: vror_vx_nxv4i64:1768; CHECK-RV64: # %bb.0:1769; CHECK-RV64-NEXT: andi a1, a0, 631770; CHECK-RV64-NEXT: neg a0, a01771; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m4, ta, ma1772; CHECK-RV64-NEXT: vsrl.vx v12, v8, a11773; CHECK-RV64-NEXT: andi a0, a0, 631774; CHECK-RV64-NEXT: vsll.vx v8, v8, a01775; CHECK-RV64-NEXT: vor.vv v8, v12, v81776; CHECK-RV64-NEXT: ret1777;1778; CHECK-ZVKB-LABEL: vror_vx_nxv4i64:1779; CHECK-ZVKB: # %bb.0:1780; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m4, ta, ma1781; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01782; CHECK-ZVKB-NEXT: ret1783 %b.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01784 %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1785 %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)1786 ret <vscale x 4 x i64> %x1787}1788 1789define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) {1790; CHECK-LABEL: vror_vi_nxv4i64:1791; CHECK: # %bb.0:1792; CHECK-NEXT: li a0, 631793; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma1794; CHECK-NEXT: vsll.vx v12, v8, a01795; CHECK-NEXT: vsrl.vi v8, v8, 11796; CHECK-NEXT: vor.vv v8, v8, v121797; CHECK-NEXT: ret1798;1799; CHECK-ZVKB-LABEL: vror_vi_nxv4i64:1800; CHECK-ZVKB: # %bb.0:1801; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1802; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11803; CHECK-ZVKB-NEXT: ret1804 %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> splat (i64 1))1805 ret <vscale x 4 x i64> %x1806}1807 1808define <vscale x 4 x i64> @vror_vi_rotl_nxv4i64(<vscale x 4 x i64> %a) {1809; CHECK-LABEL: vror_vi_rotl_nxv4i64:1810; CHECK: # %bb.0:1811; CHECK-NEXT: li a0, 631812; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma1813; CHECK-NEXT: vsrl.vx v12, v8, a01814; CHECK-NEXT: vadd.vv v8, v8, v81815; CHECK-NEXT: vor.vv v8, v8, v121816; CHECK-NEXT: ret1817;1818; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv4i64:1819; CHECK-ZVKB: # %bb.0:1820; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m4, ta, ma1821; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631822; CHECK-ZVKB-NEXT: ret1823 %x = call <vscale x 4 x i64> @llvm.fshl.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> splat (i64 1))1824 ret <vscale x 4 x i64> %x1825}1826 1827define <vscale x 8 x i64> @vror_vv_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {1828; CHECK-LABEL: vror_vv_nxv8i64:1829; CHECK: # %bb.0:1830; CHECK-NEXT: li a0, 631831; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1832; CHECK-NEXT: vrsub.vi v24, v16, 01833; CHECK-NEXT: vand.vx v16, v16, a01834; CHECK-NEXT: vand.vx v24, v24, a01835; CHECK-NEXT: vsrl.vv v16, v8, v161836; CHECK-NEXT: vsll.vv v8, v8, v241837; CHECK-NEXT: vor.vv v8, v16, v81838; CHECK-NEXT: ret1839;1840; CHECK-ZVKB-LABEL: vror_vv_nxv8i64:1841; CHECK-ZVKB: # %bb.0:1842; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1843; CHECK-ZVKB-NEXT: vror.vv v8, v8, v161844; CHECK-ZVKB-NEXT: ret1845 %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b)1846 ret <vscale x 8 x i64> %x1847}1848 1849define <vscale x 8 x i64> @vror_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {1850; CHECK-RV32-LABEL: vror_vx_nxv8i64:1851; CHECK-RV32: # %bb.0:1852; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma1853; CHECK-RV32-NEXT: vmv.v.x v16, a01854; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma1855; CHECK-RV32-NEXT: vmv.v.i v4, 01856; CHECK-RV32-NEXT: vwsub.vx v24, v4, a01857; CHECK-RV32-NEXT: li a0, 631858; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma1859; CHECK-RV32-NEXT: vand.vx v16, v16, a01860; CHECK-RV32-NEXT: vand.vx v24, v24, a01861; CHECK-RV32-NEXT: vsll.vv v24, v8, v241862; CHECK-RV32-NEXT: vsrl.vv v8, v8, v161863; CHECK-RV32-NEXT: vor.vv v8, v8, v241864; CHECK-RV32-NEXT: ret1865;1866; CHECK-RV64-LABEL: vror_vx_nxv8i64:1867; CHECK-RV64: # %bb.0:1868; CHECK-RV64-NEXT: andi a1, a0, 631869; CHECK-RV64-NEXT: neg a0, a01870; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma1871; CHECK-RV64-NEXT: vsrl.vx v16, v8, a11872; CHECK-RV64-NEXT: andi a0, a0, 631873; CHECK-RV64-NEXT: vsll.vx v8, v8, a01874; CHECK-RV64-NEXT: vor.vv v8, v16, v81875; CHECK-RV64-NEXT: ret1876;1877; CHECK-ZVKB-LABEL: vror_vx_nxv8i64:1878; CHECK-ZVKB: # %bb.0:1879; CHECK-ZVKB-NEXT: vsetvli a1, zero, e64, m8, ta, ma1880; CHECK-ZVKB-NEXT: vror.vx v8, v8, a01881; CHECK-ZVKB-NEXT: ret1882 %b.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01883 %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1884 %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)1885 ret <vscale x 8 x i64> %x1886}1887 1888define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) {1889; CHECK-LABEL: vror_vi_nxv8i64:1890; CHECK: # %bb.0:1891; CHECK-NEXT: li a0, 631892; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1893; CHECK-NEXT: vsll.vx v16, v8, a01894; CHECK-NEXT: vsrl.vi v8, v8, 11895; CHECK-NEXT: vor.vv v8, v8, v161896; CHECK-NEXT: ret1897;1898; CHECK-ZVKB-LABEL: vror_vi_nxv8i64:1899; CHECK-ZVKB: # %bb.0:1900; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1901; CHECK-ZVKB-NEXT: vror.vi v8, v8, 11902; CHECK-ZVKB-NEXT: ret1903 %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> splat (i64 1))1904 ret <vscale x 8 x i64> %x1905}1906 1907define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) {1908; CHECK-LABEL: vror_vi_rotl_nxv8i64:1909; CHECK: # %bb.0:1910; CHECK-NEXT: li a0, 631911; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma1912; CHECK-NEXT: vsrl.vx v16, v8, a01913; CHECK-NEXT: vadd.vv v8, v8, v81914; CHECK-NEXT: vor.vv v8, v8, v161915; CHECK-NEXT: ret1916;1917; CHECK-ZVKB-LABEL: vror_vi_rotl_nxv8i64:1918; CHECK-ZVKB: # %bb.0:1919; CHECK-ZVKB-NEXT: vsetvli a0, zero, e64, m8, ta, ma1920; CHECK-ZVKB-NEXT: vror.vi v8, v8, 631921; CHECK-ZVKB-NEXT: ret1922 %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> splat (i64 1))1923 ret <vscale x 8 x i64> %x1924}1925