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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV323; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV644 5define <vscale x 1 x i8> @vrsub_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {6; CHECK-LABEL: vrsub_vx_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma9; CHECK-NEXT: vrsub.vx v8, v8, a010; CHECK-NEXT: ret11 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 012 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer13 %vc = sub <vscale x 1 x i8> %splat, %va14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vrsub_vi_nxv1i8_0(<vscale x 1 x i8> %va) {18; CHECK-LABEL: vrsub_vi_nxv1i8_0:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma21; CHECK-NEXT: vrsub.vi v8, v8, -422; CHECK-NEXT: ret23 %vc = sub <vscale x 1 x i8> splat (i8 -4), %va24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 2 x i8> @vrsub_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {28; CHECK-LABEL: vrsub_vx_nxv2i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma31; CHECK-NEXT: vrsub.vx v8, v8, a032; CHECK-NEXT: ret33 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 034 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer35 %vc = sub <vscale x 2 x i8> %splat, %va36 ret <vscale x 2 x i8> %vc37}38 39define <vscale x 2 x i8> @vrsub_vi_nxv2i8_0(<vscale x 2 x i8> %va) {40; CHECK-LABEL: vrsub_vi_nxv2i8_0:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma43; CHECK-NEXT: vrsub.vi v8, v8, -444; CHECK-NEXT: ret45 %vc = sub <vscale x 2 x i8> splat (i8 -4), %va46 ret <vscale x 2 x i8> %vc47}48 49define <vscale x 4 x i8> @vrsub_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {50; CHECK-LABEL: vrsub_vx_nxv4i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma53; CHECK-NEXT: vrsub.vx v8, v8, a054; CHECK-NEXT: ret55 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 056 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer57 %vc = sub <vscale x 4 x i8> %splat, %va58 ret <vscale x 4 x i8> %vc59}60 61define <vscale x 4 x i8> @vrsub_vi_nxv4i8_0(<vscale x 4 x i8> %va) {62; CHECK-LABEL: vrsub_vi_nxv4i8_0:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma65; CHECK-NEXT: vrsub.vi v8, v8, -466; CHECK-NEXT: ret67 %vc = sub <vscale x 4 x i8> splat (i8 -4), %va68 ret <vscale x 4 x i8> %vc69}70 71define <vscale x 8 x i8> @vrsub_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {72; CHECK-LABEL: vrsub_vx_nxv8i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma75; CHECK-NEXT: vrsub.vx v8, v8, a076; CHECK-NEXT: ret77 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 078 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer79 %vc = sub <vscale x 8 x i8> %splat, %va80 ret <vscale x 8 x i8> %vc81}82 83define <vscale x 8 x i8> @vrsub_vi_nxv8i8_0(<vscale x 8 x i8> %va) {84; CHECK-LABEL: vrsub_vi_nxv8i8_0:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma87; CHECK-NEXT: vrsub.vi v8, v8, -488; CHECK-NEXT: ret89 %vc = sub <vscale x 8 x i8> splat (i8 -4), %va90 ret <vscale x 8 x i8> %vc91}92 93define <vscale x 16 x i8> @vrsub_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {94; CHECK-LABEL: vrsub_vx_nxv16i8:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma97; CHECK-NEXT: vrsub.vx v8, v8, a098; CHECK-NEXT: ret99 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0100 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer101 %vc = sub <vscale x 16 x i8> %splat, %va102 ret <vscale x 16 x i8> %vc103}104 105define <vscale x 16 x i8> @vrsub_vi_nxv16i8_0(<vscale x 16 x i8> %va) {106; CHECK-LABEL: vrsub_vi_nxv16i8_0:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma109; CHECK-NEXT: vrsub.vi v8, v8, -4110; CHECK-NEXT: ret111 %vc = sub <vscale x 16 x i8> splat (i8 -4), %va112 ret <vscale x 16 x i8> %vc113}114 115define <vscale x 32 x i8> @vrsub_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {116; CHECK-LABEL: vrsub_vx_nxv32i8:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma119; CHECK-NEXT: vrsub.vx v8, v8, a0120; CHECK-NEXT: ret121 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0122 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer123 %vc = sub <vscale x 32 x i8> %splat, %va124 ret <vscale x 32 x i8> %vc125}126 127define <vscale x 32 x i8> @vrsub_vi_nxv32i8_0(<vscale x 32 x i8> %va) {128; CHECK-LABEL: vrsub_vi_nxv32i8_0:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma131; CHECK-NEXT: vrsub.vi v8, v8, -4132; CHECK-NEXT: ret133 %vc = sub <vscale x 32 x i8> splat (i8 -4), %va134 ret <vscale x 32 x i8> %vc135}136 137define <vscale x 64 x i8> @vrsub_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {138; CHECK-LABEL: vrsub_vx_nxv64i8:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma141; CHECK-NEXT: vrsub.vx v8, v8, a0142; CHECK-NEXT: ret143 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0144 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer145 %vc = sub <vscale x 64 x i8> %splat, %va146 ret <vscale x 64 x i8> %vc147}148 149define <vscale x 64 x i8> @vrsub_vi_nxv64i8_0(<vscale x 64 x i8> %va) {150; CHECK-LABEL: vrsub_vi_nxv64i8_0:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma153; CHECK-NEXT: vrsub.vi v8, v8, -4154; CHECK-NEXT: ret155 %vc = sub <vscale x 64 x i8> splat (i8 -4), %va156 ret <vscale x 64 x i8> %vc157}158 159define <vscale x 1 x i16> @vrsub_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {160; CHECK-LABEL: vrsub_vx_nxv1i16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma163; CHECK-NEXT: vrsub.vx v8, v8, a0164; CHECK-NEXT: ret165 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0166 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer167 %vc = sub <vscale x 1 x i16> %splat, %va168 ret <vscale x 1 x i16> %vc169}170 171define <vscale x 1 x i16> @vrsub_vi_nxv1i16_0(<vscale x 1 x i16> %va) {172; CHECK-LABEL: vrsub_vi_nxv1i16_0:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma175; CHECK-NEXT: vrsub.vi v8, v8, -4176; CHECK-NEXT: ret177 %vc = sub <vscale x 1 x i16> splat (i16 -4), %va178 ret <vscale x 1 x i16> %vc179}180 181define <vscale x 2 x i16> @vrsub_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {182; CHECK-LABEL: vrsub_vx_nxv2i16:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma185; CHECK-NEXT: vrsub.vx v8, v8, a0186; CHECK-NEXT: ret187 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0188 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer189 %vc = sub <vscale x 2 x i16> %splat, %va190 ret <vscale x 2 x i16> %vc191}192 193define <vscale x 2 x i16> @vrsub_vi_nxv2i16_0(<vscale x 2 x i16> %va) {194; CHECK-LABEL: vrsub_vi_nxv2i16_0:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma197; CHECK-NEXT: vrsub.vi v8, v8, -4198; CHECK-NEXT: ret199 %vc = sub <vscale x 2 x i16> splat (i16 -4), %va200 ret <vscale x 2 x i16> %vc201}202 203define <vscale x 4 x i16> @vrsub_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {204; CHECK-LABEL: vrsub_vx_nxv4i16:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma207; CHECK-NEXT: vrsub.vx v8, v8, a0208; CHECK-NEXT: ret209 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0210 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer211 %vc = sub <vscale x 4 x i16> %splat, %va212 ret <vscale x 4 x i16> %vc213}214 215define <vscale x 4 x i16> @vrsub_vi_nxv4i16_0(<vscale x 4 x i16> %va) {216; CHECK-LABEL: vrsub_vi_nxv4i16_0:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma219; CHECK-NEXT: vrsub.vi v8, v8, -4220; CHECK-NEXT: ret221 %vc = sub <vscale x 4 x i16> splat (i16 -4), %va222 ret <vscale x 4 x i16> %vc223}224 225define <vscale x 8 x i16> @vrsub_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {226; CHECK-LABEL: vrsub_vx_nxv8i16:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma229; CHECK-NEXT: vrsub.vx v8, v8, a0230; CHECK-NEXT: ret231 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0232 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer233 %vc = sub <vscale x 8 x i16> %splat, %va234 ret <vscale x 8 x i16> %vc235}236 237define <vscale x 8 x i16> @vrsub_vi_nxv8i16_0(<vscale x 8 x i16> %va) {238; CHECK-LABEL: vrsub_vi_nxv8i16_0:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma241; CHECK-NEXT: vrsub.vi v8, v8, -4242; CHECK-NEXT: ret243 %vc = sub <vscale x 8 x i16> splat (i16 -4), %va244 ret <vscale x 8 x i16> %vc245}246 247define <vscale x 16 x i16> @vrsub_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {248; CHECK-LABEL: vrsub_vx_nxv16i16:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma251; CHECK-NEXT: vrsub.vx v8, v8, a0252; CHECK-NEXT: ret253 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0254 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer255 %vc = sub <vscale x 16 x i16> %splat, %va256 ret <vscale x 16 x i16> %vc257}258 259define <vscale x 16 x i16> @vrsub_vi_nxv16i16_0(<vscale x 16 x i16> %va) {260; CHECK-LABEL: vrsub_vi_nxv16i16_0:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma263; CHECK-NEXT: vrsub.vi v8, v8, -4264; CHECK-NEXT: ret265 %vc = sub <vscale x 16 x i16> splat (i16 -4), %va266 ret <vscale x 16 x i16> %vc267}268 269define <vscale x 32 x i16> @vrsub_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {270; CHECK-LABEL: vrsub_vx_nxv32i16:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma273; CHECK-NEXT: vrsub.vx v8, v8, a0274; CHECK-NEXT: ret275 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0276 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer277 %vc = sub <vscale x 32 x i16> %splat, %va278 ret <vscale x 32 x i16> %vc279}280 281define <vscale x 32 x i16> @vrsub_vi_nxv32i16_0(<vscale x 32 x i16> %va) {282; CHECK-LABEL: vrsub_vi_nxv32i16_0:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma285; CHECK-NEXT: vrsub.vi v8, v8, -4286; CHECK-NEXT: ret287 %vc = sub <vscale x 32 x i16> splat (i16 -4), %va288 ret <vscale x 32 x i16> %vc289}290 291define <vscale x 1 x i32> @vrsub_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {292; CHECK-LABEL: vrsub_vx_nxv1i32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma295; CHECK-NEXT: vrsub.vx v8, v8, a0296; CHECK-NEXT: ret297 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0298 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer299 %vc = sub <vscale x 1 x i32> %splat, %va300 ret <vscale x 1 x i32> %vc301}302 303define <vscale x 1 x i32> @vrsub_vi_nxv1i32_0(<vscale x 1 x i32> %va) {304; CHECK-LABEL: vrsub_vi_nxv1i32_0:305; CHECK: # %bb.0:306; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma307; CHECK-NEXT: vrsub.vi v8, v8, -4308; CHECK-NEXT: ret309 %vc = sub <vscale x 1 x i32> splat (i32 -4), %va310 ret <vscale x 1 x i32> %vc311}312 313define <vscale x 2 x i32> @vrsub_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {314; CHECK-LABEL: vrsub_vx_nxv2i32:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma317; CHECK-NEXT: vrsub.vx v8, v8, a0318; CHECK-NEXT: ret319 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0320 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer321 %vc = sub <vscale x 2 x i32> %splat, %va322 ret <vscale x 2 x i32> %vc323}324 325define <vscale x 2 x i32> @vrsub_vi_nxv2i32_0(<vscale x 2 x i32> %va) {326; CHECK-LABEL: vrsub_vi_nxv2i32_0:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma329; CHECK-NEXT: vrsub.vi v8, v8, -4330; CHECK-NEXT: ret331 %vc = sub <vscale x 2 x i32> splat (i32 -4), %va332 ret <vscale x 2 x i32> %vc333}334 335define <vscale x 4 x i32> @vrsub_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {336; CHECK-LABEL: vrsub_vx_nxv4i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma339; CHECK-NEXT: vrsub.vx v8, v8, a0340; CHECK-NEXT: ret341 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0342 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer343 %vc = sub <vscale x 4 x i32> %splat, %va344 ret <vscale x 4 x i32> %vc345}346 347define <vscale x 4 x i32> @vrsub_vi_nxv4i32_0(<vscale x 4 x i32> %va) {348; CHECK-LABEL: vrsub_vi_nxv4i32_0:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma351; CHECK-NEXT: vrsub.vi v8, v8, -4352; CHECK-NEXT: ret353 %vc = sub <vscale x 4 x i32> splat (i32 -4), %va354 ret <vscale x 4 x i32> %vc355}356 357define <vscale x 8 x i32> @vrsub_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {358; CHECK-LABEL: vrsub_vx_nxv8i32:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma361; CHECK-NEXT: vrsub.vx v8, v8, a0362; CHECK-NEXT: ret363 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0364 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer365 %vc = sub <vscale x 8 x i32> %splat, %va366 ret <vscale x 8 x i32> %vc367}368 369define <vscale x 8 x i32> @vrsub_vi_nxv8i32_0(<vscale x 8 x i32> %va) {370; CHECK-LABEL: vrsub_vi_nxv8i32_0:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma373; CHECK-NEXT: vrsub.vi v8, v8, -4374; CHECK-NEXT: ret375 %vc = sub <vscale x 8 x i32> splat (i32 -4), %va376 ret <vscale x 8 x i32> %vc377}378 379define <vscale x 16 x i32> @vrsub_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {380; CHECK-LABEL: vrsub_vx_nxv16i32:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma383; CHECK-NEXT: vrsub.vx v8, v8, a0384; CHECK-NEXT: ret385 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0386 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer387 %vc = sub <vscale x 16 x i32> %splat, %va388 ret <vscale x 16 x i32> %vc389}390 391define <vscale x 16 x i32> @vrsub_vi_nxv16i32_0(<vscale x 16 x i32> %va) {392; CHECK-LABEL: vrsub_vi_nxv16i32_0:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma395; CHECK-NEXT: vrsub.vi v8, v8, -4396; CHECK-NEXT: ret397 %vc = sub <vscale x 16 x i32> splat (i32 -4), %va398 ret <vscale x 16 x i32> %vc399}400 401define <vscale x 1 x i64> @vrsub_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {402; RV32-LABEL: vrsub_vx_nxv1i64:403; RV32: # %bb.0:404; RV32-NEXT: addi sp, sp, -16405; RV32-NEXT: .cfi_def_cfa_offset 16406; RV32-NEXT: sw a0, 8(sp)407; RV32-NEXT: sw a1, 12(sp)408; RV32-NEXT: addi a0, sp, 8409; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma410; RV32-NEXT: vlse64.v v9, (a0), zero411; RV32-NEXT: vsub.vv v8, v9, v8412; RV32-NEXT: addi sp, sp, 16413; RV32-NEXT: .cfi_def_cfa_offset 0414; RV32-NEXT: ret415;416; RV64-LABEL: vrsub_vx_nxv1i64:417; RV64: # %bb.0:418; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma419; RV64-NEXT: vrsub.vx v8, v8, a0420; RV64-NEXT: ret421 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0422 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer423 %vc = sub <vscale x 1 x i64> %splat, %va424 ret <vscale x 1 x i64> %vc425}426 427define <vscale x 1 x i64> @vrsub_vi_nxv1i64_0(<vscale x 1 x i64> %va) {428; CHECK-LABEL: vrsub_vi_nxv1i64_0:429; CHECK: # %bb.0:430; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma431; CHECK-NEXT: vrsub.vi v8, v8, -4432; CHECK-NEXT: ret433 %vc = sub <vscale x 1 x i64> splat (i64 -4), %va434 ret <vscale x 1 x i64> %vc435}436 437define <vscale x 2 x i64> @vrsub_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {438; RV32-LABEL: vrsub_vx_nxv2i64:439; RV32: # %bb.0:440; RV32-NEXT: addi sp, sp, -16441; RV32-NEXT: .cfi_def_cfa_offset 16442; RV32-NEXT: sw a0, 8(sp)443; RV32-NEXT: sw a1, 12(sp)444; RV32-NEXT: addi a0, sp, 8445; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma446; RV32-NEXT: vlse64.v v10, (a0), zero447; RV32-NEXT: vsub.vv v8, v10, v8448; RV32-NEXT: addi sp, sp, 16449; RV32-NEXT: .cfi_def_cfa_offset 0450; RV32-NEXT: ret451;452; RV64-LABEL: vrsub_vx_nxv2i64:453; RV64: # %bb.0:454; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma455; RV64-NEXT: vrsub.vx v8, v8, a0456; RV64-NEXT: ret457 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0458 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer459 %vc = sub <vscale x 2 x i64> %splat, %va460 ret <vscale x 2 x i64> %vc461}462 463define <vscale x 2 x i64> @vrsub_vi_nxv2i64_0(<vscale x 2 x i64> %va) {464; CHECK-LABEL: vrsub_vi_nxv2i64_0:465; CHECK: # %bb.0:466; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma467; CHECK-NEXT: vrsub.vi v8, v8, -4468; CHECK-NEXT: ret469 %vc = sub <vscale x 2 x i64> splat (i64 -4), %va470 ret <vscale x 2 x i64> %vc471}472 473define <vscale x 4 x i64> @vrsub_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {474; RV32-LABEL: vrsub_vx_nxv4i64:475; RV32: # %bb.0:476; RV32-NEXT: addi sp, sp, -16477; RV32-NEXT: .cfi_def_cfa_offset 16478; RV32-NEXT: sw a0, 8(sp)479; RV32-NEXT: sw a1, 12(sp)480; RV32-NEXT: addi a0, sp, 8481; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma482; RV32-NEXT: vlse64.v v12, (a0), zero483; RV32-NEXT: vsub.vv v8, v12, v8484; RV32-NEXT: addi sp, sp, 16485; RV32-NEXT: .cfi_def_cfa_offset 0486; RV32-NEXT: ret487;488; RV64-LABEL: vrsub_vx_nxv4i64:489; RV64: # %bb.0:490; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma491; RV64-NEXT: vrsub.vx v8, v8, a0492; RV64-NEXT: ret493 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0494 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer495 %vc = sub <vscale x 4 x i64> %splat, %va496 ret <vscale x 4 x i64> %vc497}498 499define <vscale x 4 x i64> @vrsub_vi_nxv4i64_0(<vscale x 4 x i64> %va) {500; CHECK-LABEL: vrsub_vi_nxv4i64_0:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma503; CHECK-NEXT: vrsub.vi v8, v8, -4504; CHECK-NEXT: ret505 %vc = sub <vscale x 4 x i64> splat (i64 -4), %va506 ret <vscale x 4 x i64> %vc507}508 509define <vscale x 8 x i64> @vrsub_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {510; RV32-LABEL: vrsub_vx_nxv8i64:511; RV32: # %bb.0:512; RV32-NEXT: addi sp, sp, -16513; RV32-NEXT: .cfi_def_cfa_offset 16514; RV32-NEXT: sw a0, 8(sp)515; RV32-NEXT: sw a1, 12(sp)516; RV32-NEXT: addi a0, sp, 8517; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma518; RV32-NEXT: vlse64.v v16, (a0), zero519; RV32-NEXT: vsub.vv v8, v16, v8520; RV32-NEXT: addi sp, sp, 16521; RV32-NEXT: .cfi_def_cfa_offset 0522; RV32-NEXT: ret523;524; RV64-LABEL: vrsub_vx_nxv8i64:525; RV64: # %bb.0:526; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma527; RV64-NEXT: vrsub.vx v8, v8, a0528; RV64-NEXT: ret529 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0530 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer531 %vc = sub <vscale x 8 x i64> %splat, %va532 ret <vscale x 8 x i64> %vc533}534 535define <vscale x 8 x i64> @vrsub_vi_nxv8i64_0(<vscale x 8 x i64> %va) {536; CHECK-LABEL: vrsub_vi_nxv8i64_0:537; CHECK: # %bb.0:538; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma539; CHECK-NEXT: vrsub.vi v8, v8, -4540; CHECK-NEXT: ret541 %vc = sub <vscale x 8 x i64> splat (i64 -4), %va542 ret <vscale x 8 x i64> %vc543}544