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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i8_nxv1i8_i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vrsub.vx v8, v8, a012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i8> %0,17 i8 %1,18 iXLen %2)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i8_nxv1i8_i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu27; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(31 <vscale x 1 x i8> %0,32 <vscale x 1 x i8> %1,33 i8 %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i8_nxv2i8_i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma44; CHECK-NEXT: vrsub.vx v8, v8, a045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(48 <vscale x 2 x i8> poison,49 <vscale x 2 x i8> %0,50 i8 %1,51 iXLen %2)52 53 ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i8_nxv2i8_i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu60; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(64 <vscale x 2 x i8> %0,65 <vscale x 2 x i8> %1,66 i8 %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i8_nxv4i8_i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma77; CHECK-NEXT: vrsub.vx v8, v8, a078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(81 <vscale x 4 x i8> poison,82 <vscale x 4 x i8> %0,83 i8 %1,84 iXLen %2)85 86 ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i8_nxv4i8_i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu93; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(97 <vscale x 4 x i8> %0,98 <vscale x 4 x i8> %1,99 i8 %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i8_nxv8i8_i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma110; CHECK-NEXT: vrsub.vx v8, v8, a0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(114 <vscale x 8 x i8> poison,115 <vscale x 8 x i8> %0,116 i8 %1,117 iXLen %2)118 119 ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i8_nxv8i8_i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu126; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(130 <vscale x 8 x i8> %0,131 <vscale x 8 x i8> %1,132 i8 %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i8_nxv16i8_i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma143; CHECK-NEXT: vrsub.vx v8, v8, a0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(147 <vscale x 16 x i8> poison,148 <vscale x 16 x i8> %0,149 i8 %1,150 iXLen %2)151 152 ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i8_nxv16i8_i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu159; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(163 <vscale x 16 x i8> %0,164 <vscale x 16 x i8> %1,165 i8 %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i8_nxv32i8_i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma176; CHECK-NEXT: vrsub.vx v8, v8, a0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(180 <vscale x 32 x i8> poison,181 <vscale x 32 x i8> %0,182 i8 %1,183 iXLen %2)184 185 ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i8_nxv32i8_i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu192; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(196 <vscale x 32 x i8> %0,197 <vscale x 32 x i8> %1,198 i8 %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 1)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 64 x i8> @intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vrsub_vx_nxv64i8_nxv64i8_i8:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma209; CHECK-NEXT: vrsub.vx v8, v8, a0210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(213 <vscale x 64 x i8> poison,214 <vscale x 64 x i8> %0,215 i8 %1,216 iXLen %2)217 218 ret <vscale x 64 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv64i8_nxv64i8_i8:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu225; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(229 <vscale x 64 x i8> %0,230 <vscale x 64 x i8> %1,231 i8 %2,232 <vscale x 64 x i1> %3,233 iXLen %4, iXLen 1)234 235 ret <vscale x 64 x i8> %a236}237 238define <vscale x 1 x i16> @intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i16_nxv1i16_i16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma242; CHECK-NEXT: vrsub.vx v8, v8, a0243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(246 <vscale x 1 x i16> poison,247 <vscale x 1 x i16> %0,248 i16 %1,249 iXLen %2)250 251 ret <vscale x 1 x i16> %a252}253 254define <vscale x 1 x i16> @intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i16_nxv1i16_i16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu258; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(262 <vscale x 1 x i16> %0,263 <vscale x 1 x i16> %1,264 i16 %2,265 <vscale x 1 x i1> %3,266 iXLen %4, iXLen 1)267 268 ret <vscale x 1 x i16> %a269}270 271define <vscale x 2 x i16> @intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {272; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i16_nxv2i16_i16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma275; CHECK-NEXT: vrsub.vx v8, v8, a0276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(279 <vscale x 2 x i16> poison,280 <vscale x 2 x i16> %0,281 i16 %1,282 iXLen %2)283 284 ret <vscale x 2 x i16> %a285}286 287define <vscale x 2 x i16> @intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i16_nxv2i16_i16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu291; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(295 <vscale x 2 x i16> %0,296 <vscale x 2 x i16> %1,297 i16 %2,298 <vscale x 2 x i1> %3,299 iXLen %4, iXLen 1)300 301 ret <vscale x 2 x i16> %a302}303 304define <vscale x 4 x i16> @intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i16_nxv4i16_i16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma308; CHECK-NEXT: vrsub.vx v8, v8, a0309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(312 <vscale x 4 x i16> poison,313 <vscale x 4 x i16> %0,314 i16 %1,315 iXLen %2)316 317 ret <vscale x 4 x i16> %a318}319 320define <vscale x 4 x i16> @intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i16_nxv4i16_i16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu324; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(328 <vscale x 4 x i16> %0,329 <vscale x 4 x i16> %1,330 i16 %2,331 <vscale x 4 x i1> %3,332 iXLen %4, iXLen 1)333 334 ret <vscale x 4 x i16> %a335}336 337define <vscale x 8 x i16> @intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i16_nxv8i16_i16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma341; CHECK-NEXT: vrsub.vx v8, v8, a0342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(345 <vscale x 8 x i16> poison,346 <vscale x 8 x i16> %0,347 i16 %1,348 iXLen %2)349 350 ret <vscale x 8 x i16> %a351}352 353define <vscale x 8 x i16> @intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i16_nxv8i16_i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu357; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(361 <vscale x 8 x i16> %0,362 <vscale x 8 x i16> %1,363 i16 %2,364 <vscale x 8 x i1> %3,365 iXLen %4, iXLen 1)366 367 ret <vscale x 8 x i16> %a368}369 370define <vscale x 16 x i16> @intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {371; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i16_nxv16i16_i16:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma374; CHECK-NEXT: vrsub.vx v8, v8, a0375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(378 <vscale x 16 x i16> poison,379 <vscale x 16 x i16> %0,380 i16 %1,381 iXLen %2)382 383 ret <vscale x 16 x i16> %a384}385 386define <vscale x 16 x i16> @intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i16_nxv16i16_i16:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu390; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(394 <vscale x 16 x i16> %0,395 <vscale x 16 x i16> %1,396 i16 %2,397 <vscale x 16 x i1> %3,398 iXLen %4, iXLen 1)399 400 ret <vscale x 16 x i16> %a401}402 403define <vscale x 32 x i16> @intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {404; CHECK-LABEL: intrinsic_vrsub_vx_nxv32i16_nxv32i16_i16:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma407; CHECK-NEXT: vrsub.vx v8, v8, a0408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(411 <vscale x 32 x i16> poison,412 <vscale x 32 x i16> %0,413 i16 %1,414 iXLen %2)415 416 ret <vscale x 32 x i16> %a417}418 419define <vscale x 32 x i16> @intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv32i16_nxv32i16_i16:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu423; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(427 <vscale x 32 x i16> %0,428 <vscale x 32 x i16> %1,429 i16 %2,430 <vscale x 32 x i1> %3,431 iXLen %4, iXLen 1)432 433 ret <vscale x 32 x i16> %a434}435 436define <vscale x 1 x i32> @intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vrsub_vx_nxv1i32_nxv1i32_i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma440; CHECK-NEXT: vrsub.vx v8, v8, a0441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(444 <vscale x 1 x i32> poison,445 <vscale x 1 x i32> %0,446 i32 %1,447 iXLen %2)448 449 ret <vscale x 1 x i32> %a450}451 452define <vscale x 1 x i32> @intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv1i32_nxv1i32_i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu456; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(460 <vscale x 1 x i32> %0,461 <vscale x 1 x i32> %1,462 i32 %2,463 <vscale x 1 x i1> %3,464 iXLen %4, iXLen 1)465 466 ret <vscale x 1 x i32> %a467}468 469define <vscale x 2 x i32> @intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vrsub_vx_nxv2i32_nxv2i32_i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma473; CHECK-NEXT: vrsub.vx v8, v8, a0474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(477 <vscale x 2 x i32> poison,478 <vscale x 2 x i32> %0,479 i32 %1,480 iXLen %2)481 482 ret <vscale x 2 x i32> %a483}484 485define <vscale x 2 x i32> @intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv2i32_nxv2i32_i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu489; CHECK-NEXT: vrsub.vx v8, v9, a0, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(493 <vscale x 2 x i32> %0,494 <vscale x 2 x i32> %1,495 i32 %2,496 <vscale x 2 x i1> %3,497 iXLen %4, iXLen 1)498 499 ret <vscale x 2 x i32> %a500}501 502define <vscale x 4 x i32> @intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {503; CHECK-LABEL: intrinsic_vrsub_vx_nxv4i32_nxv4i32_i32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma506; CHECK-NEXT: vrsub.vx v8, v8, a0507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(510 <vscale x 4 x i32> poison,511 <vscale x 4 x i32> %0,512 i32 %1,513 iXLen %2)514 515 ret <vscale x 4 x i32> %a516}517 518define <vscale x 4 x i32> @intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv4i32_nxv4i32_i32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu522; CHECK-NEXT: vrsub.vx v8, v10, a0, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(526 <vscale x 4 x i32> %0,527 <vscale x 4 x i32> %1,528 i32 %2,529 <vscale x 4 x i1> %3,530 iXLen %4, iXLen 1)531 532 ret <vscale x 4 x i32> %a533}534 535define <vscale x 8 x i32> @intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {536; CHECK-LABEL: intrinsic_vrsub_vx_nxv8i32_nxv8i32_i32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma539; CHECK-NEXT: vrsub.vx v8, v8, a0540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(543 <vscale x 8 x i32> poison,544 <vscale x 8 x i32> %0,545 i32 %1,546 iXLen %2)547 548 ret <vscale x 8 x i32> %a549}550 551define <vscale x 8 x i32> @intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv8i32_nxv8i32_i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu555; CHECK-NEXT: vrsub.vx v8, v12, a0, v0.t556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(559 <vscale x 8 x i32> %0,560 <vscale x 8 x i32> %1,561 i32 %2,562 <vscale x 8 x i1> %3,563 iXLen %4, iXLen 1)564 565 ret <vscale x 8 x i32> %a566}567 568define <vscale x 16 x i32> @intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {569; CHECK-LABEL: intrinsic_vrsub_vx_nxv16i32_nxv16i32_i32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma572; CHECK-NEXT: vrsub.vx v8, v8, a0573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(576 <vscale x 16 x i32> poison,577 <vscale x 16 x i32> %0,578 i32 %1,579 iXLen %2)580 581 ret <vscale x 16 x i32> %a582}583 584define <vscale x 16 x i32> @intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vrsub_mask_vx_nxv16i32_nxv16i32_i32:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu588; CHECK-NEXT: vrsub.vx v8, v16, a0, v0.t589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(592 <vscale x 16 x i32> %0,593 <vscale x 16 x i32> %1,594 i32 %2,595 <vscale x 16 x i1> %3,596 iXLen %4, iXLen 1)597 598 ret <vscale x 16 x i32> %a599}600 601define <vscale x 1 x i64> @intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {602; RV32-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:603; RV32: # %bb.0: # %entry604; RV32-NEXT: addi sp, sp, -16605; RV32-NEXT: sw a0, 8(sp)606; RV32-NEXT: sw a1, 12(sp)607; RV32-NEXT: addi a0, sp, 8608; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma609; RV32-NEXT: vlse64.v v9, (a0), zero610; RV32-NEXT: vsub.vv v8, v9, v8611; RV32-NEXT: addi sp, sp, 16612; RV32-NEXT: ret613;614; RV64-LABEL: intrinsic_vrsub_vx_nxv1i64_nxv1i64_i64:615; RV64: # %bb.0: # %entry616; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma617; RV64-NEXT: vrsub.vx v8, v8, a0618; RV64-NEXT: ret619entry:620 %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(621 <vscale x 1 x i64> poison,622 <vscale x 1 x i64> %0,623 i64 %1,624 iXLen %2)625 626 ret <vscale x 1 x i64> %a627}628 629define <vscale x 1 x i64> @intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {630; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:631; RV32: # %bb.0: # %entry632; RV32-NEXT: addi sp, sp, -16633; RV32-NEXT: sw a0, 8(sp)634; RV32-NEXT: sw a1, 12(sp)635; RV32-NEXT: addi a0, sp, 8636; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu637; RV32-NEXT: vlse64.v v10, (a0), zero638; RV32-NEXT: vsub.vv v8, v10, v9, v0.t639; RV32-NEXT: addi sp, sp, 16640; RV32-NEXT: ret641;642; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv1i64_nxv1i64_i64:643; RV64: # %bb.0: # %entry644; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu645; RV64-NEXT: vrsub.vx v8, v9, a0, v0.t646; RV64-NEXT: ret647entry:648 %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(649 <vscale x 1 x i64> %0,650 <vscale x 1 x i64> %1,651 i64 %2,652 <vscale x 1 x i1> %3,653 iXLen %4, iXLen 1)654 655 ret <vscale x 1 x i64> %a656}657 658define <vscale x 2 x i64> @intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {659; RV32-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:660; RV32: # %bb.0: # %entry661; RV32-NEXT: addi sp, sp, -16662; RV32-NEXT: sw a0, 8(sp)663; RV32-NEXT: sw a1, 12(sp)664; RV32-NEXT: addi a0, sp, 8665; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma666; RV32-NEXT: vlse64.v v10, (a0), zero667; RV32-NEXT: vsub.vv v8, v10, v8668; RV32-NEXT: addi sp, sp, 16669; RV32-NEXT: ret670;671; RV64-LABEL: intrinsic_vrsub_vx_nxv2i64_nxv2i64_i64:672; RV64: # %bb.0: # %entry673; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma674; RV64-NEXT: vrsub.vx v8, v8, a0675; RV64-NEXT: ret676entry:677 %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(678 <vscale x 2 x i64> poison,679 <vscale x 2 x i64> %0,680 i64 %1,681 iXLen %2)682 683 ret <vscale x 2 x i64> %a684}685 686define <vscale x 2 x i64> @intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {687; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:688; RV32: # %bb.0: # %entry689; RV32-NEXT: addi sp, sp, -16690; RV32-NEXT: sw a0, 8(sp)691; RV32-NEXT: sw a1, 12(sp)692; RV32-NEXT: addi a0, sp, 8693; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu694; RV32-NEXT: vlse64.v v12, (a0), zero695; RV32-NEXT: vsub.vv v8, v12, v10, v0.t696; RV32-NEXT: addi sp, sp, 16697; RV32-NEXT: ret698;699; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv2i64_nxv2i64_i64:700; RV64: # %bb.0: # %entry701; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu702; RV64-NEXT: vrsub.vx v8, v10, a0, v0.t703; RV64-NEXT: ret704entry:705 %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(706 <vscale x 2 x i64> %0,707 <vscale x 2 x i64> %1,708 i64 %2,709 <vscale x 2 x i1> %3,710 iXLen %4, iXLen 1)711 712 ret <vscale x 2 x i64> %a713}714 715define <vscale x 4 x i64> @intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {716; RV32-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:717; RV32: # %bb.0: # %entry718; RV32-NEXT: addi sp, sp, -16719; RV32-NEXT: sw a0, 8(sp)720; RV32-NEXT: sw a1, 12(sp)721; RV32-NEXT: addi a0, sp, 8722; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma723; RV32-NEXT: vlse64.v v12, (a0), zero724; RV32-NEXT: vsub.vv v8, v12, v8725; RV32-NEXT: addi sp, sp, 16726; RV32-NEXT: ret727;728; RV64-LABEL: intrinsic_vrsub_vx_nxv4i64_nxv4i64_i64:729; RV64: # %bb.0: # %entry730; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma731; RV64-NEXT: vrsub.vx v8, v8, a0732; RV64-NEXT: ret733entry:734 %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(735 <vscale x 4 x i64> poison,736 <vscale x 4 x i64> %0,737 i64 %1,738 iXLen %2)739 740 ret <vscale x 4 x i64> %a741}742 743define <vscale x 4 x i64> @intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {744; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:745; RV32: # %bb.0: # %entry746; RV32-NEXT: addi sp, sp, -16747; RV32-NEXT: sw a0, 8(sp)748; RV32-NEXT: sw a1, 12(sp)749; RV32-NEXT: addi a0, sp, 8750; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu751; RV32-NEXT: vlse64.v v16, (a0), zero752; RV32-NEXT: vsub.vv v8, v16, v12, v0.t753; RV32-NEXT: addi sp, sp, 16754; RV32-NEXT: ret755;756; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv4i64_nxv4i64_i64:757; RV64: # %bb.0: # %entry758; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu759; RV64-NEXT: vrsub.vx v8, v12, a0, v0.t760; RV64-NEXT: ret761entry:762 %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(763 <vscale x 4 x i64> %0,764 <vscale x 4 x i64> %1,765 i64 %2,766 <vscale x 4 x i1> %3,767 iXLen %4, iXLen 1)768 769 ret <vscale x 4 x i64> %a770}771 772define <vscale x 8 x i64> @intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {773; RV32-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:774; RV32: # %bb.0: # %entry775; RV32-NEXT: addi sp, sp, -16776; RV32-NEXT: sw a0, 8(sp)777; RV32-NEXT: sw a1, 12(sp)778; RV32-NEXT: addi a0, sp, 8779; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma780; RV32-NEXT: vlse64.v v16, (a0), zero781; RV32-NEXT: vsub.vv v8, v16, v8782; RV32-NEXT: addi sp, sp, 16783; RV32-NEXT: ret784;785; RV64-LABEL: intrinsic_vrsub_vx_nxv8i64_nxv8i64_i64:786; RV64: # %bb.0: # %entry787; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma788; RV64-NEXT: vrsub.vx v8, v8, a0789; RV64-NEXT: ret790entry:791 %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(792 <vscale x 8 x i64> poison,793 <vscale x 8 x i64> %0,794 i64 %1,795 iXLen %2)796 797 ret <vscale x 8 x i64> %a798}799 800define <vscale x 8 x i64> @intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {801; RV32-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:802; RV32: # %bb.0: # %entry803; RV32-NEXT: addi sp, sp, -16804; RV32-NEXT: sw a0, 8(sp)805; RV32-NEXT: sw a1, 12(sp)806; RV32-NEXT: addi a0, sp, 8807; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu808; RV32-NEXT: vlse64.v v24, (a0), zero809; RV32-NEXT: vsub.vv v8, v24, v16, v0.t810; RV32-NEXT: addi sp, sp, 16811; RV32-NEXT: ret812;813; RV64-LABEL: intrinsic_vrsub_mask_vx_nxv8i64_nxv8i64_i64:814; RV64: # %bb.0: # %entry815; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu816; RV64-NEXT: vrsub.vx v8, v16, a0, v0.t817; RV64-NEXT: ret818entry:819 %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(820 <vscale x 8 x i64> %0,821 <vscale x 8 x i64> %1,822 i64 %2,823 <vscale x 8 x i1> %3,824 iXLen %4, iXLen 1)825 826 ret <vscale x 8 x i64> %a827}828 829define <vscale x 1 x i8> @intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, iXLen %1) nounwind {830; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i8_nxv1i8_i8:831; CHECK: # %bb.0: # %entry832; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma833; CHECK-NEXT: vrsub.vi v8, v8, 9834; CHECK-NEXT: ret835entry:836 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.nxv1i8.i8(837 <vscale x 1 x i8> poison,838 <vscale x 1 x i8> %0,839 i8 9,840 iXLen %1)841 842 ret <vscale x 1 x i8> %a843}844 845define <vscale x 1 x i8> @intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {846; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i8_nxv1i8_i8:847; CHECK: # %bb.0: # %entry848; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu849; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t850; CHECK-NEXT: ret851entry:852 %a = call <vscale x 1 x i8> @llvm.riscv.vrsub.mask.nxv1i8.i8(853 <vscale x 1 x i8> %0,854 <vscale x 1 x i8> %1,855 i8 -9,856 <vscale x 1 x i1> %2,857 iXLen %3, iXLen 1)858 859 ret <vscale x 1 x i8> %a860}861 862define <vscale x 2 x i8> @intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, iXLen %1) nounwind {863; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i8_nxv2i8_i8:864; CHECK: # %bb.0: # %entry865; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma866; CHECK-NEXT: vrsub.vi v8, v8, 9867; CHECK-NEXT: ret868entry:869 %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.nxv2i8.i8(870 <vscale x 2 x i8> poison,871 <vscale x 2 x i8> %0,872 i8 9,873 iXLen %1)874 875 ret <vscale x 2 x i8> %a876}877 878define <vscale x 2 x i8> @intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {879; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i8_nxv2i8_i8:880; CHECK: # %bb.0: # %entry881; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu882; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t883; CHECK-NEXT: ret884entry:885 %a = call <vscale x 2 x i8> @llvm.riscv.vrsub.mask.nxv2i8.i8(886 <vscale x 2 x i8> %0,887 <vscale x 2 x i8> %1,888 i8 -9,889 <vscale x 2 x i1> %2,890 iXLen %3, iXLen 1)891 892 ret <vscale x 2 x i8> %a893}894 895define <vscale x 4 x i8> @intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, iXLen %1) nounwind {896; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i8_nxv4i8_i8:897; CHECK: # %bb.0: # %entry898; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma899; CHECK-NEXT: vrsub.vi v8, v8, 9900; CHECK-NEXT: ret901entry:902 %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.nxv4i8.i8(903 <vscale x 4 x i8> poison,904 <vscale x 4 x i8> %0,905 i8 9,906 iXLen %1)907 908 ret <vscale x 4 x i8> %a909}910 911define <vscale x 4 x i8> @intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {912; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i8_nxv4i8_i8:913; CHECK: # %bb.0: # %entry914; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu915; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t916; CHECK-NEXT: ret917entry:918 %a = call <vscale x 4 x i8> @llvm.riscv.vrsub.mask.nxv4i8.i8(919 <vscale x 4 x i8> %0,920 <vscale x 4 x i8> %1,921 i8 -9,922 <vscale x 4 x i1> %2,923 iXLen %3, iXLen 1)924 925 ret <vscale x 4 x i8> %a926}927 928define <vscale x 8 x i8> @intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, iXLen %1) nounwind {929; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i8_nxv8i8_i8:930; CHECK: # %bb.0: # %entry931; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma932; CHECK-NEXT: vrsub.vi v8, v8, 9933; CHECK-NEXT: ret934entry:935 %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.nxv8i8.i8(936 <vscale x 8 x i8> poison,937 <vscale x 8 x i8> %0,938 i8 9,939 iXLen %1)940 941 ret <vscale x 8 x i8> %a942}943 944define <vscale x 8 x i8> @intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {945; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i8_nxv8i8_i8:946; CHECK: # %bb.0: # %entry947; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu948; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t949; CHECK-NEXT: ret950entry:951 %a = call <vscale x 8 x i8> @llvm.riscv.vrsub.mask.nxv8i8.i8(952 <vscale x 8 x i8> %0,953 <vscale x 8 x i8> %1,954 i8 -9,955 <vscale x 8 x i1> %2,956 iXLen %3, iXLen 1)957 958 ret <vscale x 8 x i8> %a959}960 961define <vscale x 16 x i8> @intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, iXLen %1) nounwind {962; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i8_nxv16i8_i8:963; CHECK: # %bb.0: # %entry964; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma965; CHECK-NEXT: vrsub.vi v8, v8, 9966; CHECK-NEXT: ret967entry:968 %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.nxv16i8.i8(969 <vscale x 16 x i8> poison,970 <vscale x 16 x i8> %0,971 i8 9,972 iXLen %1)973 974 ret <vscale x 16 x i8> %a975}976 977define <vscale x 16 x i8> @intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {978; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i8_nxv16i8_i8:979; CHECK: # %bb.0: # %entry980; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu981; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t982; CHECK-NEXT: ret983entry:984 %a = call <vscale x 16 x i8> @llvm.riscv.vrsub.mask.nxv16i8.i8(985 <vscale x 16 x i8> %0,986 <vscale x 16 x i8> %1,987 i8 -9,988 <vscale x 16 x i1> %2,989 iXLen %3, iXLen 1)990 991 ret <vscale x 16 x i8> %a992}993 994define <vscale x 32 x i8> @intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, iXLen %1) nounwind {995; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i8_nxv32i8_i8:996; CHECK: # %bb.0: # %entry997; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma998; CHECK-NEXT: vrsub.vi v8, v8, 9999; CHECK-NEXT: ret1000entry:1001 %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.nxv32i8.i8(1002 <vscale x 32 x i8> poison,1003 <vscale x 32 x i8> %0,1004 i8 9,1005 iXLen %1)1006 1007 ret <vscale x 32 x i8> %a1008}1009 1010define <vscale x 32 x i8> @intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1011; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i8_nxv32i8_i8:1012; CHECK: # %bb.0: # %entry1013; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu1014; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t1015; CHECK-NEXT: ret1016entry:1017 %a = call <vscale x 32 x i8> @llvm.riscv.vrsub.mask.nxv32i8.i8(1018 <vscale x 32 x i8> %0,1019 <vscale x 32 x i8> %1,1020 i8 -9,1021 <vscale x 32 x i1> %2,1022 iXLen %3, iXLen 1)1023 1024 ret <vscale x 32 x i8> %a1025}1026 1027define <vscale x 64 x i8> @intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, iXLen %1) nounwind {1028; CHECK-LABEL: intrinsic_vrsub_vi_nxv64i8_nxv64i8_i8:1029; CHECK: # %bb.0: # %entry1030; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma1031; CHECK-NEXT: vrsub.vi v8, v8, 91032; CHECK-NEXT: ret1033entry:1034 %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.nxv64i8.i8(1035 <vscale x 64 x i8> poison,1036 <vscale x 64 x i8> %0,1037 i8 9,1038 iXLen %1)1039 1040 ret <vscale x 64 x i8> %a1041}1042 1043define <vscale x 64 x i8> @intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1044; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv64i8_nxv64i8_i8:1045; CHECK: # %bb.0: # %entry1046; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu1047; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t1048; CHECK-NEXT: ret1049entry:1050 %a = call <vscale x 64 x i8> @llvm.riscv.vrsub.mask.nxv64i8.i8(1051 <vscale x 64 x i8> %0,1052 <vscale x 64 x i8> %1,1053 i8 -9,1054 <vscale x 64 x i1> %2,1055 iXLen %3, iXLen 1)1056 1057 ret <vscale x 64 x i8> %a1058}1059 1060define <vscale x 1 x i16> @intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, iXLen %1) nounwind {1061; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i16_nxv1i16_i16:1062; CHECK: # %bb.0: # %entry1063; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma1064; CHECK-NEXT: vrsub.vi v8, v8, 91065; CHECK-NEXT: ret1066entry:1067 %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.nxv1i16.i16(1068 <vscale x 1 x i16> poison,1069 <vscale x 1 x i16> %0,1070 i16 9,1071 iXLen %1)1072 1073 ret <vscale x 1 x i16> %a1074}1075 1076define <vscale x 1 x i16> @intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1077; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i16_nxv1i16_i16:1078; CHECK: # %bb.0: # %entry1079; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu1080; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t1081; CHECK-NEXT: ret1082entry:1083 %a = call <vscale x 1 x i16> @llvm.riscv.vrsub.mask.nxv1i16.i16(1084 <vscale x 1 x i16> %0,1085 <vscale x 1 x i16> %1,1086 i16 -9,1087 <vscale x 1 x i1> %2,1088 iXLen %3, iXLen 1)1089 1090 ret <vscale x 1 x i16> %a1091}1092 1093define <vscale x 2 x i16> @intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, iXLen %1) nounwind {1094; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i16_nxv2i16_i16:1095; CHECK: # %bb.0: # %entry1096; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma1097; CHECK-NEXT: vrsub.vi v8, v8, 91098; CHECK-NEXT: ret1099entry:1100 %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.nxv2i16.i16(1101 <vscale x 2 x i16> poison,1102 <vscale x 2 x i16> %0,1103 i16 9,1104 iXLen %1)1105 1106 ret <vscale x 2 x i16> %a1107}1108 1109define <vscale x 2 x i16> @intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1110; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i16_nxv2i16_i16:1111; CHECK: # %bb.0: # %entry1112; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu1113; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t1114; CHECK-NEXT: ret1115entry:1116 %a = call <vscale x 2 x i16> @llvm.riscv.vrsub.mask.nxv2i16.i16(1117 <vscale x 2 x i16> %0,1118 <vscale x 2 x i16> %1,1119 i16 -9,1120 <vscale x 2 x i1> %2,1121 iXLen %3, iXLen 1)1122 1123 ret <vscale x 2 x i16> %a1124}1125 1126define <vscale x 4 x i16> @intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, iXLen %1) nounwind {1127; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i16_nxv4i16_i16:1128; CHECK: # %bb.0: # %entry1129; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma1130; CHECK-NEXT: vrsub.vi v8, v8, 91131; CHECK-NEXT: ret1132entry:1133 %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.nxv4i16.i16(1134 <vscale x 4 x i16> poison,1135 <vscale x 4 x i16> %0,1136 i16 9,1137 iXLen %1)1138 1139 ret <vscale x 4 x i16> %a1140}1141 1142define <vscale x 4 x i16> @intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1143; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i16_nxv4i16_i16:1144; CHECK: # %bb.0: # %entry1145; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu1146; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t1147; CHECK-NEXT: ret1148entry:1149 %a = call <vscale x 4 x i16> @llvm.riscv.vrsub.mask.nxv4i16.i16(1150 <vscale x 4 x i16> %0,1151 <vscale x 4 x i16> %1,1152 i16 -9,1153 <vscale x 4 x i1> %2,1154 iXLen %3, iXLen 1)1155 1156 ret <vscale x 4 x i16> %a1157}1158 1159define <vscale x 8 x i16> @intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, iXLen %1) nounwind {1160; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i16_nxv8i16_i16:1161; CHECK: # %bb.0: # %entry1162; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma1163; CHECK-NEXT: vrsub.vi v8, v8, 91164; CHECK-NEXT: ret1165entry:1166 %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.nxv8i16.i16(1167 <vscale x 8 x i16> poison,1168 <vscale x 8 x i16> %0,1169 i16 9,1170 iXLen %1)1171 1172 ret <vscale x 8 x i16> %a1173}1174 1175define <vscale x 8 x i16> @intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1176; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i16_nxv8i16_i16:1177; CHECK: # %bb.0: # %entry1178; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu1179; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t1180; CHECK-NEXT: ret1181entry:1182 %a = call <vscale x 8 x i16> @llvm.riscv.vrsub.mask.nxv8i16.i16(1183 <vscale x 8 x i16> %0,1184 <vscale x 8 x i16> %1,1185 i16 -9,1186 <vscale x 8 x i1> %2,1187 iXLen %3, iXLen 1)1188 1189 ret <vscale x 8 x i16> %a1190}1191 1192define <vscale x 16 x i16> @intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, iXLen %1) nounwind {1193; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i16_nxv16i16_i16:1194; CHECK: # %bb.0: # %entry1195; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma1196; CHECK-NEXT: vrsub.vi v8, v8, 91197; CHECK-NEXT: ret1198entry:1199 %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.nxv16i16.i16(1200 <vscale x 16 x i16> poison,1201 <vscale x 16 x i16> %0,1202 i16 9,1203 iXLen %1)1204 1205 ret <vscale x 16 x i16> %a1206}1207 1208define <vscale x 16 x i16> @intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1209; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i16_nxv16i16_i16:1210; CHECK: # %bb.0: # %entry1211; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu1212; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t1213; CHECK-NEXT: ret1214entry:1215 %a = call <vscale x 16 x i16> @llvm.riscv.vrsub.mask.nxv16i16.i16(1216 <vscale x 16 x i16> %0,1217 <vscale x 16 x i16> %1,1218 i16 -9,1219 <vscale x 16 x i1> %2,1220 iXLen %3, iXLen 1)1221 1222 ret <vscale x 16 x i16> %a1223}1224 1225define <vscale x 32 x i16> @intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, iXLen %1) nounwind {1226; CHECK-LABEL: intrinsic_vrsub_vi_nxv32i16_nxv32i16_i16:1227; CHECK: # %bb.0: # %entry1228; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma1229; CHECK-NEXT: vrsub.vi v8, v8, 91230; CHECK-NEXT: ret1231entry:1232 %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.nxv32i16.i16(1233 <vscale x 32 x i16> poison,1234 <vscale x 32 x i16> %0,1235 i16 9,1236 iXLen %1)1237 1238 ret <vscale x 32 x i16> %a1239}1240 1241define <vscale x 32 x i16> @intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1242; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv32i16_nxv32i16_i16:1243; CHECK: # %bb.0: # %entry1244; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu1245; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t1246; CHECK-NEXT: ret1247entry:1248 %a = call <vscale x 32 x i16> @llvm.riscv.vrsub.mask.nxv32i16.i16(1249 <vscale x 32 x i16> %0,1250 <vscale x 32 x i16> %1,1251 i16 -9,1252 <vscale x 32 x i1> %2,1253 iXLen %3, iXLen 1)1254 1255 ret <vscale x 32 x i16> %a1256}1257 1258define <vscale x 1 x i32> @intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, iXLen %1) nounwind {1259; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i32_nxv1i32_i32:1260; CHECK: # %bb.0: # %entry1261; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma1262; CHECK-NEXT: vrsub.vi v8, v8, 91263; CHECK-NEXT: ret1264entry:1265 %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.nxv1i32.i32(1266 <vscale x 1 x i32> poison,1267 <vscale x 1 x i32> %0,1268 i32 9,1269 iXLen %1)1270 1271 ret <vscale x 1 x i32> %a1272}1273 1274define <vscale x 1 x i32> @intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1275; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i32_nxv1i32_i32:1276; CHECK: # %bb.0: # %entry1277; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu1278; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t1279; CHECK-NEXT: ret1280entry:1281 %a = call <vscale x 1 x i32> @llvm.riscv.vrsub.mask.nxv1i32.i32(1282 <vscale x 1 x i32> %0,1283 <vscale x 1 x i32> %1,1284 i32 -9,1285 <vscale x 1 x i1> %2,1286 iXLen %3, iXLen 1)1287 1288 ret <vscale x 1 x i32> %a1289}1290 1291define <vscale x 2 x i32> @intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, iXLen %1) nounwind {1292; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i32_nxv2i32_i32:1293; CHECK: # %bb.0: # %entry1294; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma1295; CHECK-NEXT: vrsub.vi v8, v8, 91296; CHECK-NEXT: ret1297entry:1298 %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.nxv2i32.i32(1299 <vscale x 2 x i32> poison,1300 <vscale x 2 x i32> %0,1301 i32 9,1302 iXLen %1)1303 1304 ret <vscale x 2 x i32> %a1305}1306 1307define <vscale x 2 x i32> @intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1308; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i32_nxv2i32_i32:1309; CHECK: # %bb.0: # %entry1310; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu1311; CHECK-NEXT: vrsub.vi v8, v9, -9, v0.t1312; CHECK-NEXT: ret1313entry:1314 %a = call <vscale x 2 x i32> @llvm.riscv.vrsub.mask.nxv2i32.i32(1315 <vscale x 2 x i32> %0,1316 <vscale x 2 x i32> %1,1317 i32 -9,1318 <vscale x 2 x i1> %2,1319 iXLen %3, iXLen 1)1320 1321 ret <vscale x 2 x i32> %a1322}1323 1324define <vscale x 4 x i32> @intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, iXLen %1) nounwind {1325; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i32_nxv4i32_i32:1326; CHECK: # %bb.0: # %entry1327; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1328; CHECK-NEXT: vrsub.vi v8, v8, 91329; CHECK-NEXT: ret1330entry:1331 %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.nxv4i32.i32(1332 <vscale x 4 x i32> poison,1333 <vscale x 4 x i32> %0,1334 i32 9,1335 iXLen %1)1336 1337 ret <vscale x 4 x i32> %a1338}1339 1340define <vscale x 4 x i32> @intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1341; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i32_nxv4i32_i32:1342; CHECK: # %bb.0: # %entry1343; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu1344; CHECK-NEXT: vrsub.vi v8, v10, -9, v0.t1345; CHECK-NEXT: ret1346entry:1347 %a = call <vscale x 4 x i32> @llvm.riscv.vrsub.mask.nxv4i32.i32(1348 <vscale x 4 x i32> %0,1349 <vscale x 4 x i32> %1,1350 i32 -9,1351 <vscale x 4 x i1> %2,1352 iXLen %3, iXLen 1)1353 1354 ret <vscale x 4 x i32> %a1355}1356 1357define <vscale x 8 x i32> @intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, iXLen %1) nounwind {1358; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i32_nxv8i32_i32:1359; CHECK: # %bb.0: # %entry1360; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1361; CHECK-NEXT: vrsub.vi v8, v8, 91362; CHECK-NEXT: ret1363entry:1364 %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.nxv8i32.i32(1365 <vscale x 8 x i32> poison,1366 <vscale x 8 x i32> %0,1367 i32 9,1368 iXLen %1)1369 1370 ret <vscale x 8 x i32> %a1371}1372 1373define <vscale x 8 x i32> @intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1374; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i32_nxv8i32_i32:1375; CHECK: # %bb.0: # %entry1376; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu1377; CHECK-NEXT: vrsub.vi v8, v12, -9, v0.t1378; CHECK-NEXT: ret1379entry:1380 %a = call <vscale x 8 x i32> @llvm.riscv.vrsub.mask.nxv8i32.i32(1381 <vscale x 8 x i32> %0,1382 <vscale x 8 x i32> %1,1383 i32 -9,1384 <vscale x 8 x i1> %2,1385 iXLen %3, iXLen 1)1386 1387 ret <vscale x 8 x i32> %a1388}1389 1390define <vscale x 16 x i32> @intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, iXLen %1) nounwind {1391; CHECK-LABEL: intrinsic_vrsub_vi_nxv16i32_nxv16i32_i32:1392; CHECK: # %bb.0: # %entry1393; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1394; CHECK-NEXT: vrsub.vi v8, v8, 91395; CHECK-NEXT: ret1396entry:1397 %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.nxv16i32.i32(1398 <vscale x 16 x i32> poison,1399 <vscale x 16 x i32> %0,1400 i32 9,1401 iXLen %1)1402 1403 ret <vscale x 16 x i32> %a1404}1405 1406define <vscale x 16 x i32> @intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1407; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv16i32_nxv16i32_i32:1408; CHECK: # %bb.0: # %entry1409; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu1410; CHECK-NEXT: vrsub.vi v8, v16, -9, v0.t1411; CHECK-NEXT: ret1412entry:1413 %a = call <vscale x 16 x i32> @llvm.riscv.vrsub.mask.nxv16i32.i32(1414 <vscale x 16 x i32> %0,1415 <vscale x 16 x i32> %1,1416 i32 -9,1417 <vscale x 16 x i1> %2,1418 iXLen %3, iXLen 1)1419 1420 ret <vscale x 16 x i32> %a1421}1422 1423define <vscale x 1 x i64> @intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, iXLen %1) nounwind {1424; CHECK-LABEL: intrinsic_vrsub_vi_nxv1i64_nxv1i64_i64:1425; CHECK: # %bb.0: # %entry1426; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1427; CHECK-NEXT: vrsub.vi v8, v8, 91428; CHECK-NEXT: ret1429entry:1430 %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.nxv1i64.i64(1431 <vscale x 1 x i64> poison,1432 <vscale x 1 x i64> %0,1433 i64 9,1434 iXLen %1)1435 1436 ret <vscale x 1 x i64> %a1437}1438 1439define <vscale x 1 x i64> @intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1440; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv1i64_nxv1i64_i64:1441; CHECK: # %bb.0: # %entry1442; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu1443; CHECK-NEXT: vrsub.vi v8, v9, 9, v0.t1444; CHECK-NEXT: ret1445entry:1446 %a = call <vscale x 1 x i64> @llvm.riscv.vrsub.mask.nxv1i64.i64(1447 <vscale x 1 x i64> %0,1448 <vscale x 1 x i64> %1,1449 i64 9,1450 <vscale x 1 x i1> %2,1451 iXLen %3, iXLen 1)1452 1453 ret <vscale x 1 x i64> %a1454}1455 1456define <vscale x 2 x i64> @intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, iXLen %1) nounwind {1457; CHECK-LABEL: intrinsic_vrsub_vi_nxv2i64_nxv2i64_i64:1458; CHECK: # %bb.0: # %entry1459; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1460; CHECK-NEXT: vrsub.vi v8, v8, 91461; CHECK-NEXT: ret1462entry:1463 %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.nxv2i64.i64(1464 <vscale x 2 x i64> poison,1465 <vscale x 2 x i64> %0,1466 i64 9,1467 iXLen %1)1468 1469 ret <vscale x 2 x i64> %a1470}1471 1472define <vscale x 2 x i64> @intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1473; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv2i64_nxv2i64_i64:1474; CHECK: # %bb.0: # %entry1475; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu1476; CHECK-NEXT: vrsub.vi v8, v10, 9, v0.t1477; CHECK-NEXT: ret1478entry:1479 %a = call <vscale x 2 x i64> @llvm.riscv.vrsub.mask.nxv2i64.i64(1480 <vscale x 2 x i64> %0,1481 <vscale x 2 x i64> %1,1482 i64 9,1483 <vscale x 2 x i1> %2,1484 iXLen %3, iXLen 1)1485 1486 ret <vscale x 2 x i64> %a1487}1488 1489define <vscale x 4 x i64> @intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, iXLen %1) nounwind {1490; CHECK-LABEL: intrinsic_vrsub_vi_nxv4i64_nxv4i64_i64:1491; CHECK: # %bb.0: # %entry1492; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1493; CHECK-NEXT: vrsub.vi v8, v8, 91494; CHECK-NEXT: ret1495entry:1496 %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.nxv4i64.i64(1497 <vscale x 4 x i64> poison,1498 <vscale x 4 x i64> %0,1499 i64 9,1500 iXLen %1)1501 1502 ret <vscale x 4 x i64> %a1503}1504 1505define <vscale x 4 x i64> @intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1506; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv4i64_nxv4i64_i64:1507; CHECK: # %bb.0: # %entry1508; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu1509; CHECK-NEXT: vrsub.vi v8, v12, 9, v0.t1510; CHECK-NEXT: ret1511entry:1512 %a = call <vscale x 4 x i64> @llvm.riscv.vrsub.mask.nxv4i64.i64(1513 <vscale x 4 x i64> %0,1514 <vscale x 4 x i64> %1,1515 i64 9,1516 <vscale x 4 x i1> %2,1517 iXLen %3, iXLen 1)1518 1519 ret <vscale x 4 x i64> %a1520}1521 1522define <vscale x 8 x i64> @intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, iXLen %1) nounwind {1523; CHECK-LABEL: intrinsic_vrsub_vi_nxv8i64_nxv8i64_i64:1524; CHECK: # %bb.0: # %entry1525; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1526; CHECK-NEXT: vrsub.vi v8, v8, 91527; CHECK-NEXT: ret1528entry:1529 %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.nxv8i64.i64(1530 <vscale x 8 x i64> poison,1531 <vscale x 8 x i64> %0,1532 i64 9,1533 iXLen %1)1534 1535 ret <vscale x 8 x i64> %a1536}1537 1538define <vscale x 8 x i64> @intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1539; CHECK-LABEL: intrinsic_vrsub_mask_vi_nxv8i64_nxv8i64_i64:1540; CHECK: # %bb.0: # %entry1541; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu1542; CHECK-NEXT: vrsub.vi v8, v16, 9, v0.t1543; CHECK-NEXT: ret1544entry:1545 %a = call <vscale x 8 x i64> @llvm.riscv.vrsub.mask.nxv8i64.i64(1546 <vscale x 8 x i64> %0,1547 <vscale x 8 x i64> %1,1548 i64 9,1549 <vscale x 8 x i1> %2,1550 iXLen %3, iXLen 1)1551 1552 ret <vscale x 8 x i64> %a1553}1554