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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vsadd_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vsadd_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma11; CHECK-NEXT:    vadd.vv v8, v8, v812; CHECK-NEXT:    vsra.vi v8, v8, 113; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t14; CHECK-NEXT:    li a0, 6315; CHECK-NEXT:    vmin.vx v8, v8, a0, v0.t16; CHECK-NEXT:    li a0, 19217; CHECK-NEXT:    vmax.vx v8, v8, a0, v0.t18; CHECK-NEXT:    ret19  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 020  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer21  %v = call <vscale x 8 x i7> @llvm.vp.sadd.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)22  ret <vscale x 8 x i7> %v23}24 25define <vscale x 1 x i8> @vsadd_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {26; CHECK-LABEL: vsadd_vv_nxv1i8:27; CHECK:       # %bb.0:28; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma29; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t30; CHECK-NEXT:    ret31  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)32  ret <vscale x 1 x i8> %v33}34 35define <vscale x 1 x i8> @vsadd_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {36; CHECK-LABEL: vsadd_vv_nxv1i8_unmasked:37; CHECK:       # %bb.0:38; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma39; CHECK-NEXT:    vsadd.vv v8, v8, v940; CHECK-NEXT:    ret41  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)42  ret <vscale x 1 x i8> %v43}44 45define <vscale x 1 x i8> @vsadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {46; CHECK-LABEL: vsadd_vx_nxv1i8:47; CHECK:       # %bb.0:48; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma49; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t50; CHECK-NEXT:    ret51  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 052  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer53  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)54  ret <vscale x 1 x i8> %v55}56 57define <vscale x 1 x i8> @vsadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {58; CHECK-LABEL: vsadd_vx_nxv1i8_commute:59; CHECK:       # %bb.0:60; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma61; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t62; CHECK-NEXT:    ret63  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 064  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer65  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)66  ret <vscale x 1 x i8> %v67}68 69define <vscale x 1 x i8> @vsadd_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {70; CHECK-LABEL: vsadd_vx_nxv1i8_unmasked:71; CHECK:       # %bb.0:72; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma73; CHECK-NEXT:    vsadd.vx v8, v8, a074; CHECK-NEXT:    ret75  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 076  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer77  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)78  ret <vscale x 1 x i8> %v79}80 81define <vscale x 1 x i8> @vsadd_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {82; CHECK-LABEL: vsadd_vi_nxv1i8:83; CHECK:       # %bb.0:84; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma85; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t86; CHECK-NEXT:    ret87  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)88  ret <vscale x 1 x i8> %v89}90 91define <vscale x 1 x i8> @vsadd_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {92; CHECK-LABEL: vsadd_vi_nxv1i8_unmasked:93; CHECK:       # %bb.0:94; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma95; CHECK-NEXT:    vsadd.vi v8, v8, -196; CHECK-NEXT:    ret97  %v = call <vscale x 1 x i8> @llvm.vp.sadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)98  ret <vscale x 1 x i8> %v99}100 101define <vscale x 2 x i8> @vsadd_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {102; CHECK-LABEL: vsadd_vv_nxv2i8:103; CHECK:       # %bb.0:104; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma105; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t106; CHECK-NEXT:    ret107  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)108  ret <vscale x 2 x i8> %v109}110 111define <vscale x 2 x i8> @vsadd_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {112; CHECK-LABEL: vsadd_vv_nxv2i8_unmasked:113; CHECK:       # %bb.0:114; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma115; CHECK-NEXT:    vsadd.vv v8, v8, v9116; CHECK-NEXT:    ret117  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)118  ret <vscale x 2 x i8> %v119}120 121define <vscale x 2 x i8> @vsadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {122; CHECK-LABEL: vsadd_vx_nxv2i8:123; CHECK:       # %bb.0:124; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma125; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t126; CHECK-NEXT:    ret127  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0128  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer129  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)130  ret <vscale x 2 x i8> %v131}132 133define <vscale x 2 x i8> @vsadd_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {134; CHECK-LABEL: vsadd_vx_nxv2i8_unmasked:135; CHECK:       # %bb.0:136; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma137; CHECK-NEXT:    vsadd.vx v8, v8, a0138; CHECK-NEXT:    ret139  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0140  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer141  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)142  ret <vscale x 2 x i8> %v143}144 145define <vscale x 2 x i8> @vsadd_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {146; CHECK-LABEL: vsadd_vi_nxv2i8:147; CHECK:       # %bb.0:148; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma149; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t150; CHECK-NEXT:    ret151  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)152  ret <vscale x 2 x i8> %v153}154 155define <vscale x 2 x i8> @vsadd_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {156; CHECK-LABEL: vsadd_vi_nxv2i8_unmasked:157; CHECK:       # %bb.0:158; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma159; CHECK-NEXT:    vsadd.vi v8, v8, -1160; CHECK-NEXT:    ret161  %v = call <vscale x 2 x i8> @llvm.vp.sadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)162  ret <vscale x 2 x i8> %v163}164 165define <vscale x 3 x i8> @vsadd_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {166; CHECK-LABEL: vsadd_vv_nxv3i8:167; CHECK:       # %bb.0:168; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma169; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t170; CHECK-NEXT:    ret171  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)172  ret <vscale x 3 x i8> %v173}174 175define <vscale x 3 x i8> @vsadd_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {176; CHECK-LABEL: vsadd_vv_nxv3i8_unmasked:177; CHECK:       # %bb.0:178; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma179; CHECK-NEXT:    vsadd.vv v8, v8, v9180; CHECK-NEXT:    ret181  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)182  ret <vscale x 3 x i8> %v183}184 185define <vscale x 3 x i8> @vsadd_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {186; CHECK-LABEL: vsadd_vx_nxv3i8:187; CHECK:       # %bb.0:188; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma189; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t190; CHECK-NEXT:    ret191  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0192  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer193  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)194  ret <vscale x 3 x i8> %v195}196 197define <vscale x 3 x i8> @vsadd_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {198; CHECK-LABEL: vsadd_vx_nxv3i8_unmasked:199; CHECK:       # %bb.0:200; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma201; CHECK-NEXT:    vsadd.vx v8, v8, a0202; CHECK-NEXT:    ret203  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0204  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer205  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)206  ret <vscale x 3 x i8> %v207}208 209define <vscale x 3 x i8> @vsadd_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {210; CHECK-LABEL: vsadd_vi_nxv3i8:211; CHECK:       # %bb.0:212; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma213; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t214; CHECK-NEXT:    ret215  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)216  ret <vscale x 3 x i8> %v217}218 219define <vscale x 3 x i8> @vsadd_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {220; CHECK-LABEL: vsadd_vi_nxv3i8_unmasked:221; CHECK:       # %bb.0:222; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma223; CHECK-NEXT:    vsadd.vi v8, v8, -1224; CHECK-NEXT:    ret225  %v = call <vscale x 3 x i8> @llvm.vp.sadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)226  ret <vscale x 3 x i8> %v227}228 229define <vscale x 4 x i8> @vsadd_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {230; CHECK-LABEL: vsadd_vv_nxv4i8:231; CHECK:       # %bb.0:232; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma233; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t234; CHECK-NEXT:    ret235  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)236  ret <vscale x 4 x i8> %v237}238 239define <vscale x 4 x i8> @vsadd_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {240; CHECK-LABEL: vsadd_vv_nxv4i8_unmasked:241; CHECK:       # %bb.0:242; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma243; CHECK-NEXT:    vsadd.vv v8, v8, v9244; CHECK-NEXT:    ret245  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)246  ret <vscale x 4 x i8> %v247}248 249define <vscale x 4 x i8> @vsadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {250; CHECK-LABEL: vsadd_vx_nxv4i8:251; CHECK:       # %bb.0:252; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma253; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t254; CHECK-NEXT:    ret255  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0256  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer257  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)258  ret <vscale x 4 x i8> %v259}260 261define <vscale x 4 x i8> @vsadd_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {262; CHECK-LABEL: vsadd_vx_nxv4i8_unmasked:263; CHECK:       # %bb.0:264; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma265; CHECK-NEXT:    vsadd.vx v8, v8, a0266; CHECK-NEXT:    ret267  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0268  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer269  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)270  ret <vscale x 4 x i8> %v271}272 273define <vscale x 4 x i8> @vsadd_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {274; CHECK-LABEL: vsadd_vi_nxv4i8:275; CHECK:       # %bb.0:276; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma277; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t278; CHECK-NEXT:    ret279  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)280  ret <vscale x 4 x i8> %v281}282 283define <vscale x 4 x i8> @vsadd_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {284; CHECK-LABEL: vsadd_vi_nxv4i8_unmasked:285; CHECK:       # %bb.0:286; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma287; CHECK-NEXT:    vsadd.vi v8, v8, -1288; CHECK-NEXT:    ret289  %v = call <vscale x 4 x i8> @llvm.vp.sadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)290  ret <vscale x 4 x i8> %v291}292 293define <vscale x 8 x i8> @vsadd_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {294; CHECK-LABEL: vsadd_vv_nxv8i8:295; CHECK:       # %bb.0:296; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma297; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t298; CHECK-NEXT:    ret299  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)300  ret <vscale x 8 x i8> %v301}302 303define <vscale x 8 x i8> @vsadd_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {304; CHECK-LABEL: vsadd_vv_nxv8i8_unmasked:305; CHECK:       # %bb.0:306; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma307; CHECK-NEXT:    vsadd.vv v8, v8, v9308; CHECK-NEXT:    ret309  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)310  ret <vscale x 8 x i8> %v311}312 313define <vscale x 8 x i8> @vsadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {314; CHECK-LABEL: vsadd_vx_nxv8i8:315; CHECK:       # %bb.0:316; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma317; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t318; CHECK-NEXT:    ret319  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0320  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer321  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)322  ret <vscale x 8 x i8> %v323}324 325define <vscale x 8 x i8> @vsadd_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {326; CHECK-LABEL: vsadd_vx_nxv8i8_unmasked:327; CHECK:       # %bb.0:328; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma329; CHECK-NEXT:    vsadd.vx v8, v8, a0330; CHECK-NEXT:    ret331  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0332  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer333  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)334  ret <vscale x 8 x i8> %v335}336 337define <vscale x 8 x i8> @vsadd_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {338; CHECK-LABEL: vsadd_vi_nxv8i8:339; CHECK:       # %bb.0:340; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma341; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t342; CHECK-NEXT:    ret343  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)344  ret <vscale x 8 x i8> %v345}346 347define <vscale x 8 x i8> @vsadd_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {348; CHECK-LABEL: vsadd_vi_nxv8i8_unmasked:349; CHECK:       # %bb.0:350; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma351; CHECK-NEXT:    vsadd.vi v8, v8, -1352; CHECK-NEXT:    ret353  %v = call <vscale x 8 x i8> @llvm.vp.sadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)354  ret <vscale x 8 x i8> %v355}356 357define <vscale x 16 x i8> @vsadd_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {358; CHECK-LABEL: vsadd_vv_nxv16i8:359; CHECK:       # %bb.0:360; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma361; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t362; CHECK-NEXT:    ret363  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)364  ret <vscale x 16 x i8> %v365}366 367define <vscale x 16 x i8> @vsadd_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {368; CHECK-LABEL: vsadd_vv_nxv16i8_unmasked:369; CHECK:       # %bb.0:370; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma371; CHECK-NEXT:    vsadd.vv v8, v8, v10372; CHECK-NEXT:    ret373  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)374  ret <vscale x 16 x i8> %v375}376 377define <vscale x 16 x i8> @vsadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {378; CHECK-LABEL: vsadd_vx_nxv16i8:379; CHECK:       # %bb.0:380; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma381; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t382; CHECK-NEXT:    ret383  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0384  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer385  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)386  ret <vscale x 16 x i8> %v387}388 389define <vscale x 16 x i8> @vsadd_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {390; CHECK-LABEL: vsadd_vx_nxv16i8_unmasked:391; CHECK:       # %bb.0:392; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma393; CHECK-NEXT:    vsadd.vx v8, v8, a0394; CHECK-NEXT:    ret395  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0396  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer397  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)398  ret <vscale x 16 x i8> %v399}400 401define <vscale x 16 x i8> @vsadd_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {402; CHECK-LABEL: vsadd_vi_nxv16i8:403; CHECK:       # %bb.0:404; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma405; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t406; CHECK-NEXT:    ret407  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)408  ret <vscale x 16 x i8> %v409}410 411define <vscale x 16 x i8> @vsadd_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {412; CHECK-LABEL: vsadd_vi_nxv16i8_unmasked:413; CHECK:       # %bb.0:414; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma415; CHECK-NEXT:    vsadd.vi v8, v8, -1416; CHECK-NEXT:    ret417  %v = call <vscale x 16 x i8> @llvm.vp.sadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)418  ret <vscale x 16 x i8> %v419}420 421define <vscale x 32 x i8> @vsadd_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {422; CHECK-LABEL: vsadd_vv_nxv32i8:423; CHECK:       # %bb.0:424; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma425; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t426; CHECK-NEXT:    ret427  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)428  ret <vscale x 32 x i8> %v429}430 431define <vscale x 32 x i8> @vsadd_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {432; CHECK-LABEL: vsadd_vv_nxv32i8_unmasked:433; CHECK:       # %bb.0:434; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma435; CHECK-NEXT:    vsadd.vv v8, v8, v12436; CHECK-NEXT:    ret437  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)438  ret <vscale x 32 x i8> %v439}440 441define <vscale x 32 x i8> @vsadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {442; CHECK-LABEL: vsadd_vx_nxv32i8:443; CHECK:       # %bb.0:444; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma445; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t446; CHECK-NEXT:    ret447  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0448  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer449  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)450  ret <vscale x 32 x i8> %v451}452 453define <vscale x 32 x i8> @vsadd_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {454; CHECK-LABEL: vsadd_vx_nxv32i8_unmasked:455; CHECK:       # %bb.0:456; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma457; CHECK-NEXT:    vsadd.vx v8, v8, a0458; CHECK-NEXT:    ret459  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0460  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer461  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)462  ret <vscale x 32 x i8> %v463}464 465define <vscale x 32 x i8> @vsadd_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {466; CHECK-LABEL: vsadd_vi_nxv32i8:467; CHECK:       # %bb.0:468; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma469; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t470; CHECK-NEXT:    ret471  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)472  ret <vscale x 32 x i8> %v473}474 475define <vscale x 32 x i8> @vsadd_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {476; CHECK-LABEL: vsadd_vi_nxv32i8_unmasked:477; CHECK:       # %bb.0:478; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma479; CHECK-NEXT:    vsadd.vi v8, v8, -1480; CHECK-NEXT:    ret481  %v = call <vscale x 32 x i8> @llvm.vp.sadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)482  ret <vscale x 32 x i8> %v483}484 485define <vscale x 64 x i8> @vsadd_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {486; CHECK-LABEL: vsadd_vv_nxv64i8:487; CHECK:       # %bb.0:488; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma489; CHECK-NEXT:    vsadd.vv v8, v8, v16, v0.t490; CHECK-NEXT:    ret491  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)492  ret <vscale x 64 x i8> %v493}494 495define <vscale x 64 x i8> @vsadd_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {496; CHECK-LABEL: vsadd_vv_nxv64i8_unmasked:497; CHECK:       # %bb.0:498; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma499; CHECK-NEXT:    vsadd.vv v8, v8, v16500; CHECK-NEXT:    ret501  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)502  ret <vscale x 64 x i8> %v503}504 505define <vscale x 64 x i8> @vsadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {506; CHECK-LABEL: vsadd_vx_nxv64i8:507; CHECK:       # %bb.0:508; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma509; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t510; CHECK-NEXT:    ret511  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0512  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer513  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)514  ret <vscale x 64 x i8> %v515}516 517define <vscale x 64 x i8> @vsadd_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {518; CHECK-LABEL: vsadd_vx_nxv64i8_unmasked:519; CHECK:       # %bb.0:520; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma521; CHECK-NEXT:    vsadd.vx v8, v8, a0522; CHECK-NEXT:    ret523  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0524  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer525  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)526  ret <vscale x 64 x i8> %v527}528 529define <vscale x 64 x i8> @vsadd_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {530; CHECK-LABEL: vsadd_vi_nxv64i8:531; CHECK:       # %bb.0:532; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma533; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t534; CHECK-NEXT:    ret535  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)536  ret <vscale x 64 x i8> %v537}538 539define <vscale x 64 x i8> @vsadd_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {540; CHECK-LABEL: vsadd_vi_nxv64i8_unmasked:541; CHECK:       # %bb.0:542; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma543; CHECK-NEXT:    vsadd.vi v8, v8, -1544; CHECK-NEXT:    ret545  %v = call <vscale x 64 x i8> @llvm.vp.sadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)546  ret <vscale x 64 x i8> %v547}548 549; Test that split-legalization works when the mask itself needs splitting.550 551define <vscale x 128 x i8> @vsadd_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {552; CHECK-LABEL: vsadd_vi_nxv128i8:553; CHECK:       # %bb.0:554; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma555; CHECK-NEXT:    vmv1r.v v24, v0556; CHECK-NEXT:    vlm.v v0, (a0)557; CHECK-NEXT:    csrr a0, vlenb558; CHECK-NEXT:    slli a0, a0, 3559; CHECK-NEXT:    sub a2, a1, a0560; CHECK-NEXT:    sltu a3, a1, a2561; CHECK-NEXT:    addi a3, a3, -1562; CHECK-NEXT:    and a2, a3, a2563; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma564; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t565; CHECK-NEXT:    bltu a1, a0, .LBB50_2566; CHECK-NEXT:  # %bb.1:567; CHECK-NEXT:    mv a1, a0568; CHECK-NEXT:  .LBB50_2:569; CHECK-NEXT:    vmv1r.v v0, v24570; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma571; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t572; CHECK-NEXT:    ret573  %v = call <vscale x 128 x i8> @llvm.vp.sadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)574  ret <vscale x 128 x i8> %v575}576 577define <vscale x 128 x i8> @vsadd_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {578; CHECK-LABEL: vsadd_vi_nxv128i8_unmasked:579; CHECK:       # %bb.0:580; CHECK-NEXT:    csrr a1, vlenb581; CHECK-NEXT:    slli a1, a1, 3582; CHECK-NEXT:    sub a2, a0, a1583; CHECK-NEXT:    sltu a3, a0, a2584; CHECK-NEXT:    addi a3, a3, -1585; CHECK-NEXT:    and a2, a3, a2586; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma587; CHECK-NEXT:    vsadd.vi v16, v16, -1588; CHECK-NEXT:    bltu a0, a1, .LBB51_2589; CHECK-NEXT:  # %bb.1:590; CHECK-NEXT:    mv a0, a1591; CHECK-NEXT:  .LBB51_2:592; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma593; CHECK-NEXT:    vsadd.vi v8, v8, -1594; CHECK-NEXT:    ret595  %v = call <vscale x 128 x i8> @llvm.vp.sadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)596  ret <vscale x 128 x i8> %v597}598 599define <vscale x 1 x i16> @vsadd_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {600; CHECK-LABEL: vsadd_vv_nxv1i16:601; CHECK:       # %bb.0:602; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma603; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t604; CHECK-NEXT:    ret605  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)606  ret <vscale x 1 x i16> %v607}608 609define <vscale x 1 x i16> @vsadd_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {610; CHECK-LABEL: vsadd_vv_nxv1i16_unmasked:611; CHECK:       # %bb.0:612; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma613; CHECK-NEXT:    vsadd.vv v8, v8, v9614; CHECK-NEXT:    ret615  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)616  ret <vscale x 1 x i16> %v617}618 619define <vscale x 1 x i16> @vsadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {620; CHECK-LABEL: vsadd_vx_nxv1i16:621; CHECK:       # %bb.0:622; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma623; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t624; CHECK-NEXT:    ret625  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0626  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer627  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)628  ret <vscale x 1 x i16> %v629}630 631define <vscale x 1 x i16> @vsadd_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {632; CHECK-LABEL: vsadd_vx_nxv1i16_unmasked:633; CHECK:       # %bb.0:634; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma635; CHECK-NEXT:    vsadd.vx v8, v8, a0636; CHECK-NEXT:    ret637  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0638  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer639  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)640  ret <vscale x 1 x i16> %v641}642 643define <vscale x 1 x i16> @vsadd_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {644; CHECK-LABEL: vsadd_vi_nxv1i16:645; CHECK:       # %bb.0:646; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma647; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t648; CHECK-NEXT:    ret649  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)650  ret <vscale x 1 x i16> %v651}652 653define <vscale x 1 x i16> @vsadd_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {654; CHECK-LABEL: vsadd_vi_nxv1i16_unmasked:655; CHECK:       # %bb.0:656; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma657; CHECK-NEXT:    vsadd.vi v8, v8, -1658; CHECK-NEXT:    ret659  %v = call <vscale x 1 x i16> @llvm.vp.sadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)660  ret <vscale x 1 x i16> %v661}662 663define <vscale x 2 x i16> @vsadd_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {664; CHECK-LABEL: vsadd_vv_nxv2i16:665; CHECK:       # %bb.0:666; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma667; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t668; CHECK-NEXT:    ret669  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)670  ret <vscale x 2 x i16> %v671}672 673define <vscale x 2 x i16> @vsadd_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {674; CHECK-LABEL: vsadd_vv_nxv2i16_unmasked:675; CHECK:       # %bb.0:676; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma677; CHECK-NEXT:    vsadd.vv v8, v8, v9678; CHECK-NEXT:    ret679  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)680  ret <vscale x 2 x i16> %v681}682 683define <vscale x 2 x i16> @vsadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {684; CHECK-LABEL: vsadd_vx_nxv2i16:685; CHECK:       # %bb.0:686; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma687; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t688; CHECK-NEXT:    ret689  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0690  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer691  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)692  ret <vscale x 2 x i16> %v693}694 695define <vscale x 2 x i16> @vsadd_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {696; CHECK-LABEL: vsadd_vx_nxv2i16_unmasked:697; CHECK:       # %bb.0:698; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma699; CHECK-NEXT:    vsadd.vx v8, v8, a0700; CHECK-NEXT:    ret701  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0702  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer703  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)704  ret <vscale x 2 x i16> %v705}706 707define <vscale x 2 x i16> @vsadd_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {708; CHECK-LABEL: vsadd_vi_nxv2i16:709; CHECK:       # %bb.0:710; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma711; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t712; CHECK-NEXT:    ret713  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)714  ret <vscale x 2 x i16> %v715}716 717define <vscale x 2 x i16> @vsadd_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {718; CHECK-LABEL: vsadd_vi_nxv2i16_unmasked:719; CHECK:       # %bb.0:720; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma721; CHECK-NEXT:    vsadd.vi v8, v8, -1722; CHECK-NEXT:    ret723  %v = call <vscale x 2 x i16> @llvm.vp.sadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)724  ret <vscale x 2 x i16> %v725}726 727define <vscale x 4 x i16> @vsadd_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {728; CHECK-LABEL: vsadd_vv_nxv4i16:729; CHECK:       # %bb.0:730; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma731; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t732; CHECK-NEXT:    ret733  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)734  ret <vscale x 4 x i16> %v735}736 737define <vscale x 4 x i16> @vsadd_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {738; CHECK-LABEL: vsadd_vv_nxv4i16_unmasked:739; CHECK:       # %bb.0:740; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma741; CHECK-NEXT:    vsadd.vv v8, v8, v9742; CHECK-NEXT:    ret743  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)744  ret <vscale x 4 x i16> %v745}746 747define <vscale x 4 x i16> @vsadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {748; CHECK-LABEL: vsadd_vx_nxv4i16:749; CHECK:       # %bb.0:750; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma751; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t752; CHECK-NEXT:    ret753  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0754  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer755  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)756  ret <vscale x 4 x i16> %v757}758 759define <vscale x 4 x i16> @vsadd_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {760; CHECK-LABEL: vsadd_vx_nxv4i16_unmasked:761; CHECK:       # %bb.0:762; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma763; CHECK-NEXT:    vsadd.vx v8, v8, a0764; CHECK-NEXT:    ret765  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0766  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer767  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)768  ret <vscale x 4 x i16> %v769}770 771define <vscale x 4 x i16> @vsadd_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {772; CHECK-LABEL: vsadd_vi_nxv4i16:773; CHECK:       # %bb.0:774; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma775; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t776; CHECK-NEXT:    ret777  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)778  ret <vscale x 4 x i16> %v779}780 781define <vscale x 4 x i16> @vsadd_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {782; CHECK-LABEL: vsadd_vi_nxv4i16_unmasked:783; CHECK:       # %bb.0:784; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma785; CHECK-NEXT:    vsadd.vi v8, v8, -1786; CHECK-NEXT:    ret787  %v = call <vscale x 4 x i16> @llvm.vp.sadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)788  ret <vscale x 4 x i16> %v789}790 791define <vscale x 8 x i16> @vsadd_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {792; CHECK-LABEL: vsadd_vv_nxv8i16:793; CHECK:       # %bb.0:794; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma795; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t796; CHECK-NEXT:    ret797  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)798  ret <vscale x 8 x i16> %v799}800 801define <vscale x 8 x i16> @vsadd_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {802; CHECK-LABEL: vsadd_vv_nxv8i16_unmasked:803; CHECK:       # %bb.0:804; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma805; CHECK-NEXT:    vsadd.vv v8, v8, v10806; CHECK-NEXT:    ret807  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)808  ret <vscale x 8 x i16> %v809}810 811define <vscale x 8 x i16> @vsadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {812; CHECK-LABEL: vsadd_vx_nxv8i16:813; CHECK:       # %bb.0:814; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma815; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t816; CHECK-NEXT:    ret817  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0818  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer819  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)820  ret <vscale x 8 x i16> %v821}822 823define <vscale x 8 x i16> @vsadd_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {824; CHECK-LABEL: vsadd_vx_nxv8i16_unmasked:825; CHECK:       # %bb.0:826; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma827; CHECK-NEXT:    vsadd.vx v8, v8, a0828; CHECK-NEXT:    ret829  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0830  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer831  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)832  ret <vscale x 8 x i16> %v833}834 835define <vscale x 8 x i16> @vsadd_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {836; CHECK-LABEL: vsadd_vi_nxv8i16:837; CHECK:       # %bb.0:838; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma839; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t840; CHECK-NEXT:    ret841  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)842  ret <vscale x 8 x i16> %v843}844 845define <vscale x 8 x i16> @vsadd_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {846; CHECK-LABEL: vsadd_vi_nxv8i16_unmasked:847; CHECK:       # %bb.0:848; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma849; CHECK-NEXT:    vsadd.vi v8, v8, -1850; CHECK-NEXT:    ret851  %v = call <vscale x 8 x i16> @llvm.vp.sadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)852  ret <vscale x 8 x i16> %v853}854 855define <vscale x 16 x i16> @vsadd_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {856; CHECK-LABEL: vsadd_vv_nxv16i16:857; CHECK:       # %bb.0:858; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma859; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t860; CHECK-NEXT:    ret861  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)862  ret <vscale x 16 x i16> %v863}864 865define <vscale x 16 x i16> @vsadd_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {866; CHECK-LABEL: vsadd_vv_nxv16i16_unmasked:867; CHECK:       # %bb.0:868; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma869; CHECK-NEXT:    vsadd.vv v8, v8, v12870; CHECK-NEXT:    ret871  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)872  ret <vscale x 16 x i16> %v873}874 875define <vscale x 16 x i16> @vsadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {876; CHECK-LABEL: vsadd_vx_nxv16i16:877; CHECK:       # %bb.0:878; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma879; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t880; CHECK-NEXT:    ret881  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0882  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer883  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)884  ret <vscale x 16 x i16> %v885}886 887define <vscale x 16 x i16> @vsadd_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {888; CHECK-LABEL: vsadd_vx_nxv16i16_unmasked:889; CHECK:       # %bb.0:890; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma891; CHECK-NEXT:    vsadd.vx v8, v8, a0892; CHECK-NEXT:    ret893  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0894  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer895  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)896  ret <vscale x 16 x i16> %v897}898 899define <vscale x 16 x i16> @vsadd_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {900; CHECK-LABEL: vsadd_vi_nxv16i16:901; CHECK:       # %bb.0:902; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma903; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t904; CHECK-NEXT:    ret905  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)906  ret <vscale x 16 x i16> %v907}908 909define <vscale x 16 x i16> @vsadd_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {910; CHECK-LABEL: vsadd_vi_nxv16i16_unmasked:911; CHECK:       # %bb.0:912; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma913; CHECK-NEXT:    vsadd.vi v8, v8, -1914; CHECK-NEXT:    ret915  %v = call <vscale x 16 x i16> @llvm.vp.sadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)916  ret <vscale x 16 x i16> %v917}918 919define <vscale x 32 x i16> @vsadd_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {920; CHECK-LABEL: vsadd_vv_nxv32i16:921; CHECK:       # %bb.0:922; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma923; CHECK-NEXT:    vsadd.vv v8, v8, v16, v0.t924; CHECK-NEXT:    ret925  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)926  ret <vscale x 32 x i16> %v927}928 929define <vscale x 32 x i16> @vsadd_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {930; CHECK-LABEL: vsadd_vv_nxv32i16_unmasked:931; CHECK:       # %bb.0:932; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma933; CHECK-NEXT:    vsadd.vv v8, v8, v16934; CHECK-NEXT:    ret935  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)936  ret <vscale x 32 x i16> %v937}938 939define <vscale x 32 x i16> @vsadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {940; CHECK-LABEL: vsadd_vx_nxv32i16:941; CHECK:       # %bb.0:942; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma943; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t944; CHECK-NEXT:    ret945  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0946  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer947  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)948  ret <vscale x 32 x i16> %v949}950 951define <vscale x 32 x i16> @vsadd_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {952; CHECK-LABEL: vsadd_vx_nxv32i16_unmasked:953; CHECK:       # %bb.0:954; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma955; CHECK-NEXT:    vsadd.vx v8, v8, a0956; CHECK-NEXT:    ret957  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0958  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer959  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)960  ret <vscale x 32 x i16> %v961}962 963define <vscale x 32 x i16> @vsadd_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {964; CHECK-LABEL: vsadd_vi_nxv32i16:965; CHECK:       # %bb.0:966; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma967; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t968; CHECK-NEXT:    ret969  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)970  ret <vscale x 32 x i16> %v971}972 973define <vscale x 32 x i16> @vsadd_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {974; CHECK-LABEL: vsadd_vi_nxv32i16_unmasked:975; CHECK:       # %bb.0:976; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma977; CHECK-NEXT:    vsadd.vi v8, v8, -1978; CHECK-NEXT:    ret979  %v = call <vscale x 32 x i16> @llvm.vp.sadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)980  ret <vscale x 32 x i16> %v981}982 983define <vscale x 1 x i32> @vsadd_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {984; CHECK-LABEL: vsadd_vv_nxv1i32:985; CHECK:       # %bb.0:986; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma987; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t988; CHECK-NEXT:    ret989  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)990  ret <vscale x 1 x i32> %v991}992 993define <vscale x 1 x i32> @vsadd_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {994; CHECK-LABEL: vsadd_vv_nxv1i32_unmasked:995; CHECK:       # %bb.0:996; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma997; CHECK-NEXT:    vsadd.vv v8, v8, v9998; CHECK-NEXT:    ret999  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1000  ret <vscale x 1 x i32> %v1001}1002 1003define <vscale x 1 x i32> @vsadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1004; CHECK-LABEL: vsadd_vx_nxv1i32:1005; CHECK:       # %bb.0:1006; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1007; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t1008; CHECK-NEXT:    ret1009  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01010  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1011  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1012  ret <vscale x 1 x i32> %v1013}1014 1015define <vscale x 1 x i32> @vsadd_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1016; CHECK-LABEL: vsadd_vx_nxv1i32_unmasked:1017; CHECK:       # %bb.0:1018; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1019; CHECK-NEXT:    vsadd.vx v8, v8, a01020; CHECK-NEXT:    ret1021  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01022  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1023  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1024  ret <vscale x 1 x i32> %v1025}1026 1027define <vscale x 1 x i32> @vsadd_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1028; CHECK-LABEL: vsadd_vi_nxv1i32:1029; CHECK:       # %bb.0:1030; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1031; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1032; CHECK-NEXT:    ret1033  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1034  ret <vscale x 1 x i32> %v1035}1036 1037define <vscale x 1 x i32> @vsadd_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1038; CHECK-LABEL: vsadd_vi_nxv1i32_unmasked:1039; CHECK:       # %bb.0:1040; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1041; CHECK-NEXT:    vsadd.vi v8, v8, -11042; CHECK-NEXT:    ret1043  %v = call <vscale x 1 x i32> @llvm.vp.sadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1044  ret <vscale x 1 x i32> %v1045}1046 1047define <vscale x 2 x i32> @vsadd_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1048; CHECK-LABEL: vsadd_vv_nxv2i32:1049; CHECK:       # %bb.0:1050; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1051; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t1052; CHECK-NEXT:    ret1053  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1054  ret <vscale x 2 x i32> %v1055}1056 1057define <vscale x 2 x i32> @vsadd_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1058; CHECK-LABEL: vsadd_vv_nxv2i32_unmasked:1059; CHECK:       # %bb.0:1060; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1061; CHECK-NEXT:    vsadd.vv v8, v8, v91062; CHECK-NEXT:    ret1063  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1064  ret <vscale x 2 x i32> %v1065}1066 1067define <vscale x 2 x i32> @vsadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1068; CHECK-LABEL: vsadd_vx_nxv2i32:1069; CHECK:       # %bb.0:1070; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1071; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t1072; CHECK-NEXT:    ret1073  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01074  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1075  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1076  ret <vscale x 2 x i32> %v1077}1078 1079define <vscale x 2 x i32> @vsadd_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1080; CHECK-LABEL: vsadd_vx_nxv2i32_unmasked:1081; CHECK:       # %bb.0:1082; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1083; CHECK-NEXT:    vsadd.vx v8, v8, a01084; CHECK-NEXT:    ret1085  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01086  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1087  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1088  ret <vscale x 2 x i32> %v1089}1090 1091define <vscale x 2 x i32> @vsadd_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1092; CHECK-LABEL: vsadd_vi_nxv2i32:1093; CHECK:       # %bb.0:1094; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1095; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1096; CHECK-NEXT:    ret1097  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1098  ret <vscale x 2 x i32> %v1099}1100 1101define <vscale x 2 x i32> @vsadd_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1102; CHECK-LABEL: vsadd_vi_nxv2i32_unmasked:1103; CHECK:       # %bb.0:1104; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1105; CHECK-NEXT:    vsadd.vi v8, v8, -11106; CHECK-NEXT:    ret1107  %v = call <vscale x 2 x i32> @llvm.vp.sadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1108  ret <vscale x 2 x i32> %v1109}1110 1111define <vscale x 4 x i32> @vsadd_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1112; CHECK-LABEL: vsadd_vv_nxv4i32:1113; CHECK:       # %bb.0:1114; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1115; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t1116; CHECK-NEXT:    ret1117  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1118  ret <vscale x 4 x i32> %v1119}1120 1121define <vscale x 4 x i32> @vsadd_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1122; CHECK-LABEL: vsadd_vv_nxv4i32_unmasked:1123; CHECK:       # %bb.0:1124; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1125; CHECK-NEXT:    vsadd.vv v8, v8, v101126; CHECK-NEXT:    ret1127  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1128  ret <vscale x 4 x i32> %v1129}1130 1131define <vscale x 4 x i32> @vsadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1132; CHECK-LABEL: vsadd_vx_nxv4i32:1133; CHECK:       # %bb.0:1134; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1135; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t1136; CHECK-NEXT:    ret1137  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01138  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1139  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1140  ret <vscale x 4 x i32> %v1141}1142 1143define <vscale x 4 x i32> @vsadd_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1144; CHECK-LABEL: vsadd_vx_nxv4i32_unmasked:1145; CHECK:       # %bb.0:1146; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1147; CHECK-NEXT:    vsadd.vx v8, v8, a01148; CHECK-NEXT:    ret1149  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01150  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1151  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1152  ret <vscale x 4 x i32> %v1153}1154 1155define <vscale x 4 x i32> @vsadd_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1156; CHECK-LABEL: vsadd_vi_nxv4i32:1157; CHECK:       # %bb.0:1158; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1159; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1160; CHECK-NEXT:    ret1161  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1162  ret <vscale x 4 x i32> %v1163}1164 1165define <vscale x 4 x i32> @vsadd_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1166; CHECK-LABEL: vsadd_vi_nxv4i32_unmasked:1167; CHECK:       # %bb.0:1168; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1169; CHECK-NEXT:    vsadd.vi v8, v8, -11170; CHECK-NEXT:    ret1171  %v = call <vscale x 4 x i32> @llvm.vp.sadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1172  ret <vscale x 4 x i32> %v1173}1174 1175define <vscale x 8 x i32> @vsadd_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1176; CHECK-LABEL: vsadd_vv_nxv8i32:1177; CHECK:       # %bb.0:1178; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1179; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t1180; CHECK-NEXT:    ret1181  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1182  ret <vscale x 8 x i32> %v1183}1184 1185define <vscale x 8 x i32> @vsadd_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1186; CHECK-LABEL: vsadd_vv_nxv8i32_unmasked:1187; CHECK:       # %bb.0:1188; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1189; CHECK-NEXT:    vsadd.vv v8, v8, v121190; CHECK-NEXT:    ret1191  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1192  ret <vscale x 8 x i32> %v1193}1194 1195define <vscale x 8 x i32> @vsadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1196; CHECK-LABEL: vsadd_vx_nxv8i32:1197; CHECK:       # %bb.0:1198; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1199; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t1200; CHECK-NEXT:    ret1201  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01202  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1203  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1204  ret <vscale x 8 x i32> %v1205}1206 1207define <vscale x 8 x i32> @vsadd_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1208; CHECK-LABEL: vsadd_vx_nxv8i32_unmasked:1209; CHECK:       # %bb.0:1210; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1211; CHECK-NEXT:    vsadd.vx v8, v8, a01212; CHECK-NEXT:    ret1213  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01214  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1215  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1216  ret <vscale x 8 x i32> %v1217}1218 1219define <vscale x 8 x i32> @vsadd_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1220; CHECK-LABEL: vsadd_vi_nxv8i32:1221; CHECK:       # %bb.0:1222; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1223; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1224; CHECK-NEXT:    ret1225  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1226  ret <vscale x 8 x i32> %v1227}1228 1229define <vscale x 8 x i32> @vsadd_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1230; CHECK-LABEL: vsadd_vi_nxv8i32_unmasked:1231; CHECK:       # %bb.0:1232; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1233; CHECK-NEXT:    vsadd.vi v8, v8, -11234; CHECK-NEXT:    ret1235  %v = call <vscale x 8 x i32> @llvm.vp.sadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1236  ret <vscale x 8 x i32> %v1237}1238 1239define <vscale x 16 x i32> @vsadd_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1240; CHECK-LABEL: vsadd_vv_nxv16i32:1241; CHECK:       # %bb.0:1242; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1243; CHECK-NEXT:    vsadd.vv v8, v8, v16, v0.t1244; CHECK-NEXT:    ret1245  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1246  ret <vscale x 16 x i32> %v1247}1248 1249define <vscale x 16 x i32> @vsadd_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1250; CHECK-LABEL: vsadd_vv_nxv16i32_unmasked:1251; CHECK:       # %bb.0:1252; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1253; CHECK-NEXT:    vsadd.vv v8, v8, v161254; CHECK-NEXT:    ret1255  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1256  ret <vscale x 16 x i32> %v1257}1258 1259define <vscale x 16 x i32> @vsadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1260; CHECK-LABEL: vsadd_vx_nxv16i32:1261; CHECK:       # %bb.0:1262; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1263; CHECK-NEXT:    vsadd.vx v8, v8, a0, v0.t1264; CHECK-NEXT:    ret1265  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01266  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1267  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1268  ret <vscale x 16 x i32> %v1269}1270 1271define <vscale x 16 x i32> @vsadd_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1272; CHECK-LABEL: vsadd_vx_nxv16i32_unmasked:1273; CHECK:       # %bb.0:1274; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1275; CHECK-NEXT:    vsadd.vx v8, v8, a01276; CHECK-NEXT:    ret1277  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01278  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1279  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1280  ret <vscale x 16 x i32> %v1281}1282 1283define <vscale x 16 x i32> @vsadd_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1284; CHECK-LABEL: vsadd_vi_nxv16i32:1285; CHECK:       # %bb.0:1286; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1287; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1288; CHECK-NEXT:    ret1289  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1290  ret <vscale x 16 x i32> %v1291}1292 1293define <vscale x 16 x i32> @vsadd_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1294; CHECK-LABEL: vsadd_vi_nxv16i32_unmasked:1295; CHECK:       # %bb.0:1296; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1297; CHECK-NEXT:    vsadd.vi v8, v8, -11298; CHECK-NEXT:    ret1299  %v = call <vscale x 16 x i32> @llvm.vp.sadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1300  ret <vscale x 16 x i32> %v1301}1302 1303; Test that split-legalization works then the mask needs manual splitting.1304 1305define <vscale x 32 x i32> @vsadd_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1306; CHECK-LABEL: vsadd_vi_nxv32i32:1307; CHECK:       # %bb.0:1308; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma1309; CHECK-NEXT:    vmv1r.v v24, v01310; CHECK-NEXT:    csrr a1, vlenb1311; CHECK-NEXT:    srli a2, a1, 21312; CHECK-NEXT:    slli a1, a1, 11313; CHECK-NEXT:    vslidedown.vx v0, v0, a21314; CHECK-NEXT:    sub a2, a0, a11315; CHECK-NEXT:    sltu a3, a0, a21316; CHECK-NEXT:    addi a3, a3, -11317; CHECK-NEXT:    and a2, a3, a21318; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1319; CHECK-NEXT:    vsadd.vi v16, v16, -1, v0.t1320; CHECK-NEXT:    bltu a0, a1, .LBB118_21321; CHECK-NEXT:  # %bb.1:1322; CHECK-NEXT:    mv a0, a11323; CHECK-NEXT:  .LBB118_2:1324; CHECK-NEXT:    vmv1r.v v0, v241325; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1326; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1327; CHECK-NEXT:    ret1328  %v = call <vscale x 32 x i32> @llvm.vp.sadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)1329  ret <vscale x 32 x i32> %v1330}1331 1332define <vscale x 32 x i32> @vsadd_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {1333; CHECK-LABEL: vsadd_vi_nxv32i32_unmasked:1334; CHECK:       # %bb.0:1335; CHECK-NEXT:    csrr a1, vlenb1336; CHECK-NEXT:    slli a1, a1, 11337; CHECK-NEXT:    sub a2, a0, a11338; CHECK-NEXT:    sltu a3, a0, a21339; CHECK-NEXT:    addi a3, a3, -11340; CHECK-NEXT:    and a2, a3, a21341; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1342; CHECK-NEXT:    vsadd.vi v16, v16, -11343; CHECK-NEXT:    bltu a0, a1, .LBB119_21344; CHECK-NEXT:  # %bb.1:1345; CHECK-NEXT:    mv a0, a11346; CHECK-NEXT:  .LBB119_2:1347; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1348; CHECK-NEXT:    vsadd.vi v8, v8, -11349; CHECK-NEXT:    ret1350  %v = call <vscale x 32 x i32> @llvm.vp.sadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1351  ret <vscale x 32 x i32> %v1352}1353 1354define <vscale x 1 x i64> @vsadd_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1355; CHECK-LABEL: vsadd_vv_nxv1i64:1356; CHECK:       # %bb.0:1357; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1358; CHECK-NEXT:    vsadd.vv v8, v8, v9, v0.t1359; CHECK-NEXT:    ret1360  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1361  ret <vscale x 1 x i64> %v1362}1363 1364define <vscale x 1 x i64> @vsadd_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1365; CHECK-LABEL: vsadd_vv_nxv1i64_unmasked:1366; CHECK:       # %bb.0:1367; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1368; CHECK-NEXT:    vsadd.vv v8, v8, v91369; CHECK-NEXT:    ret1370  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1371  ret <vscale x 1 x i64> %v1372}1373 1374define <vscale x 1 x i64> @vsadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1375; RV32-LABEL: vsadd_vx_nxv1i64:1376; RV32:       # %bb.0:1377; RV32-NEXT:    addi sp, sp, -161378; RV32-NEXT:    .cfi_def_cfa_offset 161379; RV32-NEXT:    sw a0, 8(sp)1380; RV32-NEXT:    sw a1, 12(sp)1381; RV32-NEXT:    addi a0, sp, 81382; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1383; RV32-NEXT:    vlse64.v v9, (a0), zero1384; RV32-NEXT:    vsadd.vv v8, v8, v9, v0.t1385; RV32-NEXT:    addi sp, sp, 161386; RV32-NEXT:    .cfi_def_cfa_offset 01387; RV32-NEXT:    ret1388;1389; RV64-LABEL: vsadd_vx_nxv1i64:1390; RV64:       # %bb.0:1391; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1392; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t1393; RV64-NEXT:    ret1394  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01395  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1396  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1397  ret <vscale x 1 x i64> %v1398}1399 1400define <vscale x 1 x i64> @vsadd_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1401; RV32-LABEL: vsadd_vx_nxv1i64_unmasked:1402; RV32:       # %bb.0:1403; RV32-NEXT:    addi sp, sp, -161404; RV32-NEXT:    .cfi_def_cfa_offset 161405; RV32-NEXT:    sw a0, 8(sp)1406; RV32-NEXT:    sw a1, 12(sp)1407; RV32-NEXT:    addi a0, sp, 81408; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1409; RV32-NEXT:    vlse64.v v9, (a0), zero1410; RV32-NEXT:    vsadd.vv v8, v8, v91411; RV32-NEXT:    addi sp, sp, 161412; RV32-NEXT:    .cfi_def_cfa_offset 01413; RV32-NEXT:    ret1414;1415; RV64-LABEL: vsadd_vx_nxv1i64_unmasked:1416; RV64:       # %bb.0:1417; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1418; RV64-NEXT:    vsadd.vx v8, v8, a01419; RV64-NEXT:    ret1420  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01421  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1422  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1423  ret <vscale x 1 x i64> %v1424}1425 1426define <vscale x 1 x i64> @vsadd_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1427; CHECK-LABEL: vsadd_vi_nxv1i64:1428; CHECK:       # %bb.0:1429; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1430; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1431; CHECK-NEXT:    ret1432  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1433  ret <vscale x 1 x i64> %v1434}1435 1436define <vscale x 1 x i64> @vsadd_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1437; CHECK-LABEL: vsadd_vi_nxv1i64_unmasked:1438; CHECK:       # %bb.0:1439; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1440; CHECK-NEXT:    vsadd.vi v8, v8, -11441; CHECK-NEXT:    ret1442  %v = call <vscale x 1 x i64> @llvm.vp.sadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1443  ret <vscale x 1 x i64> %v1444}1445 1446define <vscale x 2 x i64> @vsadd_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1447; CHECK-LABEL: vsadd_vv_nxv2i64:1448; CHECK:       # %bb.0:1449; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1450; CHECK-NEXT:    vsadd.vv v8, v8, v10, v0.t1451; CHECK-NEXT:    ret1452  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1453  ret <vscale x 2 x i64> %v1454}1455 1456define <vscale x 2 x i64> @vsadd_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1457; CHECK-LABEL: vsadd_vv_nxv2i64_unmasked:1458; CHECK:       # %bb.0:1459; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1460; CHECK-NEXT:    vsadd.vv v8, v8, v101461; CHECK-NEXT:    ret1462  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1463  ret <vscale x 2 x i64> %v1464}1465 1466define <vscale x 2 x i64> @vsadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1467; RV32-LABEL: vsadd_vx_nxv2i64:1468; RV32:       # %bb.0:1469; RV32-NEXT:    addi sp, sp, -161470; RV32-NEXT:    .cfi_def_cfa_offset 161471; RV32-NEXT:    sw a0, 8(sp)1472; RV32-NEXT:    sw a1, 12(sp)1473; RV32-NEXT:    addi a0, sp, 81474; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1475; RV32-NEXT:    vlse64.v v10, (a0), zero1476; RV32-NEXT:    vsadd.vv v8, v8, v10, v0.t1477; RV32-NEXT:    addi sp, sp, 161478; RV32-NEXT:    .cfi_def_cfa_offset 01479; RV32-NEXT:    ret1480;1481; RV64-LABEL: vsadd_vx_nxv2i64:1482; RV64:       # %bb.0:1483; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1484; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t1485; RV64-NEXT:    ret1486  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01487  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1488  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1489  ret <vscale x 2 x i64> %v1490}1491 1492define <vscale x 2 x i64> @vsadd_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1493; RV32-LABEL: vsadd_vx_nxv2i64_unmasked:1494; RV32:       # %bb.0:1495; RV32-NEXT:    addi sp, sp, -161496; RV32-NEXT:    .cfi_def_cfa_offset 161497; RV32-NEXT:    sw a0, 8(sp)1498; RV32-NEXT:    sw a1, 12(sp)1499; RV32-NEXT:    addi a0, sp, 81500; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1501; RV32-NEXT:    vlse64.v v10, (a0), zero1502; RV32-NEXT:    vsadd.vv v8, v8, v101503; RV32-NEXT:    addi sp, sp, 161504; RV32-NEXT:    .cfi_def_cfa_offset 01505; RV32-NEXT:    ret1506;1507; RV64-LABEL: vsadd_vx_nxv2i64_unmasked:1508; RV64:       # %bb.0:1509; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1510; RV64-NEXT:    vsadd.vx v8, v8, a01511; RV64-NEXT:    ret1512  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01513  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1514  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1515  ret <vscale x 2 x i64> %v1516}1517 1518define <vscale x 2 x i64> @vsadd_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1519; CHECK-LABEL: vsadd_vi_nxv2i64:1520; CHECK:       # %bb.0:1521; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1522; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1523; CHECK-NEXT:    ret1524  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1525  ret <vscale x 2 x i64> %v1526}1527 1528define <vscale x 2 x i64> @vsadd_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1529; CHECK-LABEL: vsadd_vi_nxv2i64_unmasked:1530; CHECK:       # %bb.0:1531; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1532; CHECK-NEXT:    vsadd.vi v8, v8, -11533; CHECK-NEXT:    ret1534  %v = call <vscale x 2 x i64> @llvm.vp.sadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1535  ret <vscale x 2 x i64> %v1536}1537 1538define <vscale x 4 x i64> @vsadd_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1539; CHECK-LABEL: vsadd_vv_nxv4i64:1540; CHECK:       # %bb.0:1541; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1542; CHECK-NEXT:    vsadd.vv v8, v8, v12, v0.t1543; CHECK-NEXT:    ret1544  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1545  ret <vscale x 4 x i64> %v1546}1547 1548define <vscale x 4 x i64> @vsadd_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1549; CHECK-LABEL: vsadd_vv_nxv4i64_unmasked:1550; CHECK:       # %bb.0:1551; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1552; CHECK-NEXT:    vsadd.vv v8, v8, v121553; CHECK-NEXT:    ret1554  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1555  ret <vscale x 4 x i64> %v1556}1557 1558define <vscale x 4 x i64> @vsadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1559; RV32-LABEL: vsadd_vx_nxv4i64:1560; RV32:       # %bb.0:1561; RV32-NEXT:    addi sp, sp, -161562; RV32-NEXT:    .cfi_def_cfa_offset 161563; RV32-NEXT:    sw a0, 8(sp)1564; RV32-NEXT:    sw a1, 12(sp)1565; RV32-NEXT:    addi a0, sp, 81566; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1567; RV32-NEXT:    vlse64.v v12, (a0), zero1568; RV32-NEXT:    vsadd.vv v8, v8, v12, v0.t1569; RV32-NEXT:    addi sp, sp, 161570; RV32-NEXT:    .cfi_def_cfa_offset 01571; RV32-NEXT:    ret1572;1573; RV64-LABEL: vsadd_vx_nxv4i64:1574; RV64:       # %bb.0:1575; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1576; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t1577; RV64-NEXT:    ret1578  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01579  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1580  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1581  ret <vscale x 4 x i64> %v1582}1583 1584define <vscale x 4 x i64> @vsadd_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1585; RV32-LABEL: vsadd_vx_nxv4i64_unmasked:1586; RV32:       # %bb.0:1587; RV32-NEXT:    addi sp, sp, -161588; RV32-NEXT:    .cfi_def_cfa_offset 161589; RV32-NEXT:    sw a0, 8(sp)1590; RV32-NEXT:    sw a1, 12(sp)1591; RV32-NEXT:    addi a0, sp, 81592; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1593; RV32-NEXT:    vlse64.v v12, (a0), zero1594; RV32-NEXT:    vsadd.vv v8, v8, v121595; RV32-NEXT:    addi sp, sp, 161596; RV32-NEXT:    .cfi_def_cfa_offset 01597; RV32-NEXT:    ret1598;1599; RV64-LABEL: vsadd_vx_nxv4i64_unmasked:1600; RV64:       # %bb.0:1601; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1602; RV64-NEXT:    vsadd.vx v8, v8, a01603; RV64-NEXT:    ret1604  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01605  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1606  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1607  ret <vscale x 4 x i64> %v1608}1609 1610define <vscale x 4 x i64> @vsadd_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1611; CHECK-LABEL: vsadd_vi_nxv4i64:1612; CHECK:       # %bb.0:1613; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1614; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1615; CHECK-NEXT:    ret1616  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1617  ret <vscale x 4 x i64> %v1618}1619 1620define <vscale x 4 x i64> @vsadd_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1621; CHECK-LABEL: vsadd_vi_nxv4i64_unmasked:1622; CHECK:       # %bb.0:1623; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1624; CHECK-NEXT:    vsadd.vi v8, v8, -11625; CHECK-NEXT:    ret1626  %v = call <vscale x 4 x i64> @llvm.vp.sadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1627  ret <vscale x 4 x i64> %v1628}1629 1630define <vscale x 8 x i64> @vsadd_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1631; CHECK-LABEL: vsadd_vv_nxv8i64:1632; CHECK:       # %bb.0:1633; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1634; CHECK-NEXT:    vsadd.vv v8, v8, v16, v0.t1635; CHECK-NEXT:    ret1636  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1637  ret <vscale x 8 x i64> %v1638}1639 1640define <vscale x 8 x i64> @vsadd_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1641; CHECK-LABEL: vsadd_vv_nxv8i64_unmasked:1642; CHECK:       # %bb.0:1643; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1644; CHECK-NEXT:    vsadd.vv v8, v8, v161645; CHECK-NEXT:    ret1646  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1647  ret <vscale x 8 x i64> %v1648}1649 1650define <vscale x 8 x i64> @vsadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1651; RV32-LABEL: vsadd_vx_nxv8i64:1652; RV32:       # %bb.0:1653; RV32-NEXT:    addi sp, sp, -161654; RV32-NEXT:    .cfi_def_cfa_offset 161655; RV32-NEXT:    sw a0, 8(sp)1656; RV32-NEXT:    sw a1, 12(sp)1657; RV32-NEXT:    addi a0, sp, 81658; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1659; RV32-NEXT:    vlse64.v v16, (a0), zero1660; RV32-NEXT:    vsadd.vv v8, v8, v16, v0.t1661; RV32-NEXT:    addi sp, sp, 161662; RV32-NEXT:    .cfi_def_cfa_offset 01663; RV32-NEXT:    ret1664;1665; RV64-LABEL: vsadd_vx_nxv8i64:1666; RV64:       # %bb.0:1667; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1668; RV64-NEXT:    vsadd.vx v8, v8, a0, v0.t1669; RV64-NEXT:    ret1670  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01671  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1672  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1673  ret <vscale x 8 x i64> %v1674}1675 1676define <vscale x 8 x i64> @vsadd_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1677; RV32-LABEL: vsadd_vx_nxv8i64_unmasked:1678; RV32:       # %bb.0:1679; RV32-NEXT:    addi sp, sp, -161680; RV32-NEXT:    .cfi_def_cfa_offset 161681; RV32-NEXT:    sw a0, 8(sp)1682; RV32-NEXT:    sw a1, 12(sp)1683; RV32-NEXT:    addi a0, sp, 81684; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1685; RV32-NEXT:    vlse64.v v16, (a0), zero1686; RV32-NEXT:    vsadd.vv v8, v8, v161687; RV32-NEXT:    addi sp, sp, 161688; RV32-NEXT:    .cfi_def_cfa_offset 01689; RV32-NEXT:    ret1690;1691; RV64-LABEL: vsadd_vx_nxv8i64_unmasked:1692; RV64:       # %bb.0:1693; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1694; RV64-NEXT:    vsadd.vx v8, v8, a01695; RV64-NEXT:    ret1696  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01697  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1698  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1699  ret <vscale x 8 x i64> %v1700}1701 1702define <vscale x 8 x i64> @vsadd_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1703; CHECK-LABEL: vsadd_vi_nxv8i64:1704; CHECK:       # %bb.0:1705; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1706; CHECK-NEXT:    vsadd.vi v8, v8, -1, v0.t1707; CHECK-NEXT:    ret1708  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)1709  ret <vscale x 8 x i64> %v1710}1711 1712define <vscale x 8 x i64> @vsadd_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1713; CHECK-LABEL: vsadd_vi_nxv8i64_unmasked:1714; CHECK:       # %bb.0:1715; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1716; CHECK-NEXT:    vsadd.vi v8, v8, -11717; CHECK-NEXT:    ret1718  %v = call <vscale x 8 x i64> @llvm.vp.sadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1719  ret <vscale x 8 x i64> %v1720}1721