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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN:   | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN:   | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vsaddu_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vsaddu_vx_nxv8i7:9; CHECK:       # %bb.0:10; CHECK-NEXT:    li a2, 12711; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma12; CHECK-NEXT:    vmv.v.x v9, a013; CHECK-NEXT:    vand.vx v8, v8, a214; CHECK-NEXT:    vand.vx v9, v9, a215; CHECK-NEXT:    vadd.vv v8, v8, v9, v0.t16; CHECK-NEXT:    vminu.vx v8, v8, a2, v0.t17; CHECK-NEXT:    ret18  %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 019  %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer20  %v = call <vscale x 8 x i7> @llvm.vp.uadd.sat.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)21  ret <vscale x 8 x i7> %v22}23 24define <vscale x 1 x i8> @vsaddu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {25; CHECK-LABEL: vsaddu_vv_nxv1i8:26; CHECK:       # %bb.0:27; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma28; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t29; CHECK-NEXT:    ret30  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)31  ret <vscale x 1 x i8> %v32}33 34define <vscale x 1 x i8> @vsaddu_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {35; CHECK-LABEL: vsaddu_vv_nxv1i8_unmasked:36; CHECK:       # %bb.0:37; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma38; CHECK-NEXT:    vsaddu.vv v8, v8, v939; CHECK-NEXT:    ret40  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)41  ret <vscale x 1 x i8> %v42}43 44define <vscale x 1 x i8> @vsaddu_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {45; CHECK-LABEL: vsaddu_vx_nxv1i8:46; CHECK:       # %bb.0:47; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma48; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t49; CHECK-NEXT:    ret50  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 051  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer52  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)53  ret <vscale x 1 x i8> %v54}55 56define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {57; CHECK-LABEL: vsaddu_vx_nxv1i8_commute:58; CHECK:       # %bb.0:59; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma60; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t61; CHECK-NEXT:    ret62  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 063  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer64  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl)65  ret <vscale x 1 x i8> %v66}67 68define <vscale x 1 x i8> @vsaddu_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {69; CHECK-LABEL: vsaddu_vx_nxv1i8_unmasked:70; CHECK:       # %bb.0:71; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma72; CHECK-NEXT:    vsaddu.vx v8, v8, a073; CHECK-NEXT:    ret74  %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 075  %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer76  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)77  ret <vscale x 1 x i8> %v78}79 80define <vscale x 1 x i8> @vsaddu_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {81; CHECK-LABEL: vsaddu_vi_nxv1i8:82; CHECK:       # %bb.0:83; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma84; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t85; CHECK-NEXT:    ret86  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> %m, i32 %evl)87  ret <vscale x 1 x i8> %v88}89 90define <vscale x 1 x i8> @vsaddu_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {91; CHECK-LABEL: vsaddu_vi_nxv1i8_unmasked:92; CHECK:       # %bb.0:93; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma94; CHECK-NEXT:    vsaddu.vi v8, v8, -195; CHECK-NEXT:    ret96  %v = call <vscale x 1 x i8> @llvm.vp.uadd.sat.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)97  ret <vscale x 1 x i8> %v98}99 100define <vscale x 2 x i8> @vsaddu_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {101; CHECK-LABEL: vsaddu_vv_nxv2i8:102; CHECK:       # %bb.0:103; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma104; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t105; CHECK-NEXT:    ret106  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)107  ret <vscale x 2 x i8> %v108}109 110define <vscale x 2 x i8> @vsaddu_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {111; CHECK-LABEL: vsaddu_vv_nxv2i8_unmasked:112; CHECK:       # %bb.0:113; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma114; CHECK-NEXT:    vsaddu.vv v8, v8, v9115; CHECK-NEXT:    ret116  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)117  ret <vscale x 2 x i8> %v118}119 120define <vscale x 2 x i8> @vsaddu_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {121; CHECK-LABEL: vsaddu_vx_nxv2i8:122; CHECK:       # %bb.0:123; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma124; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t125; CHECK-NEXT:    ret126  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0127  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer128  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)129  ret <vscale x 2 x i8> %v130}131 132define <vscale x 2 x i8> @vsaddu_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {133; CHECK-LABEL: vsaddu_vx_nxv2i8_unmasked:134; CHECK:       # %bb.0:135; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma136; CHECK-NEXT:    vsaddu.vx v8, v8, a0137; CHECK-NEXT:    ret138  %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0139  %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer140  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)141  ret <vscale x 2 x i8> %v142}143 144define <vscale x 2 x i8> @vsaddu_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {145; CHECK-LABEL: vsaddu_vi_nxv2i8:146; CHECK:       # %bb.0:147; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma148; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t149; CHECK-NEXT:    ret150  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> %m, i32 %evl)151  ret <vscale x 2 x i8> %v152}153 154define <vscale x 2 x i8> @vsaddu_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {155; CHECK-LABEL: vsaddu_vi_nxv2i8_unmasked:156; CHECK:       # %bb.0:157; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma158; CHECK-NEXT:    vsaddu.vi v8, v8, -1159; CHECK-NEXT:    ret160  %v = call <vscale x 2 x i8> @llvm.vp.uadd.sat.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)161  ret <vscale x 2 x i8> %v162}163 164define <vscale x 3 x i8> @vsaddu_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {165; CHECK-LABEL: vsaddu_vv_nxv3i8:166; CHECK:       # %bb.0:167; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma168; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t169; CHECK-NEXT:    ret170  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl)171  ret <vscale x 3 x i8> %v172}173 174define <vscale x 3 x i8> @vsaddu_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) {175; CHECK-LABEL: vsaddu_vv_nxv3i8_unmasked:176; CHECK:       # %bb.0:177; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma178; CHECK-NEXT:    vsaddu.vv v8, v8, v9179; CHECK-NEXT:    ret180  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> splat (i1 true), i32 %evl)181  ret <vscale x 3 x i8> %v182}183 184define <vscale x 3 x i8> @vsaddu_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) {185; CHECK-LABEL: vsaddu_vx_nxv3i8:186; CHECK:       # %bb.0:187; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma188; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t189; CHECK-NEXT:    ret190  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0191  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer192  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl)193  ret <vscale x 3 x i8> %v194}195 196define <vscale x 3 x i8> @vsaddu_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) {197; CHECK-LABEL: vsaddu_vx_nxv3i8_unmasked:198; CHECK:       # %bb.0:199; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma200; CHECK-NEXT:    vsaddu.vx v8, v8, a0201; CHECK-NEXT:    ret202  %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0203  %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer204  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> splat (i1 true), i32 %evl)205  ret <vscale x 3 x i8> %v206}207 208define <vscale x 3 x i8> @vsaddu_vi_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %m, i32 zeroext %evl) {209; CHECK-LABEL: vsaddu_vi_nxv3i8:210; CHECK:       # %bb.0:211; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma212; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t213; CHECK-NEXT:    ret214  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> %m, i32 %evl)215  ret <vscale x 3 x i8> %v216}217 218define <vscale x 3 x i8> @vsaddu_vi_nxv3i8_unmasked(<vscale x 3 x i8> %va, i32 zeroext %evl) {219; CHECK-LABEL: vsaddu_vi_nxv3i8_unmasked:220; CHECK:       # %bb.0:221; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma222; CHECK-NEXT:    vsaddu.vi v8, v8, -1223; CHECK-NEXT:    ret224  %v = call <vscale x 3 x i8> @llvm.vp.uadd.sat.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> splat (i8 -1), <vscale x 3 x i1> splat (i1 true), i32 %evl)225  ret <vscale x 3 x i8> %v226}227 228define <vscale x 4 x i8> @vsaddu_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {229; CHECK-LABEL: vsaddu_vv_nxv4i8:230; CHECK:       # %bb.0:231; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma232; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t233; CHECK-NEXT:    ret234  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)235  ret <vscale x 4 x i8> %v236}237 238define <vscale x 4 x i8> @vsaddu_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {239; CHECK-LABEL: vsaddu_vv_nxv4i8_unmasked:240; CHECK:       # %bb.0:241; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma242; CHECK-NEXT:    vsaddu.vv v8, v8, v9243; CHECK-NEXT:    ret244  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)245  ret <vscale x 4 x i8> %v246}247 248define <vscale x 4 x i8> @vsaddu_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {249; CHECK-LABEL: vsaddu_vx_nxv4i8:250; CHECK:       # %bb.0:251; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma252; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t253; CHECK-NEXT:    ret254  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0255  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer256  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)257  ret <vscale x 4 x i8> %v258}259 260define <vscale x 4 x i8> @vsaddu_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {261; CHECK-LABEL: vsaddu_vx_nxv4i8_unmasked:262; CHECK:       # %bb.0:263; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma264; CHECK-NEXT:    vsaddu.vx v8, v8, a0265; CHECK-NEXT:    ret266  %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0267  %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer268  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)269  ret <vscale x 4 x i8> %v270}271 272define <vscale x 4 x i8> @vsaddu_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {273; CHECK-LABEL: vsaddu_vi_nxv4i8:274; CHECK:       # %bb.0:275; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma276; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t277; CHECK-NEXT:    ret278  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> %m, i32 %evl)279  ret <vscale x 4 x i8> %v280}281 282define <vscale x 4 x i8> @vsaddu_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {283; CHECK-LABEL: vsaddu_vi_nxv4i8_unmasked:284; CHECK:       # %bb.0:285; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma286; CHECK-NEXT:    vsaddu.vi v8, v8, -1287; CHECK-NEXT:    ret288  %v = call <vscale x 4 x i8> @llvm.vp.uadd.sat.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)289  ret <vscale x 4 x i8> %v290}291 292define <vscale x 8 x i8> @vsaddu_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {293; CHECK-LABEL: vsaddu_vv_nxv8i8:294; CHECK:       # %bb.0:295; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma296; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t297; CHECK-NEXT:    ret298  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)299  ret <vscale x 8 x i8> %v300}301 302define <vscale x 8 x i8> @vsaddu_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {303; CHECK-LABEL: vsaddu_vv_nxv8i8_unmasked:304; CHECK:       # %bb.0:305; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma306; CHECK-NEXT:    vsaddu.vv v8, v8, v9307; CHECK-NEXT:    ret308  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)309  ret <vscale x 8 x i8> %v310}311 312define <vscale x 8 x i8> @vsaddu_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {313; CHECK-LABEL: vsaddu_vx_nxv8i8:314; CHECK:       # %bb.0:315; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma316; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t317; CHECK-NEXT:    ret318  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0319  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer320  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)321  ret <vscale x 8 x i8> %v322}323 324define <vscale x 8 x i8> @vsaddu_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {325; CHECK-LABEL: vsaddu_vx_nxv8i8_unmasked:326; CHECK:       # %bb.0:327; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma328; CHECK-NEXT:    vsaddu.vx v8, v8, a0329; CHECK-NEXT:    ret330  %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0331  %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer332  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)333  ret <vscale x 8 x i8> %v334}335 336define <vscale x 8 x i8> @vsaddu_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {337; CHECK-LABEL: vsaddu_vi_nxv8i8:338; CHECK:       # %bb.0:339; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma340; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t341; CHECK-NEXT:    ret342  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> %m, i32 %evl)343  ret <vscale x 8 x i8> %v344}345 346define <vscale x 8 x i8> @vsaddu_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {347; CHECK-LABEL: vsaddu_vi_nxv8i8_unmasked:348; CHECK:       # %bb.0:349; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma350; CHECK-NEXT:    vsaddu.vi v8, v8, -1351; CHECK-NEXT:    ret352  %v = call <vscale x 8 x i8> @llvm.vp.uadd.sat.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)353  ret <vscale x 8 x i8> %v354}355 356define <vscale x 16 x i8> @vsaddu_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {357; CHECK-LABEL: vsaddu_vv_nxv16i8:358; CHECK:       # %bb.0:359; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma360; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t361; CHECK-NEXT:    ret362  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)363  ret <vscale x 16 x i8> %v364}365 366define <vscale x 16 x i8> @vsaddu_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {367; CHECK-LABEL: vsaddu_vv_nxv16i8_unmasked:368; CHECK:       # %bb.0:369; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma370; CHECK-NEXT:    vsaddu.vv v8, v8, v10371; CHECK-NEXT:    ret372  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)373  ret <vscale x 16 x i8> %v374}375 376define <vscale x 16 x i8> @vsaddu_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {377; CHECK-LABEL: vsaddu_vx_nxv16i8:378; CHECK:       # %bb.0:379; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma380; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t381; CHECK-NEXT:    ret382  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0383  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer384  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)385  ret <vscale x 16 x i8> %v386}387 388define <vscale x 16 x i8> @vsaddu_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {389; CHECK-LABEL: vsaddu_vx_nxv16i8_unmasked:390; CHECK:       # %bb.0:391; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma392; CHECK-NEXT:    vsaddu.vx v8, v8, a0393; CHECK-NEXT:    ret394  %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0395  %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer396  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)397  ret <vscale x 16 x i8> %v398}399 400define <vscale x 16 x i8> @vsaddu_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {401; CHECK-LABEL: vsaddu_vi_nxv16i8:402; CHECK:       # %bb.0:403; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma404; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t405; CHECK-NEXT:    ret406  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> %m, i32 %evl)407  ret <vscale x 16 x i8> %v408}409 410define <vscale x 16 x i8> @vsaddu_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {411; CHECK-LABEL: vsaddu_vi_nxv16i8_unmasked:412; CHECK:       # %bb.0:413; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma414; CHECK-NEXT:    vsaddu.vi v8, v8, -1415; CHECK-NEXT:    ret416  %v = call <vscale x 16 x i8> @llvm.vp.uadd.sat.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)417  ret <vscale x 16 x i8> %v418}419 420define <vscale x 32 x i8> @vsaddu_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {421; CHECK-LABEL: vsaddu_vv_nxv32i8:422; CHECK:       # %bb.0:423; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma424; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t425; CHECK-NEXT:    ret426  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)427  ret <vscale x 32 x i8> %v428}429 430define <vscale x 32 x i8> @vsaddu_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {431; CHECK-LABEL: vsaddu_vv_nxv32i8_unmasked:432; CHECK:       # %bb.0:433; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma434; CHECK-NEXT:    vsaddu.vv v8, v8, v12435; CHECK-NEXT:    ret436  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)437  ret <vscale x 32 x i8> %v438}439 440define <vscale x 32 x i8> @vsaddu_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {441; CHECK-LABEL: vsaddu_vx_nxv32i8:442; CHECK:       # %bb.0:443; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma444; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t445; CHECK-NEXT:    ret446  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0447  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer448  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)449  ret <vscale x 32 x i8> %v450}451 452define <vscale x 32 x i8> @vsaddu_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {453; CHECK-LABEL: vsaddu_vx_nxv32i8_unmasked:454; CHECK:       # %bb.0:455; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma456; CHECK-NEXT:    vsaddu.vx v8, v8, a0457; CHECK-NEXT:    ret458  %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0459  %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer460  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)461  ret <vscale x 32 x i8> %v462}463 464define <vscale x 32 x i8> @vsaddu_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {465; CHECK-LABEL: vsaddu_vi_nxv32i8:466; CHECK:       # %bb.0:467; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma468; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t469; CHECK-NEXT:    ret470  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> %m, i32 %evl)471  ret <vscale x 32 x i8> %v472}473 474define <vscale x 32 x i8> @vsaddu_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {475; CHECK-LABEL: vsaddu_vi_nxv32i8_unmasked:476; CHECK:       # %bb.0:477; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma478; CHECK-NEXT:    vsaddu.vi v8, v8, -1479; CHECK-NEXT:    ret480  %v = call <vscale x 32 x i8> @llvm.vp.uadd.sat.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)481  ret <vscale x 32 x i8> %v482}483 484define <vscale x 64 x i8> @vsaddu_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {485; CHECK-LABEL: vsaddu_vv_nxv64i8:486; CHECK:       # %bb.0:487; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma488; CHECK-NEXT:    vsaddu.vv v8, v8, v16, v0.t489; CHECK-NEXT:    ret490  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)491  ret <vscale x 64 x i8> %v492}493 494define <vscale x 64 x i8> @vsaddu_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {495; CHECK-LABEL: vsaddu_vv_nxv64i8_unmasked:496; CHECK:       # %bb.0:497; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma498; CHECK-NEXT:    vsaddu.vv v8, v8, v16499; CHECK-NEXT:    ret500  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)501  ret <vscale x 64 x i8> %v502}503 504define <vscale x 64 x i8> @vsaddu_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {505; CHECK-LABEL: vsaddu_vx_nxv64i8:506; CHECK:       # %bb.0:507; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma508; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t509; CHECK-NEXT:    ret510  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0511  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer512  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)513  ret <vscale x 64 x i8> %v514}515 516define <vscale x 64 x i8> @vsaddu_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {517; CHECK-LABEL: vsaddu_vx_nxv64i8_unmasked:518; CHECK:       # %bb.0:519; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma520; CHECK-NEXT:    vsaddu.vx v8, v8, a0521; CHECK-NEXT:    ret522  %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0523  %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer524  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)525  ret <vscale x 64 x i8> %v526}527 528define <vscale x 64 x i8> @vsaddu_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {529; CHECK-LABEL: vsaddu_vi_nxv64i8:530; CHECK:       # %bb.0:531; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma532; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t533; CHECK-NEXT:    ret534  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> %m, i32 %evl)535  ret <vscale x 64 x i8> %v536}537 538define <vscale x 64 x i8> @vsaddu_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {539; CHECK-LABEL: vsaddu_vi_nxv64i8_unmasked:540; CHECK:       # %bb.0:541; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma542; CHECK-NEXT:    vsaddu.vi v8, v8, -1543; CHECK-NEXT:    ret544  %v = call <vscale x 64 x i8> @llvm.vp.uadd.sat.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 -1), <vscale x 64 x i1> splat (i1 true), i32 %evl)545  ret <vscale x 64 x i8> %v546}547 548; Test that split-legalization works when the mask itself needs splitting.549 550define <vscale x 128 x i8> @vsaddu_vi_nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i1> %m, i32 zeroext %evl) {551; CHECK-LABEL: vsaddu_vi_nxv128i8:552; CHECK:       # %bb.0:553; CHECK-NEXT:    vsetvli a2, zero, e8, m8, ta, ma554; CHECK-NEXT:    vmv1r.v v24, v0555; CHECK-NEXT:    vlm.v v0, (a0)556; CHECK-NEXT:    csrr a0, vlenb557; CHECK-NEXT:    slli a0, a0, 3558; CHECK-NEXT:    sub a2, a1, a0559; CHECK-NEXT:    sltu a3, a1, a2560; CHECK-NEXT:    addi a3, a3, -1561; CHECK-NEXT:    and a2, a3, a2562; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma563; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t564; CHECK-NEXT:    bltu a1, a0, .LBB50_2565; CHECK-NEXT:  # %bb.1:566; CHECK-NEXT:    mv a1, a0567; CHECK-NEXT:  .LBB50_2:568; CHECK-NEXT:    vmv1r.v v0, v24569; CHECK-NEXT:    vsetvli zero, a1, e8, m8, ta, ma570; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t571; CHECK-NEXT:    ret572  %v = call <vscale x 128 x i8> @llvm.vp.uadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> %m, i32 %evl)573  ret <vscale x 128 x i8> %v574}575 576define <vscale x 128 x i8> @vsaddu_vi_nxv128i8_unmasked(<vscale x 128 x i8> %va, i32 zeroext %evl) {577; CHECK-LABEL: vsaddu_vi_nxv128i8_unmasked:578; CHECK:       # %bb.0:579; CHECK-NEXT:    csrr a1, vlenb580; CHECK-NEXT:    slli a1, a1, 3581; CHECK-NEXT:    sub a2, a0, a1582; CHECK-NEXT:    sltu a3, a0, a2583; CHECK-NEXT:    addi a3, a3, -1584; CHECK-NEXT:    and a2, a3, a2585; CHECK-NEXT:    vsetvli zero, a2, e8, m8, ta, ma586; CHECK-NEXT:    vsaddu.vi v16, v16, -1587; CHECK-NEXT:    bltu a0, a1, .LBB51_2588; CHECK-NEXT:  # %bb.1:589; CHECK-NEXT:    mv a0, a1590; CHECK-NEXT:  .LBB51_2:591; CHECK-NEXT:    vsetvli zero, a0, e8, m8, ta, ma592; CHECK-NEXT:    vsaddu.vi v8, v8, -1593; CHECK-NEXT:    ret594  %v = call <vscale x 128 x i8> @llvm.vp.uadd.sat.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> splat (i8 -1), <vscale x 128 x i1> splat (i1 true), i32 %evl)595  ret <vscale x 128 x i8> %v596}597 598define <vscale x 1 x i16> @vsaddu_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {599; CHECK-LABEL: vsaddu_vv_nxv1i16:600; CHECK:       # %bb.0:601; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma602; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t603; CHECK-NEXT:    ret604  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)605  ret <vscale x 1 x i16> %v606}607 608define <vscale x 1 x i16> @vsaddu_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {609; CHECK-LABEL: vsaddu_vv_nxv1i16_unmasked:610; CHECK:       # %bb.0:611; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma612; CHECK-NEXT:    vsaddu.vv v8, v8, v9613; CHECK-NEXT:    ret614  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)615  ret <vscale x 1 x i16> %v616}617 618define <vscale x 1 x i16> @vsaddu_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {619; CHECK-LABEL: vsaddu_vx_nxv1i16:620; CHECK:       # %bb.0:621; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma622; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t623; CHECK-NEXT:    ret624  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0625  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer626  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)627  ret <vscale x 1 x i16> %v628}629 630define <vscale x 1 x i16> @vsaddu_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {631; CHECK-LABEL: vsaddu_vx_nxv1i16_unmasked:632; CHECK:       # %bb.0:633; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma634; CHECK-NEXT:    vsaddu.vx v8, v8, a0635; CHECK-NEXT:    ret636  %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0637  %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer638  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)639  ret <vscale x 1 x i16> %v640}641 642define <vscale x 1 x i16> @vsaddu_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {643; CHECK-LABEL: vsaddu_vi_nxv1i16:644; CHECK:       # %bb.0:645; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma646; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t647; CHECK-NEXT:    ret648  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> %m, i32 %evl)649  ret <vscale x 1 x i16> %v650}651 652define <vscale x 1 x i16> @vsaddu_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {653; CHECK-LABEL: vsaddu_vi_nxv1i16_unmasked:654; CHECK:       # %bb.0:655; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma656; CHECK-NEXT:    vsaddu.vi v8, v8, -1657; CHECK-NEXT:    ret658  %v = call <vscale x 1 x i16> @llvm.vp.uadd.sat.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)659  ret <vscale x 1 x i16> %v660}661 662define <vscale x 2 x i16> @vsaddu_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {663; CHECK-LABEL: vsaddu_vv_nxv2i16:664; CHECK:       # %bb.0:665; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma666; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t667; CHECK-NEXT:    ret668  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)669  ret <vscale x 2 x i16> %v670}671 672define <vscale x 2 x i16> @vsaddu_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {673; CHECK-LABEL: vsaddu_vv_nxv2i16_unmasked:674; CHECK:       # %bb.0:675; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma676; CHECK-NEXT:    vsaddu.vv v8, v8, v9677; CHECK-NEXT:    ret678  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)679  ret <vscale x 2 x i16> %v680}681 682define <vscale x 2 x i16> @vsaddu_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {683; CHECK-LABEL: vsaddu_vx_nxv2i16:684; CHECK:       # %bb.0:685; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma686; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t687; CHECK-NEXT:    ret688  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0689  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer690  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)691  ret <vscale x 2 x i16> %v692}693 694define <vscale x 2 x i16> @vsaddu_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {695; CHECK-LABEL: vsaddu_vx_nxv2i16_unmasked:696; CHECK:       # %bb.0:697; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma698; CHECK-NEXT:    vsaddu.vx v8, v8, a0699; CHECK-NEXT:    ret700  %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0701  %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer702  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)703  ret <vscale x 2 x i16> %v704}705 706define <vscale x 2 x i16> @vsaddu_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {707; CHECK-LABEL: vsaddu_vi_nxv2i16:708; CHECK:       # %bb.0:709; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma710; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t711; CHECK-NEXT:    ret712  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> %m, i32 %evl)713  ret <vscale x 2 x i16> %v714}715 716define <vscale x 2 x i16> @vsaddu_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {717; CHECK-LABEL: vsaddu_vi_nxv2i16_unmasked:718; CHECK:       # %bb.0:719; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma720; CHECK-NEXT:    vsaddu.vi v8, v8, -1721; CHECK-NEXT:    ret722  %v = call <vscale x 2 x i16> @llvm.vp.uadd.sat.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)723  ret <vscale x 2 x i16> %v724}725 726define <vscale x 4 x i16> @vsaddu_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {727; CHECK-LABEL: vsaddu_vv_nxv4i16:728; CHECK:       # %bb.0:729; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma730; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t731; CHECK-NEXT:    ret732  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)733  ret <vscale x 4 x i16> %v734}735 736define <vscale x 4 x i16> @vsaddu_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {737; CHECK-LABEL: vsaddu_vv_nxv4i16_unmasked:738; CHECK:       # %bb.0:739; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma740; CHECK-NEXT:    vsaddu.vv v8, v8, v9741; CHECK-NEXT:    ret742  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)743  ret <vscale x 4 x i16> %v744}745 746define <vscale x 4 x i16> @vsaddu_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {747; CHECK-LABEL: vsaddu_vx_nxv4i16:748; CHECK:       # %bb.0:749; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma750; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t751; CHECK-NEXT:    ret752  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0753  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer754  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)755  ret <vscale x 4 x i16> %v756}757 758define <vscale x 4 x i16> @vsaddu_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {759; CHECK-LABEL: vsaddu_vx_nxv4i16_unmasked:760; CHECK:       # %bb.0:761; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma762; CHECK-NEXT:    vsaddu.vx v8, v8, a0763; CHECK-NEXT:    ret764  %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0765  %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer766  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)767  ret <vscale x 4 x i16> %v768}769 770define <vscale x 4 x i16> @vsaddu_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {771; CHECK-LABEL: vsaddu_vi_nxv4i16:772; CHECK:       # %bb.0:773; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma774; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t775; CHECK-NEXT:    ret776  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> %m, i32 %evl)777  ret <vscale x 4 x i16> %v778}779 780define <vscale x 4 x i16> @vsaddu_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {781; CHECK-LABEL: vsaddu_vi_nxv4i16_unmasked:782; CHECK:       # %bb.0:783; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma784; CHECK-NEXT:    vsaddu.vi v8, v8, -1785; CHECK-NEXT:    ret786  %v = call <vscale x 4 x i16> @llvm.vp.uadd.sat.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)787  ret <vscale x 4 x i16> %v788}789 790define <vscale x 8 x i16> @vsaddu_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {791; CHECK-LABEL: vsaddu_vv_nxv8i16:792; CHECK:       # %bb.0:793; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma794; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t795; CHECK-NEXT:    ret796  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)797  ret <vscale x 8 x i16> %v798}799 800define <vscale x 8 x i16> @vsaddu_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {801; CHECK-LABEL: vsaddu_vv_nxv8i16_unmasked:802; CHECK:       # %bb.0:803; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma804; CHECK-NEXT:    vsaddu.vv v8, v8, v10805; CHECK-NEXT:    ret806  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)807  ret <vscale x 8 x i16> %v808}809 810define <vscale x 8 x i16> @vsaddu_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {811; CHECK-LABEL: vsaddu_vx_nxv8i16:812; CHECK:       # %bb.0:813; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma814; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t815; CHECK-NEXT:    ret816  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0817  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer818  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)819  ret <vscale x 8 x i16> %v820}821 822define <vscale x 8 x i16> @vsaddu_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {823; CHECK-LABEL: vsaddu_vx_nxv8i16_unmasked:824; CHECK:       # %bb.0:825; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma826; CHECK-NEXT:    vsaddu.vx v8, v8, a0827; CHECK-NEXT:    ret828  %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0829  %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer830  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)831  ret <vscale x 8 x i16> %v832}833 834define <vscale x 8 x i16> @vsaddu_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {835; CHECK-LABEL: vsaddu_vi_nxv8i16:836; CHECK:       # %bb.0:837; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma838; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t839; CHECK-NEXT:    ret840  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> %m, i32 %evl)841  ret <vscale x 8 x i16> %v842}843 844define <vscale x 8 x i16> @vsaddu_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {845; CHECK-LABEL: vsaddu_vi_nxv8i16_unmasked:846; CHECK:       # %bb.0:847; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma848; CHECK-NEXT:    vsaddu.vi v8, v8, -1849; CHECK-NEXT:    ret850  %v = call <vscale x 8 x i16> @llvm.vp.uadd.sat.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)851  ret <vscale x 8 x i16> %v852}853 854define <vscale x 16 x i16> @vsaddu_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {855; CHECK-LABEL: vsaddu_vv_nxv16i16:856; CHECK:       # %bb.0:857; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma858; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t859; CHECK-NEXT:    ret860  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)861  ret <vscale x 16 x i16> %v862}863 864define <vscale x 16 x i16> @vsaddu_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {865; CHECK-LABEL: vsaddu_vv_nxv16i16_unmasked:866; CHECK:       # %bb.0:867; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma868; CHECK-NEXT:    vsaddu.vv v8, v8, v12869; CHECK-NEXT:    ret870  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)871  ret <vscale x 16 x i16> %v872}873 874define <vscale x 16 x i16> @vsaddu_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {875; CHECK-LABEL: vsaddu_vx_nxv16i16:876; CHECK:       # %bb.0:877; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma878; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t879; CHECK-NEXT:    ret880  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0881  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer882  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)883  ret <vscale x 16 x i16> %v884}885 886define <vscale x 16 x i16> @vsaddu_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {887; CHECK-LABEL: vsaddu_vx_nxv16i16_unmasked:888; CHECK:       # %bb.0:889; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma890; CHECK-NEXT:    vsaddu.vx v8, v8, a0891; CHECK-NEXT:    ret892  %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0893  %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer894  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)895  ret <vscale x 16 x i16> %v896}897 898define <vscale x 16 x i16> @vsaddu_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {899; CHECK-LABEL: vsaddu_vi_nxv16i16:900; CHECK:       # %bb.0:901; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma902; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t903; CHECK-NEXT:    ret904  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> %m, i32 %evl)905  ret <vscale x 16 x i16> %v906}907 908define <vscale x 16 x i16> @vsaddu_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {909; CHECK-LABEL: vsaddu_vi_nxv16i16_unmasked:910; CHECK:       # %bb.0:911; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma912; CHECK-NEXT:    vsaddu.vi v8, v8, -1913; CHECK-NEXT:    ret914  %v = call <vscale x 16 x i16> @llvm.vp.uadd.sat.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)915  ret <vscale x 16 x i16> %v916}917 918define <vscale x 32 x i16> @vsaddu_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {919; CHECK-LABEL: vsaddu_vv_nxv32i16:920; CHECK:       # %bb.0:921; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma922; CHECK-NEXT:    vsaddu.vv v8, v8, v16, v0.t923; CHECK-NEXT:    ret924  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)925  ret <vscale x 32 x i16> %v926}927 928define <vscale x 32 x i16> @vsaddu_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {929; CHECK-LABEL: vsaddu_vv_nxv32i16_unmasked:930; CHECK:       # %bb.0:931; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma932; CHECK-NEXT:    vsaddu.vv v8, v8, v16933; CHECK-NEXT:    ret934  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)935  ret <vscale x 32 x i16> %v936}937 938define <vscale x 32 x i16> @vsaddu_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {939; CHECK-LABEL: vsaddu_vx_nxv32i16:940; CHECK:       # %bb.0:941; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma942; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t943; CHECK-NEXT:    ret944  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0945  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer946  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)947  ret <vscale x 32 x i16> %v948}949 950define <vscale x 32 x i16> @vsaddu_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {951; CHECK-LABEL: vsaddu_vx_nxv32i16_unmasked:952; CHECK:       # %bb.0:953; CHECK-NEXT:    vsetvli zero, a1, e16, m8, ta, ma954; CHECK-NEXT:    vsaddu.vx v8, v8, a0955; CHECK-NEXT:    ret956  %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0957  %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer958  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)959  ret <vscale x 32 x i16> %v960}961 962define <vscale x 32 x i16> @vsaddu_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {963; CHECK-LABEL: vsaddu_vi_nxv32i16:964; CHECK:       # %bb.0:965; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma966; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t967; CHECK-NEXT:    ret968  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> %m, i32 %evl)969  ret <vscale x 32 x i16> %v970}971 972define <vscale x 32 x i16> @vsaddu_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {973; CHECK-LABEL: vsaddu_vi_nxv32i16_unmasked:974; CHECK:       # %bb.0:975; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma976; CHECK-NEXT:    vsaddu.vi v8, v8, -1977; CHECK-NEXT:    ret978  %v = call <vscale x 32 x i16> @llvm.vp.uadd.sat.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)979  ret <vscale x 32 x i16> %v980}981 982define <vscale x 1 x i32> @vsaddu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {983; CHECK-LABEL: vsaddu_vv_nxv1i32:984; CHECK:       # %bb.0:985; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma986; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t987; CHECK-NEXT:    ret988  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)989  ret <vscale x 1 x i32> %v990}991 992define <vscale x 1 x i32> @vsaddu_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {993; CHECK-LABEL: vsaddu_vv_nxv1i32_unmasked:994; CHECK:       # %bb.0:995; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma996; CHECK-NEXT:    vsaddu.vv v8, v8, v9997; CHECK-NEXT:    ret998  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)999  ret <vscale x 1 x i32> %v1000}1001 1002define <vscale x 1 x i32> @vsaddu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1003; CHECK-LABEL: vsaddu_vx_nxv1i32:1004; CHECK:       # %bb.0:1005; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1006; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t1007; CHECK-NEXT:    ret1008  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01009  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1010  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)1011  ret <vscale x 1 x i32> %v1012}1013 1014define <vscale x 1 x i32> @vsaddu_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {1015; CHECK-LABEL: vsaddu_vx_nxv1i32_unmasked:1016; CHECK:       # %bb.0:1017; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1018; CHECK-NEXT:    vsaddu.vx v8, v8, a01019; CHECK-NEXT:    ret1020  %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 01021  %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer1022  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1023  ret <vscale x 1 x i32> %v1024}1025 1026define <vscale x 1 x i32> @vsaddu_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1027; CHECK-LABEL: vsaddu_vi_nxv1i32:1028; CHECK:       # %bb.0:1029; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1030; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1031; CHECK-NEXT:    ret1032  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> %m, i32 %evl)1033  ret <vscale x 1 x i32> %v1034}1035 1036define <vscale x 1 x i32> @vsaddu_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {1037; CHECK-LABEL: vsaddu_vi_nxv1i32_unmasked:1038; CHECK:       # %bb.0:1039; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1040; CHECK-NEXT:    vsaddu.vi v8, v8, -11041; CHECK-NEXT:    ret1042  %v = call <vscale x 1 x i32> @llvm.vp.uadd.sat.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1043  ret <vscale x 1 x i32> %v1044}1045 1046define <vscale x 2 x i32> @vsaddu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1047; CHECK-LABEL: vsaddu_vv_nxv2i32:1048; CHECK:       # %bb.0:1049; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1050; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t1051; CHECK-NEXT:    ret1052  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)1053  ret <vscale x 2 x i32> %v1054}1055 1056define <vscale x 2 x i32> @vsaddu_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {1057; CHECK-LABEL: vsaddu_vv_nxv2i32_unmasked:1058; CHECK:       # %bb.0:1059; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1060; CHECK-NEXT:    vsaddu.vv v8, v8, v91061; CHECK-NEXT:    ret1062  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1063  ret <vscale x 2 x i32> %v1064}1065 1066define <vscale x 2 x i32> @vsaddu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1067; CHECK-LABEL: vsaddu_vx_nxv2i32:1068; CHECK:       # %bb.0:1069; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1070; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t1071; CHECK-NEXT:    ret1072  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01073  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1074  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)1075  ret <vscale x 2 x i32> %v1076}1077 1078define <vscale x 2 x i32> @vsaddu_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {1079; CHECK-LABEL: vsaddu_vx_nxv2i32_unmasked:1080; CHECK:       # %bb.0:1081; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1082; CHECK-NEXT:    vsaddu.vx v8, v8, a01083; CHECK-NEXT:    ret1084  %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 01085  %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer1086  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1087  ret <vscale x 2 x i32> %v1088}1089 1090define <vscale x 2 x i32> @vsaddu_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1091; CHECK-LABEL: vsaddu_vi_nxv2i32:1092; CHECK:       # %bb.0:1093; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1094; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1095; CHECK-NEXT:    ret1096  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> %m, i32 %evl)1097  ret <vscale x 2 x i32> %v1098}1099 1100define <vscale x 2 x i32> @vsaddu_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {1101; CHECK-LABEL: vsaddu_vi_nxv2i32_unmasked:1102; CHECK:       # %bb.0:1103; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1104; CHECK-NEXT:    vsaddu.vi v8, v8, -11105; CHECK-NEXT:    ret1106  %v = call <vscale x 2 x i32> @llvm.vp.uadd.sat.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1107  ret <vscale x 2 x i32> %v1108}1109 1110define <vscale x 4 x i32> @vsaddu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1111; CHECK-LABEL: vsaddu_vv_nxv4i32:1112; CHECK:       # %bb.0:1113; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1114; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t1115; CHECK-NEXT:    ret1116  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)1117  ret <vscale x 4 x i32> %v1118}1119 1120define <vscale x 4 x i32> @vsaddu_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {1121; CHECK-LABEL: vsaddu_vv_nxv4i32_unmasked:1122; CHECK:       # %bb.0:1123; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1124; CHECK-NEXT:    vsaddu.vv v8, v8, v101125; CHECK-NEXT:    ret1126  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1127  ret <vscale x 4 x i32> %v1128}1129 1130define <vscale x 4 x i32> @vsaddu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1131; CHECK-LABEL: vsaddu_vx_nxv4i32:1132; CHECK:       # %bb.0:1133; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1134; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t1135; CHECK-NEXT:    ret1136  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01137  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1138  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1139  ret <vscale x 4 x i32> %v1140}1141 1142define <vscale x 4 x i32> @vsaddu_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1143; CHECK-LABEL: vsaddu_vx_nxv4i32_unmasked:1144; CHECK:       # %bb.0:1145; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1146; CHECK-NEXT:    vsaddu.vx v8, v8, a01147; CHECK-NEXT:    ret1148  %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01149  %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1150  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1151  ret <vscale x 4 x i32> %v1152}1153 1154define <vscale x 4 x i32> @vsaddu_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1155; CHECK-LABEL: vsaddu_vi_nxv4i32:1156; CHECK:       # %bb.0:1157; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1158; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1159; CHECK-NEXT:    ret1160  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> %m, i32 %evl)1161  ret <vscale x 4 x i32> %v1162}1163 1164define <vscale x 4 x i32> @vsaddu_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1165; CHECK-LABEL: vsaddu_vi_nxv4i32_unmasked:1166; CHECK:       # %bb.0:1167; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1168; CHECK-NEXT:    vsaddu.vi v8, v8, -11169; CHECK-NEXT:    ret1170  %v = call <vscale x 4 x i32> @llvm.vp.uadd.sat.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1171  ret <vscale x 4 x i32> %v1172}1173 1174define <vscale x 8 x i32> @vsaddu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1175; CHECK-LABEL: vsaddu_vv_nxv8i32:1176; CHECK:       # %bb.0:1177; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1178; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t1179; CHECK-NEXT:    ret1180  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1181  ret <vscale x 8 x i32> %v1182}1183 1184define <vscale x 8 x i32> @vsaddu_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1185; CHECK-LABEL: vsaddu_vv_nxv8i32_unmasked:1186; CHECK:       # %bb.0:1187; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1188; CHECK-NEXT:    vsaddu.vv v8, v8, v121189; CHECK-NEXT:    ret1190  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1191  ret <vscale x 8 x i32> %v1192}1193 1194define <vscale x 8 x i32> @vsaddu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1195; CHECK-LABEL: vsaddu_vx_nxv8i32:1196; CHECK:       # %bb.0:1197; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1198; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t1199; CHECK-NEXT:    ret1200  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01201  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1202  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1203  ret <vscale x 8 x i32> %v1204}1205 1206define <vscale x 8 x i32> @vsaddu_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1207; CHECK-LABEL: vsaddu_vx_nxv8i32_unmasked:1208; CHECK:       # %bb.0:1209; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1210; CHECK-NEXT:    vsaddu.vx v8, v8, a01211; CHECK-NEXT:    ret1212  %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01213  %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1214  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1215  ret <vscale x 8 x i32> %v1216}1217 1218define <vscale x 8 x i32> @vsaddu_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1219; CHECK-LABEL: vsaddu_vi_nxv8i32:1220; CHECK:       # %bb.0:1221; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1222; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1223; CHECK-NEXT:    ret1224  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> %m, i32 %evl)1225  ret <vscale x 8 x i32> %v1226}1227 1228define <vscale x 8 x i32> @vsaddu_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1229; CHECK-LABEL: vsaddu_vi_nxv8i32_unmasked:1230; CHECK:       # %bb.0:1231; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1232; CHECK-NEXT:    vsaddu.vi v8, v8, -11233; CHECK-NEXT:    ret1234  %v = call <vscale x 8 x i32> @llvm.vp.uadd.sat.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1235  ret <vscale x 8 x i32> %v1236}1237 1238define <vscale x 16 x i32> @vsaddu_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1239; CHECK-LABEL: vsaddu_vv_nxv16i32:1240; CHECK:       # %bb.0:1241; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1242; CHECK-NEXT:    vsaddu.vv v8, v8, v16, v0.t1243; CHECK-NEXT:    ret1244  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1245  ret <vscale x 16 x i32> %v1246}1247 1248define <vscale x 16 x i32> @vsaddu_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1249; CHECK-LABEL: vsaddu_vv_nxv16i32_unmasked:1250; CHECK:       # %bb.0:1251; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1252; CHECK-NEXT:    vsaddu.vv v8, v8, v161253; CHECK-NEXT:    ret1254  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1255  ret <vscale x 16 x i32> %v1256}1257 1258define <vscale x 16 x i32> @vsaddu_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1259; CHECK-LABEL: vsaddu_vx_nxv16i32:1260; CHECK:       # %bb.0:1261; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1262; CHECK-NEXT:    vsaddu.vx v8, v8, a0, v0.t1263; CHECK-NEXT:    ret1264  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01265  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1266  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1267  ret <vscale x 16 x i32> %v1268}1269 1270define <vscale x 16 x i32> @vsaddu_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1271; CHECK-LABEL: vsaddu_vx_nxv16i32_unmasked:1272; CHECK:       # %bb.0:1273; CHECK-NEXT:    vsetvli zero, a1, e32, m8, ta, ma1274; CHECK-NEXT:    vsaddu.vx v8, v8, a01275; CHECK-NEXT:    ret1276  %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01277  %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1278  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1279  ret <vscale x 16 x i32> %v1280}1281 1282define <vscale x 16 x i32> @vsaddu_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1283; CHECK-LABEL: vsaddu_vi_nxv16i32:1284; CHECK:       # %bb.0:1285; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1286; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1287; CHECK-NEXT:    ret1288  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> %m, i32 %evl)1289  ret <vscale x 16 x i32> %v1290}1291 1292define <vscale x 16 x i32> @vsaddu_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1293; CHECK-LABEL: vsaddu_vi_nxv16i32_unmasked:1294; CHECK:       # %bb.0:1295; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1296; CHECK-NEXT:    vsaddu.vi v8, v8, -11297; CHECK-NEXT:    ret1298  %v = call <vscale x 16 x i32> @llvm.vp.uadd.sat.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 -1), <vscale x 16 x i1> splat (i1 true), i32 %evl)1299  ret <vscale x 16 x i32> %v1300}1301 1302; Test that split-legalization works then the mask needs manual splitting.1303 1304define <vscale x 32 x i32> @vsaddu_vi_nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {1305; CHECK-LABEL: vsaddu_vi_nxv32i32:1306; CHECK:       # %bb.0:1307; CHECK-NEXT:    vsetvli a1, zero, e8, mf2, ta, ma1308; CHECK-NEXT:    vmv1r.v v24, v01309; CHECK-NEXT:    csrr a1, vlenb1310; CHECK-NEXT:    srli a2, a1, 21311; CHECK-NEXT:    slli a1, a1, 11312; CHECK-NEXT:    vslidedown.vx v0, v0, a21313; CHECK-NEXT:    sub a2, a0, a11314; CHECK-NEXT:    sltu a3, a0, a21315; CHECK-NEXT:    addi a3, a3, -11316; CHECK-NEXT:    and a2, a3, a21317; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1318; CHECK-NEXT:    vsaddu.vi v16, v16, -1, v0.t1319; CHECK-NEXT:    bltu a0, a1, .LBB118_21320; CHECK-NEXT:  # %bb.1:1321; CHECK-NEXT:    mv a0, a11322; CHECK-NEXT:  .LBB118_2:1323; CHECK-NEXT:    vmv1r.v v0, v241324; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1325; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1326; CHECK-NEXT:    ret1327  %v = call <vscale x 32 x i32> @llvm.vp.uadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> %m, i32 %evl)1328  ret <vscale x 32 x i32> %v1329}1330 1331define <vscale x 32 x i32> @vsaddu_vi_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 zeroext %evl) {1332; CHECK-LABEL: vsaddu_vi_nxv32i32_unmasked:1333; CHECK:       # %bb.0:1334; CHECK-NEXT:    csrr a1, vlenb1335; CHECK-NEXT:    slli a1, a1, 11336; CHECK-NEXT:    sub a2, a0, a11337; CHECK-NEXT:    sltu a3, a0, a21338; CHECK-NEXT:    addi a3, a3, -11339; CHECK-NEXT:    and a2, a3, a21340; CHECK-NEXT:    vsetvli zero, a2, e32, m8, ta, ma1341; CHECK-NEXT:    vsaddu.vi v16, v16, -11342; CHECK-NEXT:    bltu a0, a1, .LBB119_21343; CHECK-NEXT:  # %bb.1:1344; CHECK-NEXT:    mv a0, a11345; CHECK-NEXT:  .LBB119_2:1346; CHECK-NEXT:    vsetvli zero, a0, e32, m8, ta, ma1347; CHECK-NEXT:    vsaddu.vi v8, v8, -11348; CHECK-NEXT:    ret1349  %v = call <vscale x 32 x i32> @llvm.vp.uadd.sat.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> splat (i32 -1), <vscale x 32 x i1> splat (i1 true), i32 %evl)1350  ret <vscale x 32 x i32> %v1351}1352 1353define <vscale x 1 x i64> @vsaddu_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1354; CHECK-LABEL: vsaddu_vv_nxv1i64:1355; CHECK:       # %bb.0:1356; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1357; CHECK-NEXT:    vsaddu.vv v8, v8, v9, v0.t1358; CHECK-NEXT:    ret1359  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1360  ret <vscale x 1 x i64> %v1361}1362 1363define <vscale x 1 x i64> @vsaddu_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1364; CHECK-LABEL: vsaddu_vv_nxv1i64_unmasked:1365; CHECK:       # %bb.0:1366; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1367; CHECK-NEXT:    vsaddu.vv v8, v8, v91368; CHECK-NEXT:    ret1369  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1370  ret <vscale x 1 x i64> %v1371}1372 1373define <vscale x 1 x i64> @vsaddu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1374; RV32-LABEL: vsaddu_vx_nxv1i64:1375; RV32:       # %bb.0:1376; RV32-NEXT:    addi sp, sp, -161377; RV32-NEXT:    .cfi_def_cfa_offset 161378; RV32-NEXT:    sw a0, 8(sp)1379; RV32-NEXT:    sw a1, 12(sp)1380; RV32-NEXT:    addi a0, sp, 81381; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1382; RV32-NEXT:    vlse64.v v9, (a0), zero1383; RV32-NEXT:    vsaddu.vv v8, v8, v9, v0.t1384; RV32-NEXT:    addi sp, sp, 161385; RV32-NEXT:    .cfi_def_cfa_offset 01386; RV32-NEXT:    ret1387;1388; RV64-LABEL: vsaddu_vx_nxv1i64:1389; RV64:       # %bb.0:1390; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1391; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t1392; RV64-NEXT:    ret1393  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01394  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1395  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1396  ret <vscale x 1 x i64> %v1397}1398 1399define <vscale x 1 x i64> @vsaddu_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1400; RV32-LABEL: vsaddu_vx_nxv1i64_unmasked:1401; RV32:       # %bb.0:1402; RV32-NEXT:    addi sp, sp, -161403; RV32-NEXT:    .cfi_def_cfa_offset 161404; RV32-NEXT:    sw a0, 8(sp)1405; RV32-NEXT:    sw a1, 12(sp)1406; RV32-NEXT:    addi a0, sp, 81407; RV32-NEXT:    vsetvli zero, a2, e64, m1, ta, ma1408; RV32-NEXT:    vlse64.v v9, (a0), zero1409; RV32-NEXT:    vsaddu.vv v8, v8, v91410; RV32-NEXT:    addi sp, sp, 161411; RV32-NEXT:    .cfi_def_cfa_offset 01412; RV32-NEXT:    ret1413;1414; RV64-LABEL: vsaddu_vx_nxv1i64_unmasked:1415; RV64:       # %bb.0:1416; RV64-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1417; RV64-NEXT:    vsaddu.vx v8, v8, a01418; RV64-NEXT:    ret1419  %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01420  %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1421  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1422  ret <vscale x 1 x i64> %v1423}1424 1425define <vscale x 1 x i64> @vsaddu_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1426; CHECK-LABEL: vsaddu_vi_nxv1i64:1427; CHECK:       # %bb.0:1428; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1429; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1430; CHECK-NEXT:    ret1431  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> %m, i32 %evl)1432  ret <vscale x 1 x i64> %v1433}1434 1435define <vscale x 1 x i64> @vsaddu_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1436; CHECK-LABEL: vsaddu_vi_nxv1i64_unmasked:1437; CHECK:       # %bb.0:1438; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1439; CHECK-NEXT:    vsaddu.vi v8, v8, -11440; CHECK-NEXT:    ret1441  %v = call <vscale x 1 x i64> @llvm.vp.uadd.sat.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 -1), <vscale x 1 x i1> splat (i1 true), i32 %evl)1442  ret <vscale x 1 x i64> %v1443}1444 1445define <vscale x 2 x i64> @vsaddu_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1446; CHECK-LABEL: vsaddu_vv_nxv2i64:1447; CHECK:       # %bb.0:1448; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1449; CHECK-NEXT:    vsaddu.vv v8, v8, v10, v0.t1450; CHECK-NEXT:    ret1451  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1452  ret <vscale x 2 x i64> %v1453}1454 1455define <vscale x 2 x i64> @vsaddu_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1456; CHECK-LABEL: vsaddu_vv_nxv2i64_unmasked:1457; CHECK:       # %bb.0:1458; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1459; CHECK-NEXT:    vsaddu.vv v8, v8, v101460; CHECK-NEXT:    ret1461  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1462  ret <vscale x 2 x i64> %v1463}1464 1465define <vscale x 2 x i64> @vsaddu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1466; RV32-LABEL: vsaddu_vx_nxv2i64:1467; RV32:       # %bb.0:1468; RV32-NEXT:    addi sp, sp, -161469; RV32-NEXT:    .cfi_def_cfa_offset 161470; RV32-NEXT:    sw a0, 8(sp)1471; RV32-NEXT:    sw a1, 12(sp)1472; RV32-NEXT:    addi a0, sp, 81473; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1474; RV32-NEXT:    vlse64.v v10, (a0), zero1475; RV32-NEXT:    vsaddu.vv v8, v8, v10, v0.t1476; RV32-NEXT:    addi sp, sp, 161477; RV32-NEXT:    .cfi_def_cfa_offset 01478; RV32-NEXT:    ret1479;1480; RV64-LABEL: vsaddu_vx_nxv2i64:1481; RV64:       # %bb.0:1482; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1483; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t1484; RV64-NEXT:    ret1485  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01486  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1487  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1488  ret <vscale x 2 x i64> %v1489}1490 1491define <vscale x 2 x i64> @vsaddu_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1492; RV32-LABEL: vsaddu_vx_nxv2i64_unmasked:1493; RV32:       # %bb.0:1494; RV32-NEXT:    addi sp, sp, -161495; RV32-NEXT:    .cfi_def_cfa_offset 161496; RV32-NEXT:    sw a0, 8(sp)1497; RV32-NEXT:    sw a1, 12(sp)1498; RV32-NEXT:    addi a0, sp, 81499; RV32-NEXT:    vsetvli zero, a2, e64, m2, ta, ma1500; RV32-NEXT:    vlse64.v v10, (a0), zero1501; RV32-NEXT:    vsaddu.vv v8, v8, v101502; RV32-NEXT:    addi sp, sp, 161503; RV32-NEXT:    .cfi_def_cfa_offset 01504; RV32-NEXT:    ret1505;1506; RV64-LABEL: vsaddu_vx_nxv2i64_unmasked:1507; RV64:       # %bb.0:1508; RV64-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1509; RV64-NEXT:    vsaddu.vx v8, v8, a01510; RV64-NEXT:    ret1511  %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01512  %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1513  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1514  ret <vscale x 2 x i64> %v1515}1516 1517define <vscale x 2 x i64> @vsaddu_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1518; CHECK-LABEL: vsaddu_vi_nxv2i64:1519; CHECK:       # %bb.0:1520; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1521; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1522; CHECK-NEXT:    ret1523  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> %m, i32 %evl)1524  ret <vscale x 2 x i64> %v1525}1526 1527define <vscale x 2 x i64> @vsaddu_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1528; CHECK-LABEL: vsaddu_vi_nxv2i64_unmasked:1529; CHECK:       # %bb.0:1530; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1531; CHECK-NEXT:    vsaddu.vi v8, v8, -11532; CHECK-NEXT:    ret1533  %v = call <vscale x 2 x i64> @llvm.vp.uadd.sat.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i1> splat (i1 true), i32 %evl)1534  ret <vscale x 2 x i64> %v1535}1536 1537define <vscale x 4 x i64> @vsaddu_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1538; CHECK-LABEL: vsaddu_vv_nxv4i64:1539; CHECK:       # %bb.0:1540; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1541; CHECK-NEXT:    vsaddu.vv v8, v8, v12, v0.t1542; CHECK-NEXT:    ret1543  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1544  ret <vscale x 4 x i64> %v1545}1546 1547define <vscale x 4 x i64> @vsaddu_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1548; CHECK-LABEL: vsaddu_vv_nxv4i64_unmasked:1549; CHECK:       # %bb.0:1550; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1551; CHECK-NEXT:    vsaddu.vv v8, v8, v121552; CHECK-NEXT:    ret1553  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1554  ret <vscale x 4 x i64> %v1555}1556 1557define <vscale x 4 x i64> @vsaddu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1558; RV32-LABEL: vsaddu_vx_nxv4i64:1559; RV32:       # %bb.0:1560; RV32-NEXT:    addi sp, sp, -161561; RV32-NEXT:    .cfi_def_cfa_offset 161562; RV32-NEXT:    sw a0, 8(sp)1563; RV32-NEXT:    sw a1, 12(sp)1564; RV32-NEXT:    addi a0, sp, 81565; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1566; RV32-NEXT:    vlse64.v v12, (a0), zero1567; RV32-NEXT:    vsaddu.vv v8, v8, v12, v0.t1568; RV32-NEXT:    addi sp, sp, 161569; RV32-NEXT:    .cfi_def_cfa_offset 01570; RV32-NEXT:    ret1571;1572; RV64-LABEL: vsaddu_vx_nxv4i64:1573; RV64:       # %bb.0:1574; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1575; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t1576; RV64-NEXT:    ret1577  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01578  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1579  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1580  ret <vscale x 4 x i64> %v1581}1582 1583define <vscale x 4 x i64> @vsaddu_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1584; RV32-LABEL: vsaddu_vx_nxv4i64_unmasked:1585; RV32:       # %bb.0:1586; RV32-NEXT:    addi sp, sp, -161587; RV32-NEXT:    .cfi_def_cfa_offset 161588; RV32-NEXT:    sw a0, 8(sp)1589; RV32-NEXT:    sw a1, 12(sp)1590; RV32-NEXT:    addi a0, sp, 81591; RV32-NEXT:    vsetvli zero, a2, e64, m4, ta, ma1592; RV32-NEXT:    vlse64.v v12, (a0), zero1593; RV32-NEXT:    vsaddu.vv v8, v8, v121594; RV32-NEXT:    addi sp, sp, 161595; RV32-NEXT:    .cfi_def_cfa_offset 01596; RV32-NEXT:    ret1597;1598; RV64-LABEL: vsaddu_vx_nxv4i64_unmasked:1599; RV64:       # %bb.0:1600; RV64-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1601; RV64-NEXT:    vsaddu.vx v8, v8, a01602; RV64-NEXT:    ret1603  %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01604  %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1605  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1606  ret <vscale x 4 x i64> %v1607}1608 1609define <vscale x 4 x i64> @vsaddu_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1610; CHECK-LABEL: vsaddu_vi_nxv4i64:1611; CHECK:       # %bb.0:1612; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1613; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1614; CHECK-NEXT:    ret1615  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> %m, i32 %evl)1616  ret <vscale x 4 x i64> %v1617}1618 1619define <vscale x 4 x i64> @vsaddu_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1620; CHECK-LABEL: vsaddu_vi_nxv4i64_unmasked:1621; CHECK:       # %bb.0:1622; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1623; CHECK-NEXT:    vsaddu.vi v8, v8, -11624; CHECK-NEXT:    ret1625  %v = call <vscale x 4 x i64> @llvm.vp.uadd.sat.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 -1), <vscale x 4 x i1> splat (i1 true), i32 %evl)1626  ret <vscale x 4 x i64> %v1627}1628 1629define <vscale x 8 x i64> @vsaddu_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1630; CHECK-LABEL: vsaddu_vv_nxv8i64:1631; CHECK:       # %bb.0:1632; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1633; CHECK-NEXT:    vsaddu.vv v8, v8, v16, v0.t1634; CHECK-NEXT:    ret1635  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1636  ret <vscale x 8 x i64> %v1637}1638 1639define <vscale x 8 x i64> @vsaddu_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1640; CHECK-LABEL: vsaddu_vv_nxv8i64_unmasked:1641; CHECK:       # %bb.0:1642; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1643; CHECK-NEXT:    vsaddu.vv v8, v8, v161644; CHECK-NEXT:    ret1645  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1646  ret <vscale x 8 x i64> %v1647}1648 1649define <vscale x 8 x i64> @vsaddu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1650; RV32-LABEL: vsaddu_vx_nxv8i64:1651; RV32:       # %bb.0:1652; RV32-NEXT:    addi sp, sp, -161653; RV32-NEXT:    .cfi_def_cfa_offset 161654; RV32-NEXT:    sw a0, 8(sp)1655; RV32-NEXT:    sw a1, 12(sp)1656; RV32-NEXT:    addi a0, sp, 81657; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1658; RV32-NEXT:    vlse64.v v16, (a0), zero1659; RV32-NEXT:    vsaddu.vv v8, v8, v16, v0.t1660; RV32-NEXT:    addi sp, sp, 161661; RV32-NEXT:    .cfi_def_cfa_offset 01662; RV32-NEXT:    ret1663;1664; RV64-LABEL: vsaddu_vx_nxv8i64:1665; RV64:       # %bb.0:1666; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1667; RV64-NEXT:    vsaddu.vx v8, v8, a0, v0.t1668; RV64-NEXT:    ret1669  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01670  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1671  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1672  ret <vscale x 8 x i64> %v1673}1674 1675define <vscale x 8 x i64> @vsaddu_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1676; RV32-LABEL: vsaddu_vx_nxv8i64_unmasked:1677; RV32:       # %bb.0:1678; RV32-NEXT:    addi sp, sp, -161679; RV32-NEXT:    .cfi_def_cfa_offset 161680; RV32-NEXT:    sw a0, 8(sp)1681; RV32-NEXT:    sw a1, 12(sp)1682; RV32-NEXT:    addi a0, sp, 81683; RV32-NEXT:    vsetvli zero, a2, e64, m8, ta, ma1684; RV32-NEXT:    vlse64.v v16, (a0), zero1685; RV32-NEXT:    vsaddu.vv v8, v8, v161686; RV32-NEXT:    addi sp, sp, 161687; RV32-NEXT:    .cfi_def_cfa_offset 01688; RV32-NEXT:    ret1689;1690; RV64-LABEL: vsaddu_vx_nxv8i64_unmasked:1691; RV64:       # %bb.0:1692; RV64-NEXT:    vsetvli zero, a1, e64, m8, ta, ma1693; RV64-NEXT:    vsaddu.vx v8, v8, a01694; RV64-NEXT:    ret1695  %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01696  %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1697  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1698  ret <vscale x 8 x i64> %v1699}1700 1701define <vscale x 8 x i64> @vsaddu_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1702; CHECK-LABEL: vsaddu_vi_nxv8i64:1703; CHECK:       # %bb.0:1704; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1705; CHECK-NEXT:    vsaddu.vi v8, v8, -1, v0.t1706; CHECK-NEXT:    ret1707  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> %m, i32 %evl)1708  ret <vscale x 8 x i64> %v1709}1710 1711define <vscale x 8 x i64> @vsaddu_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1712; CHECK-LABEL: vsaddu_vi_nxv8i64_unmasked:1713; CHECK:       # %bb.0:1714; CHECK-NEXT:    vsetvli zero, a0, e64, m8, ta, ma1715; CHECK-NEXT:    vsaddu.vi v8, v8, -11716; CHECK-NEXT:    ret1717  %v = call <vscale x 8 x i64> @llvm.vp.uadd.sat.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 -1), <vscale x 8 x i1> splat (i1 true), i32 %evl)1718  ret <vscale x 8 x i64> %v1719}1720