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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i8_nxv1i8_nxv1i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma11; CHECK-NEXT: vsbc.vvm v8, v8, v9, v012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.nxv1i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i8> %0,17 <vscale x 1 x i8> %1,18 <vscale x 1 x i1> %2,19 iXLen %3)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 2 x i8> @intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {25; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i8_nxv2i8_nxv2i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma28; CHECK-NEXT: vsbc.vvm v8, v8, v9, v029; CHECK-NEXT: ret30entry:31 %a = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.nxv2i8(32 <vscale x 2 x i8> poison,33 <vscale x 2 x i8> %0,34 <vscale x 2 x i8> %1,35 <vscale x 2 x i1> %2,36 iXLen %3)37 38 ret <vscale x 2 x i8> %a39}40 41define <vscale x 4 x i8> @intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {42; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i8_nxv4i8_nxv4i8:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma45; CHECK-NEXT: vsbc.vvm v8, v8, v9, v046; CHECK-NEXT: ret47entry:48 %a = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.nxv4i8(49 <vscale x 4 x i8> poison,50 <vscale x 4 x i8> %0,51 <vscale x 4 x i8> %1,52 <vscale x 4 x i1> %2,53 iXLen %3)54 55 ret <vscale x 4 x i8> %a56}57 58define <vscale x 8 x i8> @intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {59; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i8_nxv8i8_nxv8i8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma62; CHECK-NEXT: vsbc.vvm v8, v8, v9, v063; CHECK-NEXT: ret64entry:65 %a = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.nxv8i8(66 <vscale x 8 x i8> poison,67 <vscale x 8 x i8> %0,68 <vscale x 8 x i8> %1,69 <vscale x 8 x i1> %2,70 iXLen %3)71 72 ret <vscale x 8 x i8> %a73}74 75define <vscale x 16 x i8> @intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {76; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i8_nxv16i8_nxv16i8:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma79; CHECK-NEXT: vsbc.vvm v8, v8, v10, v080; CHECK-NEXT: ret81entry:82 %a = call <vscale x 16 x i8> @llvm.riscv.vsbc.nxv16i8.nxv16i8(83 <vscale x 16 x i8> poison,84 <vscale x 16 x i8> %0,85 <vscale x 16 x i8> %1,86 <vscale x 16 x i1> %2,87 iXLen %3)88 89 ret <vscale x 16 x i8> %a90}91 92define <vscale x 32 x i8> @intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {93; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i8_nxv32i8_nxv32i8:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma96; CHECK-NEXT: vsbc.vvm v8, v8, v12, v097; CHECK-NEXT: ret98entry:99 %a = call <vscale x 32 x i8> @llvm.riscv.vsbc.nxv32i8.nxv32i8(100 <vscale x 32 x i8> poison,101 <vscale x 32 x i8> %0,102 <vscale x 32 x i8> %1,103 <vscale x 32 x i1> %2,104 iXLen %3)105 106 ret <vscale x 32 x i8> %a107}108 109define <vscale x 64 x i8> @intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {110; CHECK-LABEL: intrinsic_vsbc_vvm_nxv64i8_nxv64i8_nxv64i8:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma113; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0114; CHECK-NEXT: ret115entry:116 %a = call <vscale x 64 x i8> @llvm.riscv.vsbc.nxv64i8.nxv64i8(117 <vscale x 64 x i8> poison,118 <vscale x 64 x i8> %0,119 <vscale x 64 x i8> %1,120 <vscale x 64 x i1> %2,121 iXLen %3)122 123 ret <vscale x 64 x i8> %a124}125 126define <vscale x 1 x i16> @intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {127; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i16_nxv1i16_nxv1i16:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma130; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 1 x i16> @llvm.riscv.vsbc.nxv1i16.nxv1i16(134 <vscale x 1 x i16> poison,135 <vscale x 1 x i16> %0,136 <vscale x 1 x i16> %1,137 <vscale x 1 x i1> %2,138 iXLen %3)139 140 ret <vscale x 1 x i16> %a141}142 143define <vscale x 2 x i16> @intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {144; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i16_nxv2i16_nxv2i16:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma147; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0148; CHECK-NEXT: ret149entry:150 %a = call <vscale x 2 x i16> @llvm.riscv.vsbc.nxv2i16.nxv2i16(151 <vscale x 2 x i16> poison,152 <vscale x 2 x i16> %0,153 <vscale x 2 x i16> %1,154 <vscale x 2 x i1> %2,155 iXLen %3)156 157 ret <vscale x 2 x i16> %a158}159 160define <vscale x 4 x i16> @intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {161; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i16_nxv4i16_nxv4i16:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma164; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 4 x i16> @llvm.riscv.vsbc.nxv4i16.nxv4i16(168 <vscale x 4 x i16> poison,169 <vscale x 4 x i16> %0,170 <vscale x 4 x i16> %1,171 <vscale x 4 x i1> %2,172 iXLen %3)173 174 ret <vscale x 4 x i16> %a175}176 177define <vscale x 8 x i16> @intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {178; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i16_nxv8i16_nxv8i16:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma181; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0182; CHECK-NEXT: ret183entry:184 %a = call <vscale x 8 x i16> @llvm.riscv.vsbc.nxv8i16.nxv8i16(185 <vscale x 8 x i16> poison,186 <vscale x 8 x i16> %0,187 <vscale x 8 x i16> %1,188 <vscale x 8 x i1> %2,189 iXLen %3)190 191 ret <vscale x 8 x i16> %a192}193 194define <vscale x 16 x i16> @intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {195; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i16_nxv16i16_nxv16i16:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma198; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 16 x i16> @llvm.riscv.vsbc.nxv16i16.nxv16i16(202 <vscale x 16 x i16> poison,203 <vscale x 16 x i16> %0,204 <vscale x 16 x i16> %1,205 <vscale x 16 x i1> %2,206 iXLen %3)207 208 ret <vscale x 16 x i16> %a209}210 211define <vscale x 32 x i16> @intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {212; CHECK-LABEL: intrinsic_vsbc_vvm_nxv32i16_nxv32i16_nxv32i16:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma215; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0216; CHECK-NEXT: ret217entry:218 %a = call <vscale x 32 x i16> @llvm.riscv.vsbc.nxv32i16.nxv32i16(219 <vscale x 32 x i16> poison,220 <vscale x 32 x i16> %0,221 <vscale x 32 x i16> %1,222 <vscale x 32 x i1> %2,223 iXLen %3)224 225 ret <vscale x 32 x i16> %a226}227 228define <vscale x 1 x i32> @intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {229; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i32_nxv1i32_nxv1i32:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma232; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 1 x i32> @llvm.riscv.vsbc.nxv1i32.nxv1i32(236 <vscale x 1 x i32> poison,237 <vscale x 1 x i32> %0,238 <vscale x 1 x i32> %1,239 <vscale x 1 x i1> %2,240 iXLen %3)241 242 ret <vscale x 1 x i32> %a243}244 245define <vscale x 2 x i32> @intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {246; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i32_nxv2i32_nxv2i32:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma249; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0250; CHECK-NEXT: ret251entry:252 %a = call <vscale x 2 x i32> @llvm.riscv.vsbc.nxv2i32.nxv2i32(253 <vscale x 2 x i32> poison,254 <vscale x 2 x i32> %0,255 <vscale x 2 x i32> %1,256 <vscale x 2 x i1> %2,257 iXLen %3)258 259 ret <vscale x 2 x i32> %a260}261 262define <vscale x 4 x i32> @intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {263; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i32_nxv4i32_nxv4i32:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma266; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 4 x i32> @llvm.riscv.vsbc.nxv4i32.nxv4i32(270 <vscale x 4 x i32> poison,271 <vscale x 4 x i32> %0,272 <vscale x 4 x i32> %1,273 <vscale x 4 x i1> %2,274 iXLen %3)275 276 ret <vscale x 4 x i32> %a277}278 279define <vscale x 8 x i32> @intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i32_nxv8i32_nxv8i32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma283; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 8 x i32> @llvm.riscv.vsbc.nxv8i32.nxv8i32(287 <vscale x 8 x i32> poison,288 <vscale x 8 x i32> %0,289 <vscale x 8 x i32> %1,290 <vscale x 8 x i1> %2,291 iXLen %3)292 293 ret <vscale x 8 x i32> %a294}295 296define <vscale x 16 x i32> @intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {297; CHECK-LABEL: intrinsic_vsbc_vvm_nxv16i32_nxv16i32_nxv16i32:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma300; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 16 x i32> @llvm.riscv.vsbc.nxv16i32.nxv16i32(304 <vscale x 16 x i32> poison,305 <vscale x 16 x i32> %0,306 <vscale x 16 x i32> %1,307 <vscale x 16 x i1> %2,308 iXLen %3)309 310 ret <vscale x 16 x i32> %a311}312 313define <vscale x 1 x i64> @intrinsic_vsbc_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {314; CHECK-LABEL: intrinsic_vsbc_vvm_nxv1i64_nxv1i64_nxv1i64:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma317; CHECK-NEXT: vsbc.vvm v8, v8, v9, v0318; CHECK-NEXT: ret319entry:320 %a = call <vscale x 1 x i64> @llvm.riscv.vsbc.nxv1i64.nxv1i64(321 <vscale x 1 x i64> poison,322 <vscale x 1 x i64> %0,323 <vscale x 1 x i64> %1,324 <vscale x 1 x i1> %2,325 iXLen %3)326 327 ret <vscale x 1 x i64> %a328}329 330define <vscale x 2 x i64> @intrinsic_vsbc_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {331; CHECK-LABEL: intrinsic_vsbc_vvm_nxv2i64_nxv2i64_nxv2i64:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma334; CHECK-NEXT: vsbc.vvm v8, v8, v10, v0335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 2 x i64> @llvm.riscv.vsbc.nxv2i64.nxv2i64(338 <vscale x 2 x i64> poison,339 <vscale x 2 x i64> %0,340 <vscale x 2 x i64> %1,341 <vscale x 2 x i1> %2,342 iXLen %3)343 344 ret <vscale x 2 x i64> %a345}346 347define <vscale x 4 x i64> @intrinsic_vsbc_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {348; CHECK-LABEL: intrinsic_vsbc_vvm_nxv4i64_nxv4i64_nxv4i64:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma351; CHECK-NEXT: vsbc.vvm v8, v8, v12, v0352; CHECK-NEXT: ret353entry:354 %a = call <vscale x 4 x i64> @llvm.riscv.vsbc.nxv4i64.nxv4i64(355 <vscale x 4 x i64> poison,356 <vscale x 4 x i64> %0,357 <vscale x 4 x i64> %1,358 <vscale x 4 x i1> %2,359 iXLen %3)360 361 ret <vscale x 4 x i64> %a362}363 364define <vscale x 8 x i64> @intrinsic_vsbc_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {365; CHECK-LABEL: intrinsic_vsbc_vvm_nxv8i64_nxv8i64_nxv8i64:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma368; CHECK-NEXT: vsbc.vvm v8, v8, v16, v0369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 8 x i64> @llvm.riscv.vsbc.nxv8i64.nxv8i64(372 <vscale x 8 x i64> poison,373 <vscale x 8 x i64> %0,374 <vscale x 8 x i64> %1,375 <vscale x 8 x i1> %2,376 iXLen %3)377 378 ret <vscale x 8 x i64> %a379}380 381define <vscale x 1 x i8> @intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {382; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i8_nxv1i8_i8:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma385; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0386; CHECK-NEXT: ret387entry:388 %a = call <vscale x 1 x i8> @llvm.riscv.vsbc.nxv1i8.i8(389 <vscale x 1 x i8> poison,390 <vscale x 1 x i8> %0,391 i8 %1,392 <vscale x 1 x i1> %2,393 iXLen %3)394 395 ret <vscale x 1 x i8> %a396}397 398define <vscale x 2 x i8> @intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {399; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i8_nxv2i8_i8:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma402; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 2 x i8> @llvm.riscv.vsbc.nxv2i8.i8(406 <vscale x 2 x i8> poison,407 <vscale x 2 x i8> %0,408 i8 %1,409 <vscale x 2 x i1> %2,410 iXLen %3)411 412 ret <vscale x 2 x i8> %a413}414 415define <vscale x 4 x i8> @intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {416; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i8_nxv4i8_i8:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma419; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0420; CHECK-NEXT: ret421entry:422 %a = call <vscale x 4 x i8> @llvm.riscv.vsbc.nxv4i8.i8(423 <vscale x 4 x i8> poison,424 <vscale x 4 x i8> %0,425 i8 %1,426 <vscale x 4 x i1> %2,427 iXLen %3)428 429 ret <vscale x 4 x i8> %a430}431 432define <vscale x 8 x i8> @intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {433; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i8_nxv8i8_i8:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma436; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0437; CHECK-NEXT: ret438entry:439 %a = call <vscale x 8 x i8> @llvm.riscv.vsbc.nxv8i8.i8(440 <vscale x 8 x i8> poison,441 <vscale x 8 x i8> %0,442 i8 %1,443 <vscale x 8 x i1> %2,444 iXLen %3)445 446 ret <vscale x 8 x i8> %a447}448 449define <vscale x 16 x i8> @intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {450; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i8_nxv16i8_i8:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma453; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0454; CHECK-NEXT: ret455entry:456 %a = call <vscale x 16 x i8> @llvm.riscv.vsbc.nxv16i8.i8(457 <vscale x 16 x i8> poison,458 <vscale x 16 x i8> %0,459 i8 %1,460 <vscale x 16 x i1> %2,461 iXLen %3)462 463 ret <vscale x 16 x i8> %a464}465 466define <vscale x 32 x i8> @intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {467; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i8_nxv32i8_i8:468; CHECK: # %bb.0: # %entry469; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma470; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0471; CHECK-NEXT: ret472entry:473 %a = call <vscale x 32 x i8> @llvm.riscv.vsbc.nxv32i8.i8(474 <vscale x 32 x i8> poison,475 <vscale x 32 x i8> %0,476 i8 %1,477 <vscale x 32 x i1> %2,478 iXLen %3)479 480 ret <vscale x 32 x i8> %a481}482 483define <vscale x 64 x i8> @intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {484; CHECK-LABEL: intrinsic_vsbc_vxm_nxv64i8_nxv64i8_i8:485; CHECK: # %bb.0: # %entry486; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma487; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0488; CHECK-NEXT: ret489entry:490 %a = call <vscale x 64 x i8> @llvm.riscv.vsbc.nxv64i8.i8(491 <vscale x 64 x i8> poison,492 <vscale x 64 x i8> %0,493 i8 %1,494 <vscale x 64 x i1> %2,495 iXLen %3)496 497 ret <vscale x 64 x i8> %a498}499 500define <vscale x 1 x i16> @intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {501; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i16_nxv1i16_i16:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma504; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 1 x i16> @llvm.riscv.vsbc.nxv1i16.i16(508 <vscale x 1 x i16> poison,509 <vscale x 1 x i16> %0,510 i16 %1,511 <vscale x 1 x i1> %2,512 iXLen %3)513 514 ret <vscale x 1 x i16> %a515}516 517define <vscale x 2 x i16> @intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {518; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i16_nxv2i16_i16:519; CHECK: # %bb.0: # %entry520; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma521; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0522; CHECK-NEXT: ret523entry:524 %a = call <vscale x 2 x i16> @llvm.riscv.vsbc.nxv2i16.i16(525 <vscale x 2 x i16> poison,526 <vscale x 2 x i16> %0,527 i16 %1,528 <vscale x 2 x i1> %2,529 iXLen %3)530 531 ret <vscale x 2 x i16> %a532}533 534define <vscale x 4 x i16> @intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {535; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i16_nxv4i16_i16:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma538; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0539; CHECK-NEXT: ret540entry:541 %a = call <vscale x 4 x i16> @llvm.riscv.vsbc.nxv4i16.i16(542 <vscale x 4 x i16> poison,543 <vscale x 4 x i16> %0,544 i16 %1,545 <vscale x 4 x i1> %2,546 iXLen %3)547 548 ret <vscale x 4 x i16> %a549}550 551define <vscale x 8 x i16> @intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {552; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i16_nxv8i16_i16:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma555; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 8 x i16> @llvm.riscv.vsbc.nxv8i16.i16(559 <vscale x 8 x i16> poison,560 <vscale x 8 x i16> %0,561 i16 %1,562 <vscale x 8 x i1> %2,563 iXLen %3)564 565 ret <vscale x 8 x i16> %a566}567 568define <vscale x 16 x i16> @intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {569; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i16_nxv16i16_i16:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma572; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 16 x i16> @llvm.riscv.vsbc.nxv16i16.i16(576 <vscale x 16 x i16> poison,577 <vscale x 16 x i16> %0,578 i16 %1,579 <vscale x 16 x i1> %2,580 iXLen %3)581 582 ret <vscale x 16 x i16> %a583}584 585define <vscale x 32 x i16> @intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {586; CHECK-LABEL: intrinsic_vsbc_vxm_nxv32i16_nxv32i16_i16:587; CHECK: # %bb.0: # %entry588; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma589; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0590; CHECK-NEXT: ret591entry:592 %a = call <vscale x 32 x i16> @llvm.riscv.vsbc.nxv32i16.i16(593 <vscale x 32 x i16> poison,594 <vscale x 32 x i16> %0,595 i16 %1,596 <vscale x 32 x i1> %2,597 iXLen %3)598 599 ret <vscale x 32 x i16> %a600}601 602define <vscale x 1 x i32> @intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {603; CHECK-LABEL: intrinsic_vsbc_vxm_nxv1i32_nxv1i32_i32:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma606; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0607; CHECK-NEXT: ret608entry:609 %a = call <vscale x 1 x i32> @llvm.riscv.vsbc.nxv1i32.i32(610 <vscale x 1 x i32> poison,611 <vscale x 1 x i32> %0,612 i32 %1,613 <vscale x 1 x i1> %2,614 iXLen %3)615 616 ret <vscale x 1 x i32> %a617}618 619define <vscale x 2 x i32> @intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {620; CHECK-LABEL: intrinsic_vsbc_vxm_nxv2i32_nxv2i32_i32:621; CHECK: # %bb.0: # %entry622; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma623; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0624; CHECK-NEXT: ret625entry:626 %a = call <vscale x 2 x i32> @llvm.riscv.vsbc.nxv2i32.i32(627 <vscale x 2 x i32> poison,628 <vscale x 2 x i32> %0,629 i32 %1,630 <vscale x 2 x i1> %2,631 iXLen %3)632 633 ret <vscale x 2 x i32> %a634}635 636define <vscale x 4 x i32> @intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {637; CHECK-LABEL: intrinsic_vsbc_vxm_nxv4i32_nxv4i32_i32:638; CHECK: # %bb.0: # %entry639; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma640; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0641; CHECK-NEXT: ret642entry:643 %a = call <vscale x 4 x i32> @llvm.riscv.vsbc.nxv4i32.i32(644 <vscale x 4 x i32> poison,645 <vscale x 4 x i32> %0,646 i32 %1,647 <vscale x 4 x i1> %2,648 iXLen %3)649 650 ret <vscale x 4 x i32> %a651}652 653define <vscale x 8 x i32> @intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {654; CHECK-LABEL: intrinsic_vsbc_vxm_nxv8i32_nxv8i32_i32:655; CHECK: # %bb.0: # %entry656; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma657; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0658; CHECK-NEXT: ret659entry:660 %a = call <vscale x 8 x i32> @llvm.riscv.vsbc.nxv8i32.i32(661 <vscale x 8 x i32> poison,662 <vscale x 8 x i32> %0,663 i32 %1,664 <vscale x 8 x i1> %2,665 iXLen %3)666 667 ret <vscale x 8 x i32> %a668}669 670define <vscale x 16 x i32> @intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {671; CHECK-LABEL: intrinsic_vsbc_vxm_nxv16i32_nxv16i32_i32:672; CHECK: # %bb.0: # %entry673; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma674; CHECK-NEXT: vsbc.vxm v8, v8, a0, v0675; CHECK-NEXT: ret676entry:677 %a = call <vscale x 16 x i32> @llvm.riscv.vsbc.nxv16i32.i32(678 <vscale x 16 x i32> poison,679 <vscale x 16 x i32> %0,680 i32 %1,681 <vscale x 16 x i1> %2,682 iXLen %3)683 684 ret <vscale x 16 x i32> %a685}686 687define <vscale x 1 x i64> @intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {688; RV32-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64:689; RV32: # %bb.0: # %entry690; RV32-NEXT: addi sp, sp, -16691; RV32-NEXT: sw a0, 8(sp)692; RV32-NEXT: sw a1, 12(sp)693; RV32-NEXT: addi a0, sp, 8694; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma695; RV32-NEXT: vlse64.v v9, (a0), zero696; RV32-NEXT: vsbc.vvm v8, v8, v9, v0697; RV32-NEXT: addi sp, sp, 16698; RV32-NEXT: ret699;700; RV64-LABEL: intrinsic_vsbc_vxm_nxv1i64_nxv1i64_i64:701; RV64: # %bb.0: # %entry702; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma703; RV64-NEXT: vsbc.vxm v8, v8, a0, v0704; RV64-NEXT: ret705entry:706 %a = call <vscale x 1 x i64> @llvm.riscv.vsbc.nxv1i64.i64(707 <vscale x 1 x i64> poison,708 <vscale x 1 x i64> %0,709 i64 %1,710 <vscale x 1 x i1> %2,711 iXLen %3)712 713 ret <vscale x 1 x i64> %a714}715 716define <vscale x 2 x i64> @intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {717; RV32-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64:718; RV32: # %bb.0: # %entry719; RV32-NEXT: addi sp, sp, -16720; RV32-NEXT: sw a0, 8(sp)721; RV32-NEXT: sw a1, 12(sp)722; RV32-NEXT: addi a0, sp, 8723; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma724; RV32-NEXT: vlse64.v v10, (a0), zero725; RV32-NEXT: vsbc.vvm v8, v8, v10, v0726; RV32-NEXT: addi sp, sp, 16727; RV32-NEXT: ret728;729; RV64-LABEL: intrinsic_vsbc_vxm_nxv2i64_nxv2i64_i64:730; RV64: # %bb.0: # %entry731; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma732; RV64-NEXT: vsbc.vxm v8, v8, a0, v0733; RV64-NEXT: ret734entry:735 %a = call <vscale x 2 x i64> @llvm.riscv.vsbc.nxv2i64.i64(736 <vscale x 2 x i64> poison,737 <vscale x 2 x i64> %0,738 i64 %1,739 <vscale x 2 x i1> %2,740 iXLen %3)741 742 ret <vscale x 2 x i64> %a743}744 745define <vscale x 4 x i64> @intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {746; RV32-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64:747; RV32: # %bb.0: # %entry748; RV32-NEXT: addi sp, sp, -16749; RV32-NEXT: sw a0, 8(sp)750; RV32-NEXT: sw a1, 12(sp)751; RV32-NEXT: addi a0, sp, 8752; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma753; RV32-NEXT: vlse64.v v12, (a0), zero754; RV32-NEXT: vsbc.vvm v8, v8, v12, v0755; RV32-NEXT: addi sp, sp, 16756; RV32-NEXT: ret757;758; RV64-LABEL: intrinsic_vsbc_vxm_nxv4i64_nxv4i64_i64:759; RV64: # %bb.0: # %entry760; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma761; RV64-NEXT: vsbc.vxm v8, v8, a0, v0762; RV64-NEXT: ret763entry:764 %a = call <vscale x 4 x i64> @llvm.riscv.vsbc.nxv4i64.i64(765 <vscale x 4 x i64> poison,766 <vscale x 4 x i64> %0,767 i64 %1,768 <vscale x 4 x i1> %2,769 iXLen %3)770 771 ret <vscale x 4 x i64> %a772}773 774define <vscale x 8 x i64> @intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {775; RV32-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64:776; RV32: # %bb.0: # %entry777; RV32-NEXT: addi sp, sp, -16778; RV32-NEXT: sw a0, 8(sp)779; RV32-NEXT: sw a1, 12(sp)780; RV32-NEXT: addi a0, sp, 8781; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma782; RV32-NEXT: vlse64.v v16, (a0), zero783; RV32-NEXT: vsbc.vvm v8, v8, v16, v0784; RV32-NEXT: addi sp, sp, 16785; RV32-NEXT: ret786;787; RV64-LABEL: intrinsic_vsbc_vxm_nxv8i64_nxv8i64_i64:788; RV64: # %bb.0: # %entry789; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma790; RV64-NEXT: vsbc.vxm v8, v8, a0, v0791; RV64-NEXT: ret792entry:793 %a = call <vscale x 8 x i64> @llvm.riscv.vsbc.nxv8i64.i64(794 <vscale x 8 x i64> poison,795 <vscale x 8 x i64> %0,796 i64 %1,797 <vscale x 8 x i1> %2,798 iXLen %3)799 800 ret <vscale x 8 x i64> %a801}802