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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+zve64x,+m -verify-machineinstrs < %s | FileCheck %s4 5define i64 @vscale_lshr(i64 %TC) {6; CHECK-LABEL: vscale_lshr:7; CHECK: # %bb.0:8; CHECK-NEXT: csrr a1, vlenb9; CHECK-NEXT: srli a1, a1, 610; CHECK-NEXT: addi a1, a1, -111; CHECK-NEXT: and a0, a0, a112; CHECK-NEXT: ret13 %vscale = call i64 @llvm.vscale.i64()14 %shifted = lshr i64 %vscale, 315 %urem = urem i64 %TC, %shifted16 ret i64 %urem17}18 19define i64 @vscale(i64 %TC) {20; CHECK-LABEL: vscale:21; CHECK: # %bb.0:22; CHECK-NEXT: csrr a1, vlenb23; CHECK-NEXT: srli a1, a1, 324; CHECK-NEXT: addi a1, a1, -125; CHECK-NEXT: and a0, a0, a126; CHECK-NEXT: ret27 %vscale = call i64 @llvm.vscale.i64()28 %urem = urem i64 %TC, %vscale29 ret i64 %urem30}31 32define i64 @vscale_shl(i64 %TC) {33; CHECK-LABEL: vscale_shl:34; CHECK: # %bb.0:35; CHECK-NEXT: csrr a1, vlenb36; CHECK-NEXT: addi a1, a1, -137; CHECK-NEXT: and a0, a0, a138; CHECK-NEXT: ret39 %vscale = call i64 @llvm.vscale.i64()40 %shifted = shl i64 %vscale, 341 %urem = urem i64 %TC, %shifted42 ret i64 %urem43}44 45define i64 @TC_minus_rem(i64 %TC) {46; CHECK-LABEL: TC_minus_rem:47; CHECK: # %bb.0:48; CHECK-NEXT: csrr a1, vlenb49; CHECK-NEXT: srli a1, a1, 350; CHECK-NEXT: neg a1, a151; CHECK-NEXT: and a0, a0, a152; CHECK-NEXT: ret53 %vscale = call i64 @llvm.vscale.i64()54 %urem = urem i64 %TC, %vscale55 %VTC = sub i64 %TC, %urem56 ret i64 %VTC57}58 59define i64 @TC_minus_rem_shl(i64 %TC) {60; CHECK-LABEL: TC_minus_rem_shl:61; CHECK: # %bb.0:62; CHECK-NEXT: csrr a1, vlenb63; CHECK-NEXT: neg a1, a164; CHECK-NEXT: and a0, a0, a165; CHECK-NEXT: ret66 %vscale = call i64 @llvm.vscale.i64()67 %shifted = shl i64 %vscale, 368 %urem = urem i64 %TC, %shifted69 %VTC = sub i64 %TC, %urem70 ret i64 %VTC71}72 73define i64 @con1024_minus_rem() {74; CHECK-LABEL: con1024_minus_rem:75; CHECK: # %bb.0:76; CHECK-NEXT: csrr a0, vlenb77; CHECK-NEXT: srli a0, a0, 378; CHECK-NEXT: neg a0, a079; CHECK-NEXT: andi a0, a0, 102480; CHECK-NEXT: ret81 %vscale = call i64 @llvm.vscale.i64()82 %urem = urem i64 1024, %vscale83 %VTC = sub i64 1024, %urem84 ret i64 %VTC85}86 87; Maximum VLEN=64k implies Maximum vscale=1024.88; TODO: This should fold to 204889define i64 @con2048_minus_rem() {90; CHECK-LABEL: con2048_minus_rem:91; CHECK: # %bb.0:92; CHECK-NEXT: csrr a0, vlenb93; CHECK-NEXT: li a1, 194; CHECK-NEXT: srli a0, a0, 395; CHECK-NEXT: neg a0, a096; CHECK-NEXT: slli a1, a1, 1197; CHECK-NEXT: and a0, a0, a198; CHECK-NEXT: ret99 %vscale = call i64 @llvm.vscale.i64()100 %urem = urem i64 2048, %vscale101 %VTC = sub i64 2048, %urem102 ret i64 %VTC103}104