1355 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin \3; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin \5; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s6 7define void @intrinsic_vse_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vse_v_nxv1i64_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma11; CHECK-NEXT: vse64.v v8, (a0)12; CHECK-NEXT: ret13entry:14 call void @llvm.riscv.vse.nxv1i64(15 <vscale x 1 x i64> %0,16 ptr %1,17 iXLen %2)18 19 ret void20}21 22define void @intrinsic_vse_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {23; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i64_nxv1i64:24; CHECK: # %bb.0: # %entry25; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma26; CHECK-NEXT: vse64.v v8, (a0), v0.t27; CHECK-NEXT: ret28entry:29 call void @llvm.riscv.vse.mask.nxv1i64(30 <vscale x 1 x i64> %0,31 ptr %1,32 <vscale x 1 x i1> %2,33 iXLen %3)34 35 ret void36}37 38define void @intrinsic_vse_allonesmask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {39; CHECK-LABEL: intrinsic_vse_allonesmask_v_nxv1i64_nxv1i64:40; CHECK: # %bb.0: # %entry41; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma42; CHECK-NEXT: vse64.v v8, (a0)43; CHECK-NEXT: ret44entry:45 call void @llvm.riscv.vse.mask.nxv1i64(46 <vscale x 1 x i64> %0,47 ptr %1,48 <vscale x 1 x i1> splat (i1 true),49 iXLen %3)50 51 ret void52}53 54define void @intrinsic_vse_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, iXLen %2) nounwind {55; CHECK-LABEL: intrinsic_vse_v_nxv2i64_nxv2i64:56; CHECK: # %bb.0: # %entry57; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma58; CHECK-NEXT: vse64.v v8, (a0)59; CHECK-NEXT: ret60entry:61 call void @llvm.riscv.vse.nxv2i64(62 <vscale x 2 x i64> %0,63 ptr %1,64 iXLen %2)65 66 ret void67}68 69define void @intrinsic_vse_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {70; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i64_nxv2i64:71; CHECK: # %bb.0: # %entry72; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma73; CHECK-NEXT: vse64.v v8, (a0), v0.t74; CHECK-NEXT: ret75entry:76 call void @llvm.riscv.vse.mask.nxv2i64(77 <vscale x 2 x i64> %0,78 ptr %1,79 <vscale x 2 x i1> %2,80 iXLen %3)81 82 ret void83}84 85define void @intrinsic_vse_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, iXLen %2) nounwind {86; CHECK-LABEL: intrinsic_vse_v_nxv4i64_nxv4i64:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma89; CHECK-NEXT: vse64.v v8, (a0)90; CHECK-NEXT: ret91entry:92 call void @llvm.riscv.vse.nxv4i64(93 <vscale x 4 x i64> %0,94 ptr %1,95 iXLen %2)96 97 ret void98}99 100define void @intrinsic_vse_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {101; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i64_nxv4i64:102; CHECK: # %bb.0: # %entry103; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma104; CHECK-NEXT: vse64.v v8, (a0), v0.t105; CHECK-NEXT: ret106entry:107 call void @llvm.riscv.vse.mask.nxv4i64(108 <vscale x 4 x i64> %0,109 ptr %1,110 <vscale x 4 x i1> %2,111 iXLen %3)112 113 ret void114}115 116define void @intrinsic_vse_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, iXLen %2) nounwind {117; CHECK-LABEL: intrinsic_vse_v_nxv8i64_nxv8i64:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma120; CHECK-NEXT: vse64.v v8, (a0)121; CHECK-NEXT: ret122entry:123 call void @llvm.riscv.vse.nxv8i64(124 <vscale x 8 x i64> %0,125 ptr %1,126 iXLen %2)127 128 ret void129}130 131define void @intrinsic_vse_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {132; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i64_nxv8i64:133; CHECK: # %bb.0: # %entry134; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma135; CHECK-NEXT: vse64.v v8, (a0), v0.t136; CHECK-NEXT: ret137entry:138 call void @llvm.riscv.vse.mask.nxv8i64(139 <vscale x 8 x i64> %0,140 ptr %1,141 <vscale x 8 x i1> %2,142 iXLen %3)143 144 ret void145}146 147define void @intrinsic_vse_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, iXLen %2) nounwind {148; CHECK-LABEL: intrinsic_vse_v_nxv1f64_nxv1f64:149; CHECK: # %bb.0: # %entry150; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma151; CHECK-NEXT: vse64.v v8, (a0)152; CHECK-NEXT: ret153entry:154 call void @llvm.riscv.vse.nxv1f64(155 <vscale x 1 x double> %0,156 ptr %1,157 iXLen %2)158 159 ret void160}161 162define void @intrinsic_vse_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {163; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f64_nxv1f64:164; CHECK: # %bb.0: # %entry165; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma166; CHECK-NEXT: vse64.v v8, (a0), v0.t167; CHECK-NEXT: ret168entry:169 call void @llvm.riscv.vse.mask.nxv1f64(170 <vscale x 1 x double> %0,171 ptr %1,172 <vscale x 1 x i1> %2,173 iXLen %3)174 175 ret void176}177 178define void @intrinsic_vse_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, iXLen %2) nounwind {179; CHECK-LABEL: intrinsic_vse_v_nxv2f64_nxv2f64:180; CHECK: # %bb.0: # %entry181; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma182; CHECK-NEXT: vse64.v v8, (a0)183; CHECK-NEXT: ret184entry:185 call void @llvm.riscv.vse.nxv2f64(186 <vscale x 2 x double> %0,187 ptr %1,188 iXLen %2)189 190 ret void191}192 193define void @intrinsic_vse_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {194; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f64_nxv2f64:195; CHECK: # %bb.0: # %entry196; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma197; CHECK-NEXT: vse64.v v8, (a0), v0.t198; CHECK-NEXT: ret199entry:200 call void @llvm.riscv.vse.mask.nxv2f64(201 <vscale x 2 x double> %0,202 ptr %1,203 <vscale x 2 x i1> %2,204 iXLen %3)205 206 ret void207}208 209define void @intrinsic_vse_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, iXLen %2) nounwind {210; CHECK-LABEL: intrinsic_vse_v_nxv4f64_nxv4f64:211; CHECK: # %bb.0: # %entry212; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma213; CHECK-NEXT: vse64.v v8, (a0)214; CHECK-NEXT: ret215entry:216 call void @llvm.riscv.vse.nxv4f64(217 <vscale x 4 x double> %0,218 ptr %1,219 iXLen %2)220 221 ret void222}223 224define void @intrinsic_vse_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {225; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f64_nxv4f64:226; CHECK: # %bb.0: # %entry227; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma228; CHECK-NEXT: vse64.v v8, (a0), v0.t229; CHECK-NEXT: ret230entry:231 call void @llvm.riscv.vse.mask.nxv4f64(232 <vscale x 4 x double> %0,233 ptr %1,234 <vscale x 4 x i1> %2,235 iXLen %3)236 237 ret void238}239 240define void @intrinsic_vse_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, iXLen %2) nounwind {241; CHECK-LABEL: intrinsic_vse_v_nxv8f64_nxv8f64:242; CHECK: # %bb.0: # %entry243; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma244; CHECK-NEXT: vse64.v v8, (a0)245; CHECK-NEXT: ret246entry:247 call void @llvm.riscv.vse.nxv8f64(248 <vscale x 8 x double> %0,249 ptr %1,250 iXLen %2)251 252 ret void253}254 255define void @intrinsic_vse_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {256; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f64_nxv8f64:257; CHECK: # %bb.0: # %entry258; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma259; CHECK-NEXT: vse64.v v8, (a0), v0.t260; CHECK-NEXT: ret261entry:262 call void @llvm.riscv.vse.mask.nxv8f64(263 <vscale x 8 x double> %0,264 ptr %1,265 <vscale x 8 x i1> %2,266 iXLen %3)267 268 ret void269}270 271define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, iXLen %2) nounwind {272; CHECK-LABEL: intrinsic_vse_v_nxv1i32_nxv1i32:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma275; CHECK-NEXT: vse32.v v8, (a0)276; CHECK-NEXT: ret277entry:278 call void @llvm.riscv.vse.nxv1i32(279 <vscale x 1 x i32> %0,280 ptr %1,281 iXLen %2)282 283 ret void284}285 286define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {287; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i32_nxv1i32:288; CHECK: # %bb.0: # %entry289; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma290; CHECK-NEXT: vse32.v v8, (a0), v0.t291; CHECK-NEXT: ret292entry:293 call void @llvm.riscv.vse.mask.nxv1i32(294 <vscale x 1 x i32> %0,295 ptr %1,296 <vscale x 1 x i1> %2,297 iXLen %3)298 299 ret void300}301 302define void @intrinsic_vse_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, iXLen %2) nounwind {303; CHECK-LABEL: intrinsic_vse_v_nxv2i32_nxv2i32:304; CHECK: # %bb.0: # %entry305; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma306; CHECK-NEXT: vse32.v v8, (a0)307; CHECK-NEXT: ret308entry:309 call void @llvm.riscv.vse.nxv2i32(310 <vscale x 2 x i32> %0,311 ptr %1,312 iXLen %2)313 314 ret void315}316 317define void @intrinsic_vse_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {318; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i32_nxv2i32:319; CHECK: # %bb.0: # %entry320; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma321; CHECK-NEXT: vse32.v v8, (a0), v0.t322; CHECK-NEXT: ret323entry:324 call void @llvm.riscv.vse.mask.nxv2i32(325 <vscale x 2 x i32> %0,326 ptr %1,327 <vscale x 2 x i1> %2,328 iXLen %3)329 330 ret void331}332 333define void @intrinsic_vse_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, iXLen %2) nounwind {334; CHECK-LABEL: intrinsic_vse_v_nxv4i32_nxv4i32:335; CHECK: # %bb.0: # %entry336; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma337; CHECK-NEXT: vse32.v v8, (a0)338; CHECK-NEXT: ret339entry:340 call void @llvm.riscv.vse.nxv4i32(341 <vscale x 4 x i32> %0,342 ptr %1,343 iXLen %2)344 345 ret void346}347 348define void @intrinsic_vse_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {349; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i32_nxv4i32:350; CHECK: # %bb.0: # %entry351; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma352; CHECK-NEXT: vse32.v v8, (a0), v0.t353; CHECK-NEXT: ret354entry:355 call void @llvm.riscv.vse.mask.nxv4i32(356 <vscale x 4 x i32> %0,357 ptr %1,358 <vscale x 4 x i1> %2,359 iXLen %3)360 361 ret void362}363 364define void @intrinsic_vse_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, iXLen %2) nounwind {365; CHECK-LABEL: intrinsic_vse_v_nxv8i32_nxv8i32:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma368; CHECK-NEXT: vse32.v v8, (a0)369; CHECK-NEXT: ret370entry:371 call void @llvm.riscv.vse.nxv8i32(372 <vscale x 8 x i32> %0,373 ptr %1,374 iXLen %2)375 376 ret void377}378 379define void @intrinsic_vse_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {380; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i32_nxv8i32:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma383; CHECK-NEXT: vse32.v v8, (a0), v0.t384; CHECK-NEXT: ret385entry:386 call void @llvm.riscv.vse.mask.nxv8i32(387 <vscale x 8 x i32> %0,388 ptr %1,389 <vscale x 8 x i1> %2,390 iXLen %3)391 392 ret void393}394 395define void @intrinsic_vse_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, iXLen %2) nounwind {396; CHECK-LABEL: intrinsic_vse_v_nxv16i32_nxv16i32:397; CHECK: # %bb.0: # %entry398; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma399; CHECK-NEXT: vse32.v v8, (a0)400; CHECK-NEXT: ret401entry:402 call void @llvm.riscv.vse.nxv16i32(403 <vscale x 16 x i32> %0,404 ptr %1,405 iXLen %2)406 407 ret void408}409 410define void @intrinsic_vse_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {411; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i32_nxv16i32:412; CHECK: # %bb.0: # %entry413; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma414; CHECK-NEXT: vse32.v v8, (a0), v0.t415; CHECK-NEXT: ret416entry:417 call void @llvm.riscv.vse.mask.nxv16i32(418 <vscale x 16 x i32> %0,419 ptr %1,420 <vscale x 16 x i1> %2,421 iXLen %3)422 423 ret void424}425 426define void @intrinsic_vse_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, iXLen %2) nounwind {427; CHECK-LABEL: intrinsic_vse_v_nxv1f32_nxv1f32:428; CHECK: # %bb.0: # %entry429; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma430; CHECK-NEXT: vse32.v v8, (a0)431; CHECK-NEXT: ret432entry:433 call void @llvm.riscv.vse.nxv1f32(434 <vscale x 1 x float> %0,435 ptr %1,436 iXLen %2)437 438 ret void439}440 441define void @intrinsic_vse_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {442; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f32_nxv1f32:443; CHECK: # %bb.0: # %entry444; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma445; CHECK-NEXT: vse32.v v8, (a0), v0.t446; CHECK-NEXT: ret447entry:448 call void @llvm.riscv.vse.mask.nxv1f32(449 <vscale x 1 x float> %0,450 ptr %1,451 <vscale x 1 x i1> %2,452 iXLen %3)453 454 ret void455}456 457define void @intrinsic_vse_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, iXLen %2) nounwind {458; CHECK-LABEL: intrinsic_vse_v_nxv2f32_nxv2f32:459; CHECK: # %bb.0: # %entry460; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma461; CHECK-NEXT: vse32.v v8, (a0)462; CHECK-NEXT: ret463entry:464 call void @llvm.riscv.vse.nxv2f32(465 <vscale x 2 x float> %0,466 ptr %1,467 iXLen %2)468 469 ret void470}471 472define void @intrinsic_vse_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {473; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f32_nxv2f32:474; CHECK: # %bb.0: # %entry475; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma476; CHECK-NEXT: vse32.v v8, (a0), v0.t477; CHECK-NEXT: ret478entry:479 call void @llvm.riscv.vse.mask.nxv2f32(480 <vscale x 2 x float> %0,481 ptr %1,482 <vscale x 2 x i1> %2,483 iXLen %3)484 485 ret void486}487 488define void @intrinsic_vse_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, iXLen %2) nounwind {489; CHECK-LABEL: intrinsic_vse_v_nxv4f32_nxv4f32:490; CHECK: # %bb.0: # %entry491; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma492; CHECK-NEXT: vse32.v v8, (a0)493; CHECK-NEXT: ret494entry:495 call void @llvm.riscv.vse.nxv4f32(496 <vscale x 4 x float> %0,497 ptr %1,498 iXLen %2)499 500 ret void501}502 503define void @intrinsic_vse_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {504; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f32_nxv4f32:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma507; CHECK-NEXT: vse32.v v8, (a0), v0.t508; CHECK-NEXT: ret509entry:510 call void @llvm.riscv.vse.mask.nxv4f32(511 <vscale x 4 x float> %0,512 ptr %1,513 <vscale x 4 x i1> %2,514 iXLen %3)515 516 ret void517}518 519define void @intrinsic_vse_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, iXLen %2) nounwind {520; CHECK-LABEL: intrinsic_vse_v_nxv8f32_nxv8f32:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma523; CHECK-NEXT: vse32.v v8, (a0)524; CHECK-NEXT: ret525entry:526 call void @llvm.riscv.vse.nxv8f32(527 <vscale x 8 x float> %0,528 ptr %1,529 iXLen %2)530 531 ret void532}533 534define void @intrinsic_vse_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {535; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f32_nxv8f32:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma538; CHECK-NEXT: vse32.v v8, (a0), v0.t539; CHECK-NEXT: ret540entry:541 call void @llvm.riscv.vse.mask.nxv8f32(542 <vscale x 8 x float> %0,543 ptr %1,544 <vscale x 8 x i1> %2,545 iXLen %3)546 547 ret void548}549 550define void @intrinsic_vse_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, iXLen %2) nounwind {551; CHECK-LABEL: intrinsic_vse_v_nxv16f32_nxv16f32:552; CHECK: # %bb.0: # %entry553; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma554; CHECK-NEXT: vse32.v v8, (a0)555; CHECK-NEXT: ret556entry:557 call void @llvm.riscv.vse.nxv16f32(558 <vscale x 16 x float> %0,559 ptr %1,560 iXLen %2)561 562 ret void563}564 565define void @intrinsic_vse_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {566; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f32_nxv16f32:567; CHECK: # %bb.0: # %entry568; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma569; CHECK-NEXT: vse32.v v8, (a0), v0.t570; CHECK-NEXT: ret571entry:572 call void @llvm.riscv.vse.mask.nxv16f32(573 <vscale x 16 x float> %0,574 ptr %1,575 <vscale x 16 x i1> %2,576 iXLen %3)577 578 ret void579}580 581define void @intrinsic_vse_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, iXLen %2) nounwind {582; CHECK-LABEL: intrinsic_vse_v_nxv1i16_nxv1i16:583; CHECK: # %bb.0: # %entry584; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma585; CHECK-NEXT: vse16.v v8, (a0)586; CHECK-NEXT: ret587entry:588 call void @llvm.riscv.vse.nxv1i16(589 <vscale x 1 x i16> %0,590 ptr %1,591 iXLen %2)592 593 ret void594}595 596define void @intrinsic_vse_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {597; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i16_nxv1i16:598; CHECK: # %bb.0: # %entry599; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma600; CHECK-NEXT: vse16.v v8, (a0), v0.t601; CHECK-NEXT: ret602entry:603 call void @llvm.riscv.vse.mask.nxv1i16(604 <vscale x 1 x i16> %0,605 ptr %1,606 <vscale x 1 x i1> %2,607 iXLen %3)608 609 ret void610}611 612define void @intrinsic_vse_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, iXLen %2) nounwind {613; CHECK-LABEL: intrinsic_vse_v_nxv2i16_nxv2i16:614; CHECK: # %bb.0: # %entry615; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma616; CHECK-NEXT: vse16.v v8, (a0)617; CHECK-NEXT: ret618entry:619 call void @llvm.riscv.vse.nxv2i16(620 <vscale x 2 x i16> %0,621 ptr %1,622 iXLen %2)623 624 ret void625}626 627define void @intrinsic_vse_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {628; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i16_nxv2i16:629; CHECK: # %bb.0: # %entry630; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma631; CHECK-NEXT: vse16.v v8, (a0), v0.t632; CHECK-NEXT: ret633entry:634 call void @llvm.riscv.vse.mask.nxv2i16(635 <vscale x 2 x i16> %0,636 ptr %1,637 <vscale x 2 x i1> %2,638 iXLen %3)639 640 ret void641}642 643define void @intrinsic_vse_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, iXLen %2) nounwind {644; CHECK-LABEL: intrinsic_vse_v_nxv4i16_nxv4i16:645; CHECK: # %bb.0: # %entry646; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma647; CHECK-NEXT: vse16.v v8, (a0)648; CHECK-NEXT: ret649entry:650 call void @llvm.riscv.vse.nxv4i16(651 <vscale x 4 x i16> %0,652 ptr %1,653 iXLen %2)654 655 ret void656}657 658define void @intrinsic_vse_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {659; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i16_nxv4i16:660; CHECK: # %bb.0: # %entry661; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma662; CHECK-NEXT: vse16.v v8, (a0), v0.t663; CHECK-NEXT: ret664entry:665 call void @llvm.riscv.vse.mask.nxv4i16(666 <vscale x 4 x i16> %0,667 ptr %1,668 <vscale x 4 x i1> %2,669 iXLen %3)670 671 ret void672}673 674define void @intrinsic_vse_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, iXLen %2) nounwind {675; CHECK-LABEL: intrinsic_vse_v_nxv8i16_nxv8i16:676; CHECK: # %bb.0: # %entry677; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma678; CHECK-NEXT: vse16.v v8, (a0)679; CHECK-NEXT: ret680entry:681 call void @llvm.riscv.vse.nxv8i16(682 <vscale x 8 x i16> %0,683 ptr %1,684 iXLen %2)685 686 ret void687}688 689define void @intrinsic_vse_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {690; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i16_nxv8i16:691; CHECK: # %bb.0: # %entry692; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma693; CHECK-NEXT: vse16.v v8, (a0), v0.t694; CHECK-NEXT: ret695entry:696 call void @llvm.riscv.vse.mask.nxv8i16(697 <vscale x 8 x i16> %0,698 ptr %1,699 <vscale x 8 x i1> %2,700 iXLen %3)701 702 ret void703}704 705define void @intrinsic_vse_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, iXLen %2) nounwind {706; CHECK-LABEL: intrinsic_vse_v_nxv16i16_nxv16i16:707; CHECK: # %bb.0: # %entry708; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma709; CHECK-NEXT: vse16.v v8, (a0)710; CHECK-NEXT: ret711entry:712 call void @llvm.riscv.vse.nxv16i16(713 <vscale x 16 x i16> %0,714 ptr %1,715 iXLen %2)716 717 ret void718}719 720define void @intrinsic_vse_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {721; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i16_nxv16i16:722; CHECK: # %bb.0: # %entry723; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma724; CHECK-NEXT: vse16.v v8, (a0), v0.t725; CHECK-NEXT: ret726entry:727 call void @llvm.riscv.vse.mask.nxv16i16(728 <vscale x 16 x i16> %0,729 ptr %1,730 <vscale x 16 x i1> %2,731 iXLen %3)732 733 ret void734}735 736define void @intrinsic_vse_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, iXLen %2) nounwind {737; CHECK-LABEL: intrinsic_vse_v_nxv32i16_nxv32i16:738; CHECK: # %bb.0: # %entry739; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma740; CHECK-NEXT: vse16.v v8, (a0)741; CHECK-NEXT: ret742entry:743 call void @llvm.riscv.vse.nxv32i16(744 <vscale x 32 x i16> %0,745 ptr %1,746 iXLen %2)747 748 ret void749}750 751define void @intrinsic_vse_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {752; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i16_nxv32i16:753; CHECK: # %bb.0: # %entry754; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma755; CHECK-NEXT: vse16.v v8, (a0), v0.t756; CHECK-NEXT: ret757entry:758 call void @llvm.riscv.vse.mask.nxv32i16(759 <vscale x 32 x i16> %0,760 ptr %1,761 <vscale x 32 x i1> %2,762 iXLen %3)763 764 ret void765}766 767define void @intrinsic_vse_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, iXLen %2) nounwind {768; CHECK-LABEL: intrinsic_vse_v_nxv1f16_nxv1f16:769; CHECK: # %bb.0: # %entry770; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma771; CHECK-NEXT: vse16.v v8, (a0)772; CHECK-NEXT: ret773entry:774 call void @llvm.riscv.vse.nxv1f16(775 <vscale x 1 x half> %0,776 ptr %1,777 iXLen %2)778 779 ret void780}781 782define void @intrinsic_vse_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {783; CHECK-LABEL: intrinsic_vse_mask_v_nxv1f16_nxv1f16:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma786; CHECK-NEXT: vse16.v v8, (a0), v0.t787; CHECK-NEXT: ret788entry:789 call void @llvm.riscv.vse.mask.nxv1f16(790 <vscale x 1 x half> %0,791 ptr %1,792 <vscale x 1 x i1> %2,793 iXLen %3)794 795 ret void796}797 798define void @intrinsic_vse_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, iXLen %2) nounwind {799; CHECK-LABEL: intrinsic_vse_v_nxv2f16_nxv2f16:800; CHECK: # %bb.0: # %entry801; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma802; CHECK-NEXT: vse16.v v8, (a0)803; CHECK-NEXT: ret804entry:805 call void @llvm.riscv.vse.nxv2f16(806 <vscale x 2 x half> %0,807 ptr %1,808 iXLen %2)809 810 ret void811}812 813define void @intrinsic_vse_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {814; CHECK-LABEL: intrinsic_vse_mask_v_nxv2f16_nxv2f16:815; CHECK: # %bb.0: # %entry816; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma817; CHECK-NEXT: vse16.v v8, (a0), v0.t818; CHECK-NEXT: ret819entry:820 call void @llvm.riscv.vse.mask.nxv2f16(821 <vscale x 2 x half> %0,822 ptr %1,823 <vscale x 2 x i1> %2,824 iXLen %3)825 826 ret void827}828 829define void @intrinsic_vse_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, iXLen %2) nounwind {830; CHECK-LABEL: intrinsic_vse_v_nxv4f16_nxv4f16:831; CHECK: # %bb.0: # %entry832; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma833; CHECK-NEXT: vse16.v v8, (a0)834; CHECK-NEXT: ret835entry:836 call void @llvm.riscv.vse.nxv4f16(837 <vscale x 4 x half> %0,838 ptr %1,839 iXLen %2)840 841 ret void842}843 844define void @intrinsic_vse_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {845; CHECK-LABEL: intrinsic_vse_mask_v_nxv4f16_nxv4f16:846; CHECK: # %bb.0: # %entry847; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma848; CHECK-NEXT: vse16.v v8, (a0), v0.t849; CHECK-NEXT: ret850entry:851 call void @llvm.riscv.vse.mask.nxv4f16(852 <vscale x 4 x half> %0,853 ptr %1,854 <vscale x 4 x i1> %2,855 iXLen %3)856 857 ret void858}859 860define void @intrinsic_vse_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, iXLen %2) nounwind {861; CHECK-LABEL: intrinsic_vse_v_nxv8f16_nxv8f16:862; CHECK: # %bb.0: # %entry863; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma864; CHECK-NEXT: vse16.v v8, (a0)865; CHECK-NEXT: ret866entry:867 call void @llvm.riscv.vse.nxv8f16(868 <vscale x 8 x half> %0,869 ptr %1,870 iXLen %2)871 872 ret void873}874 875define void @intrinsic_vse_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {876; CHECK-LABEL: intrinsic_vse_mask_v_nxv8f16_nxv8f16:877; CHECK: # %bb.0: # %entry878; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma879; CHECK-NEXT: vse16.v v8, (a0), v0.t880; CHECK-NEXT: ret881entry:882 call void @llvm.riscv.vse.mask.nxv8f16(883 <vscale x 8 x half> %0,884 ptr %1,885 <vscale x 8 x i1> %2,886 iXLen %3)887 888 ret void889}890 891define void @intrinsic_vse_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, iXLen %2) nounwind {892; CHECK-LABEL: intrinsic_vse_v_nxv16f16_nxv16f16:893; CHECK: # %bb.0: # %entry894; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma895; CHECK-NEXT: vse16.v v8, (a0)896; CHECK-NEXT: ret897entry:898 call void @llvm.riscv.vse.nxv16f16(899 <vscale x 16 x half> %0,900 ptr %1,901 iXLen %2)902 903 ret void904}905 906define void @intrinsic_vse_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {907; CHECK-LABEL: intrinsic_vse_mask_v_nxv16f16_nxv16f16:908; CHECK: # %bb.0: # %entry909; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma910; CHECK-NEXT: vse16.v v8, (a0), v0.t911; CHECK-NEXT: ret912entry:913 call void @llvm.riscv.vse.mask.nxv16f16(914 <vscale x 16 x half> %0,915 ptr %1,916 <vscale x 16 x i1> %2,917 iXLen %3)918 919 ret void920}921 922define void @intrinsic_vse_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, iXLen %2) nounwind {923; CHECK-LABEL: intrinsic_vse_v_nxv32f16_nxv32f16:924; CHECK: # %bb.0: # %entry925; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma926; CHECK-NEXT: vse16.v v8, (a0)927; CHECK-NEXT: ret928entry:929 call void @llvm.riscv.vse.nxv32f16(930 <vscale x 32 x half> %0,931 ptr %1,932 iXLen %2)933 934 ret void935}936 937define void @intrinsic_vse_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {938; CHECK-LABEL: intrinsic_vse_mask_v_nxv32f16_nxv32f16:939; CHECK: # %bb.0: # %entry940; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma941; CHECK-NEXT: vse16.v v8, (a0), v0.t942; CHECK-NEXT: ret943entry:944 call void @llvm.riscv.vse.mask.nxv32f16(945 <vscale x 32 x half> %0,946 ptr %1,947 <vscale x 32 x i1> %2,948 iXLen %3)949 950 ret void951}952 953define void @intrinsic_vse_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, iXLen %2) nounwind {954; CHECK-LABEL: intrinsic_vse_v_nxv1bf16_nxv1bf16:955; CHECK: # %bb.0: # %entry956; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma957; CHECK-NEXT: vse16.v v8, (a0)958; CHECK-NEXT: ret959entry:960 call void @llvm.riscv.vse.nxv1bf16(961 <vscale x 1 x bfloat> %0,962 ptr %1,963 iXLen %2)964 965 ret void966}967 968define void @intrinsic_vse_mask_v_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {969; CHECK-LABEL: intrinsic_vse_mask_v_nxv1bf16_nxv1bf16:970; CHECK: # %bb.0: # %entry971; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma972; CHECK-NEXT: vse16.v v8, (a0), v0.t973; CHECK-NEXT: ret974entry:975 call void @llvm.riscv.vse.mask.nxv1bf16(976 <vscale x 1 x bfloat> %0,977 ptr %1,978 <vscale x 1 x i1> %2,979 iXLen %3)980 981 ret void982}983 984define void @intrinsic_vse_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, iXLen %2) nounwind {985; CHECK-LABEL: intrinsic_vse_v_nxv2bf16_nxv2bf16:986; CHECK: # %bb.0: # %entry987; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma988; CHECK-NEXT: vse16.v v8, (a0)989; CHECK-NEXT: ret990entry:991 call void @llvm.riscv.vse.nxv2bf16(992 <vscale x 2 x bfloat> %0,993 ptr %1,994 iXLen %2)995 996 ret void997}998 999define void @intrinsic_vse_mask_v_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1000; CHECK-LABEL: intrinsic_vse_mask_v_nxv2bf16_nxv2bf16:1001; CHECK: # %bb.0: # %entry1002; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1003; CHECK-NEXT: vse16.v v8, (a0), v0.t1004; CHECK-NEXT: ret1005entry:1006 call void @llvm.riscv.vse.mask.nxv2bf16(1007 <vscale x 2 x bfloat> %0,1008 ptr %1,1009 <vscale x 2 x i1> %2,1010 iXLen %3)1011 1012 ret void1013}1014 1015define void @intrinsic_vse_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, iXLen %2) nounwind {1016; CHECK-LABEL: intrinsic_vse_v_nxv4bf16_nxv4bf16:1017; CHECK: # %bb.0: # %entry1018; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1019; CHECK-NEXT: vse16.v v8, (a0)1020; CHECK-NEXT: ret1021entry:1022 call void @llvm.riscv.vse.nxv4bf16(1023 <vscale x 4 x bfloat> %0,1024 ptr %1,1025 iXLen %2)1026 1027 ret void1028}1029 1030define void @intrinsic_vse_mask_v_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1031; CHECK-LABEL: intrinsic_vse_mask_v_nxv4bf16_nxv4bf16:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1034; CHECK-NEXT: vse16.v v8, (a0), v0.t1035; CHECK-NEXT: ret1036entry:1037 call void @llvm.riscv.vse.mask.nxv4bf16(1038 <vscale x 4 x bfloat> %0,1039 ptr %1,1040 <vscale x 4 x i1> %2,1041 iXLen %3)1042 1043 ret void1044}1045 1046define void @intrinsic_vse_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, iXLen %2) nounwind {1047; CHECK-LABEL: intrinsic_vse_v_nxv8bf16_nxv8bf16:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1050; CHECK-NEXT: vse16.v v8, (a0)1051; CHECK-NEXT: ret1052entry:1053 call void @llvm.riscv.vse.nxv8bf16(1054 <vscale x 8 x bfloat> %0,1055 ptr %1,1056 iXLen %2)1057 1058 ret void1059}1060 1061define void @intrinsic_vse_mask_v_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1062; CHECK-LABEL: intrinsic_vse_mask_v_nxv8bf16_nxv8bf16:1063; CHECK: # %bb.0: # %entry1064; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1065; CHECK-NEXT: vse16.v v8, (a0), v0.t1066; CHECK-NEXT: ret1067entry:1068 call void @llvm.riscv.vse.mask.nxv8bf16(1069 <vscale x 8 x bfloat> %0,1070 ptr %1,1071 <vscale x 8 x i1> %2,1072 iXLen %3)1073 1074 ret void1075}1076 1077define void @intrinsic_vse_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, iXLen %2) nounwind {1078; CHECK-LABEL: intrinsic_vse_v_nxv16bf16_nxv16bf16:1079; CHECK: # %bb.0: # %entry1080; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1081; CHECK-NEXT: vse16.v v8, (a0)1082; CHECK-NEXT: ret1083entry:1084 call void @llvm.riscv.vse.nxv16bf16(1085 <vscale x 16 x bfloat> %0,1086 ptr %1,1087 iXLen %2)1088 1089 ret void1090}1091 1092define void @intrinsic_vse_mask_v_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1093; CHECK-LABEL: intrinsic_vse_mask_v_nxv16bf16_nxv16bf16:1094; CHECK: # %bb.0: # %entry1095; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1096; CHECK-NEXT: vse16.v v8, (a0), v0.t1097; CHECK-NEXT: ret1098entry:1099 call void @llvm.riscv.vse.mask.nxv16bf16(1100 <vscale x 16 x bfloat> %0,1101 ptr %1,1102 <vscale x 16 x i1> %2,1103 iXLen %3)1104 1105 ret void1106}1107 1108define void @intrinsic_vse_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, iXLen %2) nounwind {1109; CHECK-LABEL: intrinsic_vse_v_nxv32bf16_nxv32bf16:1110; CHECK: # %bb.0: # %entry1111; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1112; CHECK-NEXT: vse16.v v8, (a0)1113; CHECK-NEXT: ret1114entry:1115 call void @llvm.riscv.vse.nxv32bf16(1116 <vscale x 32 x bfloat> %0,1117 ptr %1,1118 iXLen %2)1119 1120 ret void1121}1122 1123define void @intrinsic_vse_mask_v_nxv32bf16_nxv32bf16(<vscale x 32 x bfloat> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1124; CHECK-LABEL: intrinsic_vse_mask_v_nxv32bf16_nxv32bf16:1125; CHECK: # %bb.0: # %entry1126; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1127; CHECK-NEXT: vse16.v v8, (a0), v0.t1128; CHECK-NEXT: ret1129entry:1130 call void @llvm.riscv.vse.mask.nxv32bf16(1131 <vscale x 32 x bfloat> %0,1132 ptr %1,1133 <vscale x 32 x i1> %2,1134 iXLen %3)1135 1136 ret void1137}1138 1139define void @intrinsic_vse_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, iXLen %2) nounwind {1140; CHECK-LABEL: intrinsic_vse_v_nxv1i8_nxv1i8:1141; CHECK: # %bb.0: # %entry1142; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1143; CHECK-NEXT: vse8.v v8, (a0)1144; CHECK-NEXT: ret1145entry:1146 call void @llvm.riscv.vse.nxv1i8(1147 <vscale x 1 x i8> %0,1148 ptr %1,1149 iXLen %2)1150 1151 ret void1152}1153 1154define void @intrinsic_vse_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1155; CHECK-LABEL: intrinsic_vse_mask_v_nxv1i8_nxv1i8:1156; CHECK: # %bb.0: # %entry1157; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma1158; CHECK-NEXT: vse8.v v8, (a0), v0.t1159; CHECK-NEXT: ret1160entry:1161 call void @llvm.riscv.vse.mask.nxv1i8(1162 <vscale x 1 x i8> %0,1163 ptr %1,1164 <vscale x 1 x i1> %2,1165 iXLen %3)1166 1167 ret void1168}1169 1170define void @intrinsic_vse_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, iXLen %2) nounwind {1171; CHECK-LABEL: intrinsic_vse_v_nxv2i8_nxv2i8:1172; CHECK: # %bb.0: # %entry1173; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1174; CHECK-NEXT: vse8.v v8, (a0)1175; CHECK-NEXT: ret1176entry:1177 call void @llvm.riscv.vse.nxv2i8(1178 <vscale x 2 x i8> %0,1179 ptr %1,1180 iXLen %2)1181 1182 ret void1183}1184 1185define void @intrinsic_vse_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1186; CHECK-LABEL: intrinsic_vse_mask_v_nxv2i8_nxv2i8:1187; CHECK: # %bb.0: # %entry1188; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma1189; CHECK-NEXT: vse8.v v8, (a0), v0.t1190; CHECK-NEXT: ret1191entry:1192 call void @llvm.riscv.vse.mask.nxv2i8(1193 <vscale x 2 x i8> %0,1194 ptr %1,1195 <vscale x 2 x i1> %2,1196 iXLen %3)1197 1198 ret void1199}1200 1201define void @intrinsic_vse_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, iXLen %2) nounwind {1202; CHECK-LABEL: intrinsic_vse_v_nxv4i8_nxv4i8:1203; CHECK: # %bb.0: # %entry1204; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1205; CHECK-NEXT: vse8.v v8, (a0)1206; CHECK-NEXT: ret1207entry:1208 call void @llvm.riscv.vse.nxv4i8(1209 <vscale x 4 x i8> %0,1210 ptr %1,1211 iXLen %2)1212 1213 ret void1214}1215 1216define void @intrinsic_vse_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1217; CHECK-LABEL: intrinsic_vse_mask_v_nxv4i8_nxv4i8:1218; CHECK: # %bb.0: # %entry1219; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma1220; CHECK-NEXT: vse8.v v8, (a0), v0.t1221; CHECK-NEXT: ret1222entry:1223 call void @llvm.riscv.vse.mask.nxv4i8(1224 <vscale x 4 x i8> %0,1225 ptr %1,1226 <vscale x 4 x i1> %2,1227 iXLen %3)1228 1229 ret void1230}1231 1232define void @intrinsic_vse_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, iXLen %2) nounwind {1233; CHECK-LABEL: intrinsic_vse_v_nxv8i8_nxv8i8:1234; CHECK: # %bb.0: # %entry1235; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1236; CHECK-NEXT: vse8.v v8, (a0)1237; CHECK-NEXT: ret1238entry:1239 call void @llvm.riscv.vse.nxv8i8(1240 <vscale x 8 x i8> %0,1241 ptr %1,1242 iXLen %2)1243 1244 ret void1245}1246 1247define void @intrinsic_vse_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1248; CHECK-LABEL: intrinsic_vse_mask_v_nxv8i8_nxv8i8:1249; CHECK: # %bb.0: # %entry1250; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma1251; CHECK-NEXT: vse8.v v8, (a0), v0.t1252; CHECK-NEXT: ret1253entry:1254 call void @llvm.riscv.vse.mask.nxv8i8(1255 <vscale x 8 x i8> %0,1256 ptr %1,1257 <vscale x 8 x i1> %2,1258 iXLen %3)1259 1260 ret void1261}1262 1263define void @intrinsic_vse_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, iXLen %2) nounwind {1264; CHECK-LABEL: intrinsic_vse_v_nxv16i8_nxv16i8:1265; CHECK: # %bb.0: # %entry1266; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1267; CHECK-NEXT: vse8.v v8, (a0)1268; CHECK-NEXT: ret1269entry:1270 call void @llvm.riscv.vse.nxv16i8(1271 <vscale x 16 x i8> %0,1272 ptr %1,1273 iXLen %2)1274 1275 ret void1276}1277 1278define void @intrinsic_vse_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, ptr %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1279; CHECK-LABEL: intrinsic_vse_mask_v_nxv16i8_nxv16i8:1280; CHECK: # %bb.0: # %entry1281; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma1282; CHECK-NEXT: vse8.v v8, (a0), v0.t1283; CHECK-NEXT: ret1284entry:1285 call void @llvm.riscv.vse.mask.nxv16i8(1286 <vscale x 16 x i8> %0,1287 ptr %1,1288 <vscale x 16 x i1> %2,1289 iXLen %3)1290 1291 ret void1292}1293 1294define void @intrinsic_vse_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, iXLen %2) nounwind {1295; CHECK-LABEL: intrinsic_vse_v_nxv32i8_nxv32i8:1296; CHECK: # %bb.0: # %entry1297; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1298; CHECK-NEXT: vse8.v v8, (a0)1299; CHECK-NEXT: ret1300entry:1301 call void @llvm.riscv.vse.nxv32i8(1302 <vscale x 32 x i8> %0,1303 ptr %1,1304 iXLen %2)1305 1306 ret void1307}1308 1309define void @intrinsic_vse_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, ptr %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {1310; CHECK-LABEL: intrinsic_vse_mask_v_nxv32i8_nxv32i8:1311; CHECK: # %bb.0: # %entry1312; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma1313; CHECK-NEXT: vse8.v v8, (a0), v0.t1314; CHECK-NEXT: ret1315entry:1316 call void @llvm.riscv.vse.mask.nxv32i8(1317 <vscale x 32 x i8> %0,1318 ptr %1,1319 <vscale x 32 x i1> %2,1320 iXLen %3)1321 1322 ret void1323}1324 1325define void @intrinsic_vse_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, iXLen %2) nounwind {1326; CHECK-LABEL: intrinsic_vse_v_nxv64i8_nxv64i8:1327; CHECK: # %bb.0: # %entry1328; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1329; CHECK-NEXT: vse8.v v8, (a0)1330; CHECK-NEXT: ret1331entry:1332 call void @llvm.riscv.vse.nxv64i8(1333 <vscale x 64 x i8> %0,1334 ptr %1,1335 iXLen %2)1336 1337 ret void1338}1339 1340define void @intrinsic_vse_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, ptr %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {1341; CHECK-LABEL: intrinsic_vse_mask_v_nxv64i8_nxv64i8:1342; CHECK: # %bb.0: # %entry1343; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1344; CHECK-NEXT: vse8.v v8, (a0), v0.t1345; CHECK-NEXT: ret1346entry:1347 call void @llvm.riscv.vse.mask.nxv64i8(1348 <vscale x 64 x i8> %0,1349 ptr %1,1350 <vscale x 64 x i1> %2,1351 iXLen %3)1352 1353 ret void1354}1355