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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zfbfmin,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zfbfmin,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+v,+zvfh,+zfbfmin,+zvfbfmin -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+v,+zvfh,+zfbfmin,+zvfbfmin -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s10 11define <vscale x 1 x bfloat> @vfmerge_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x i1> %cond) {12; CHECK-LABEL: vfmerge_vv_nxv1bf16:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma15; CHECK-NEXT: vmerge.vvm v8, v9, v8, v016; CHECK-NEXT: ret17 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb18 ret <vscale x 1 x bfloat> %vc19}20 21define <vscale x 1 x bfloat> @vfmerge_fv_nxv1bf16(<vscale x 1 x bfloat> %va, bfloat %b, <vscale x 1 x i1> %cond) {22; CHECK-LABEL: vfmerge_fv_nxv1bf16:23; CHECK: # %bb.0:24; CHECK-NEXT: fmv.x.h a0, fa025; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma26; CHECK-NEXT: vmv.v.x v9, a027; CHECK-NEXT: vmerge.vvm v8, v8, v9, v028; CHECK-NEXT: ret29 %head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 030 %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer31 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x bfloat> %splat, <vscale x 1 x bfloat> %va32 ret <vscale x 1 x bfloat> %vc33}34 35define <vscale x 2 x bfloat> @vfmerge_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %cond) {36; CHECK-LABEL: vfmerge_vv_nxv2bf16:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma39; CHECK-NEXT: vmerge.vvm v8, v9, v8, v040; CHECK-NEXT: ret41 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb42 ret <vscale x 2 x bfloat> %vc43}44 45define <vscale x 2 x bfloat> @vfmerge_fv_nxv2bf16(<vscale x 2 x bfloat> %va, bfloat %b, <vscale x 2 x i1> %cond) {46; CHECK-LABEL: vfmerge_fv_nxv2bf16:47; CHECK: # %bb.0:48; CHECK-NEXT: fmv.x.h a0, fa049; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma50; CHECK-NEXT: vmv.v.x v9, a051; CHECK-NEXT: vmerge.vvm v8, v8, v9, v052; CHECK-NEXT: ret53 %head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 054 %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer55 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x bfloat> %splat, <vscale x 2 x bfloat> %va56 ret <vscale x 2 x bfloat> %vc57}58 59define <vscale x 4 x bfloat> @vfmerge_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %cond) {60; CHECK-LABEL: vfmerge_vv_nxv4bf16:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma63; CHECK-NEXT: vmerge.vvm v8, v9, v8, v064; CHECK-NEXT: ret65 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb66 ret <vscale x 4 x bfloat> %vc67}68 69define <vscale x 4 x bfloat> @vfmerge_fv_nxv4bf16(<vscale x 4 x bfloat> %va, bfloat %b, <vscale x 4 x i1> %cond) {70; CHECK-LABEL: vfmerge_fv_nxv4bf16:71; CHECK: # %bb.0:72; CHECK-NEXT: fmv.x.h a0, fa073; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma74; CHECK-NEXT: vmv.v.x v9, a075; CHECK-NEXT: vmerge.vvm v8, v8, v9, v076; CHECK-NEXT: ret77 %head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 078 %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer79 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x bfloat> %splat, <vscale x 4 x bfloat> %va80 ret <vscale x 4 x bfloat> %vc81}82 83define <vscale x 8 x bfloat> @vfmerge_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x i1> %cond) {84; CHECK-LABEL: vfmerge_vv_nxv8bf16:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma87; CHECK-NEXT: vmerge.vvm v8, v10, v8, v088; CHECK-NEXT: ret89 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb90 ret <vscale x 8 x bfloat> %vc91}92 93define <vscale x 8 x bfloat> @vfmerge_fv_nxv8bf16(<vscale x 8 x bfloat> %va, bfloat %b, <vscale x 8 x i1> %cond) {94; CHECK-LABEL: vfmerge_fv_nxv8bf16:95; CHECK: # %bb.0:96; CHECK-NEXT: fmv.x.h a0, fa097; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma98; CHECK-NEXT: vmv.v.x v10, a099; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0100; CHECK-NEXT: ret101 %head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0102 %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer103 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> %splat, <vscale x 8 x bfloat> %va104 ret <vscale x 8 x bfloat> %vc105}106 107define <vscale x 8 x bfloat> @vfmerge_zv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %cond) {108; CHECK-LABEL: vfmerge_zv_nxv8bf16:109; CHECK: # %bb.0:110; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma111; CHECK-NEXT: vmv.v.i v10, 0112; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0113; CHECK-NEXT: ret114 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> splat (bfloat zeroinitializer), <vscale x 8 x bfloat> %va115 ret <vscale x 8 x bfloat> %vc116}117 118define <vscale x 8 x bfloat> @vmerge_truelhs_nxv8bf16_0(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb) {119; CHECK-LABEL: vmerge_truelhs_nxv8bf16_0:120; CHECK: # %bb.0:121; CHECK-NEXT: ret122 %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb123 ret <vscale x 8 x bfloat> %vc124}125 126define <vscale x 8 x bfloat> @vmerge_falselhs_nxv8bf16_0(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb) {127; CHECK-LABEL: vmerge_falselhs_nxv8bf16_0:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma130; CHECK-NEXT: vmv2r.v v8, v10131; CHECK-NEXT: ret132 %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb133 ret <vscale x 8 x bfloat> %vc134}135 136define <vscale x 16 x bfloat> @vfmerge_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x i1> %cond) {137; CHECK-LABEL: vfmerge_vv_nxv16bf16:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma140; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0141; CHECK-NEXT: ret142 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb143 ret <vscale x 16 x bfloat> %vc144}145 146define <vscale x 16 x bfloat> @vfmerge_fv_nxv16bf16(<vscale x 16 x bfloat> %va, bfloat %b, <vscale x 16 x i1> %cond) {147; CHECK-LABEL: vfmerge_fv_nxv16bf16:148; CHECK: # %bb.0:149; CHECK-NEXT: fmv.x.h a0, fa0150; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma151; CHECK-NEXT: vmv.v.x v12, a0152; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0153; CHECK-NEXT: ret154 %head = insertelement <vscale x 16 x bfloat> poison, bfloat %b, i32 0155 %splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer156 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x bfloat> %splat, <vscale x 16 x bfloat> %va157 ret <vscale x 16 x bfloat> %vc158}159 160define <vscale x 32 x bfloat> @vfmerge_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x i1> %cond) {161; CHECK-LABEL: vfmerge_vv_nxv32bf16:162; CHECK: # %bb.0:163; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma164; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0165; CHECK-NEXT: ret166 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb167 ret <vscale x 32 x bfloat> %vc168}169 170define <vscale x 32 x bfloat> @vfmerge_fv_nxv32bf16(<vscale x 32 x bfloat> %va, bfloat %b, <vscale x 32 x i1> %cond) {171; CHECK-LABEL: vfmerge_fv_nxv32bf16:172; CHECK: # %bb.0:173; CHECK-NEXT: fmv.x.h a0, fa0174; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma175; CHECK-NEXT: vmv.v.x v16, a0176; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0177; CHECK-NEXT: ret178 %head = insertelement <vscale x 32 x bfloat> poison, bfloat %b, i32 0179 %splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer180 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x bfloat> %splat, <vscale x 32 x bfloat> %va181 ret <vscale x 32 x bfloat> %vc182}183