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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,CHECK-ZVFH4; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,CHECK-ZVFH6; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,CHECK-ZVFHMIN8; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,CHECK-ZVFHMIN10 11define <vscale x 1 x half> @vfmerge_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x i1> %cond) {12; CHECK-LABEL: vfmerge_vv_nxv1f16:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma15; CHECK-NEXT: vmerge.vvm v8, v9, v8, v016; CHECK-NEXT: ret17 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %va, <vscale x 1 x half> %vb18 ret <vscale x 1 x half> %vc19}20 21define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %cond) {22; CHECK-ZVFH-LABEL: vfmerge_fv_nxv1f16:23; CHECK-ZVFH: # %bb.0:24; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma25; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v026; CHECK-ZVFH-NEXT: ret27;28; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv1f16:29; CHECK-ZVFHMIN: # %bb.0:30; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa031; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma32; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a033; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v034; CHECK-ZVFHMIN-NEXT: ret35 %head = insertelement <vscale x 1 x half> poison, half %b, i32 036 %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer37 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x half> %splat, <vscale x 1 x half> %va38 ret <vscale x 1 x half> %vc39}40 41define <vscale x 2 x half> @vfmerge_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %cond) {42; CHECK-LABEL: vfmerge_vv_nxv2f16:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma45; CHECK-NEXT: vmerge.vvm v8, v9, v8, v046; CHECK-NEXT: ret47 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %va, <vscale x 2 x half> %vb48 ret <vscale x 2 x half> %vc49}50 51define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b, <vscale x 2 x i1> %cond) {52; CHECK-ZVFH-LABEL: vfmerge_fv_nxv2f16:53; CHECK-ZVFH: # %bb.0:54; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma55; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v056; CHECK-ZVFH-NEXT: ret57;58; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv2f16:59; CHECK-ZVFHMIN: # %bb.0:60; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa061; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma62; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a063; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v064; CHECK-ZVFHMIN-NEXT: ret65 %head = insertelement <vscale x 2 x half> poison, half %b, i32 066 %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer67 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x half> %splat, <vscale x 2 x half> %va68 ret <vscale x 2 x half> %vc69}70 71define <vscale x 4 x half> @vfmerge_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x i1> %cond) {72; CHECK-LABEL: vfmerge_vv_nxv4f16:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma75; CHECK-NEXT: vmerge.vvm v8, v9, v8, v076; CHECK-NEXT: ret77 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %va, <vscale x 4 x half> %vb78 ret <vscale x 4 x half> %vc79}80 81define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b, <vscale x 4 x i1> %cond) {82; CHECK-ZVFH-LABEL: vfmerge_fv_nxv4f16:83; CHECK-ZVFH: # %bb.0:84; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma85; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v086; CHECK-ZVFH-NEXT: ret87;88; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv4f16:89; CHECK-ZVFHMIN: # %bb.0:90; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa091; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma92; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a093; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v094; CHECK-ZVFHMIN-NEXT: ret95 %head = insertelement <vscale x 4 x half> poison, half %b, i32 096 %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer97 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x half> %splat, <vscale x 4 x half> %va98 ret <vscale x 4 x half> %vc99}100 101define <vscale x 8 x half> @vfmerge_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %cond) {102; CHECK-LABEL: vfmerge_vv_nxv8f16:103; CHECK: # %bb.0:104; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma105; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0106; CHECK-NEXT: ret107 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %va, <vscale x 8 x half> %vb108 ret <vscale x 8 x half> %vc109}110 111define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %cond) {112; CHECK-ZVFH-LABEL: vfmerge_fv_nxv8f16:113; CHECK-ZVFH: # %bb.0:114; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma115; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0116; CHECK-ZVFH-NEXT: ret117;118; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv8f16:119; CHECK-ZVFHMIN: # %bb.0:120; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0121; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma122; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0123; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0124; CHECK-ZVFHMIN-NEXT: ret125 %head = insertelement <vscale x 8 x half> poison, half %b, i32 0126 %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer127 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> %splat, <vscale x 8 x half> %va128 ret <vscale x 8 x half> %vc129}130 131define <vscale x 8 x half> @vfmerge_zv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {132; CHECK-ZVFH-LABEL: vfmerge_zv_nxv8f16:133; CHECK-ZVFH: # %bb.0:134; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma135; CHECK-ZVFH-NEXT: vmerge.vim v8, v8, 0, v0136; CHECK-ZVFH-NEXT: ret137;138; CHECK-ZVFHMIN-LABEL: vfmerge_zv_nxv8f16:139; CHECK-ZVFHMIN: # %bb.0:140; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma141; CHECK-ZVFHMIN-NEXT: vmv.v.i v10, 0142; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0143; CHECK-ZVFHMIN-NEXT: ret144 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half zeroinitializer), <vscale x 8 x half> %va145 ret <vscale x 8 x half> %vc146}147 148define <vscale x 8 x half> @vfmerge_nzv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {149; CHECK-ZVFH-LABEL: vfmerge_nzv_nxv8f16:150; CHECK-ZVFH: # %bb.0:151; CHECK-ZVFH-NEXT: lui a0, 1048568152; CHECK-ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma153; CHECK-ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0154; CHECK-ZVFH-NEXT: ret155;156; CHECK-ZVFHMIN-LABEL: vfmerge_nzv_nxv8f16:157; CHECK-ZVFHMIN: # %bb.0:158; CHECK-ZVFHMIN-NEXT: lui a0, 1048568159; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma160; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0161; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0162; CHECK-ZVFHMIN-NEXT: ret163 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half -0.0), <vscale x 8 x half> %va164 ret <vscale x 8 x half> %vc165}166 167define <vscale x 8 x half> @vmerge_truelhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {168; CHECK-LABEL: vmerge_truelhs_nxv8f16_0:169; CHECK: # %bb.0:170; CHECK-NEXT: ret171 %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x half> %va, <vscale x 8 x half> %vb172 ret <vscale x 8 x half> %vc173}174 175define <vscale x 8 x half> @vmerge_falselhs_nxv8f16_0(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {176; CHECK-LABEL: vmerge_falselhs_nxv8f16_0:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma179; CHECK-NEXT: vmv2r.v v8, v10180; CHECK-NEXT: ret181 %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x half> %va, <vscale x 8 x half> %vb182 ret <vscale x 8 x half> %vc183}184 185define <vscale x 16 x half> @vfmerge_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x i1> %cond) {186; CHECK-LABEL: vfmerge_vv_nxv16f16:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma189; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0190; CHECK-NEXT: ret191 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %va, <vscale x 16 x half> %vb192 ret <vscale x 16 x half> %vc193}194 195define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half %b, <vscale x 16 x i1> %cond) {196; CHECK-ZVFH-LABEL: vfmerge_fv_nxv16f16:197; CHECK-ZVFH: # %bb.0:198; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma199; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0200; CHECK-ZVFH-NEXT: ret201;202; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv16f16:203; CHECK-ZVFHMIN: # %bb.0:204; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0205; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma206; CHECK-ZVFHMIN-NEXT: vmv.v.x v12, a0207; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0208; CHECK-ZVFHMIN-NEXT: ret209 %head = insertelement <vscale x 16 x half> poison, half %b, i32 0210 %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer211 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x half> %splat, <vscale x 16 x half> %va212 ret <vscale x 16 x half> %vc213}214 215define <vscale x 32 x half> @vfmerge_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x i1> %cond) {216; CHECK-LABEL: vfmerge_vv_nxv32f16:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma219; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0220; CHECK-NEXT: ret221 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %va, <vscale x 32 x half> %vb222 ret <vscale x 32 x half> %vc223}224 225define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half %b, <vscale x 32 x i1> %cond) {226; CHECK-ZVFH-LABEL: vfmerge_fv_nxv32f16:227; CHECK-ZVFH: # %bb.0:228; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma229; CHECK-ZVFH-NEXT: vfmerge.vfm v8, v8, fa0, v0230; CHECK-ZVFH-NEXT: ret231;232; CHECK-ZVFHMIN-LABEL: vfmerge_fv_nxv32f16:233; CHECK-ZVFHMIN: # %bb.0:234; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0235; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma236; CHECK-ZVFHMIN-NEXT: vmv.v.x v16, a0237; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0238; CHECK-ZVFHMIN-NEXT: ret239 %head = insertelement <vscale x 32 x half> poison, half %b, i32 0240 %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer241 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x half> %splat, <vscale x 32 x half> %va242 ret <vscale x 32 x half> %vc243}244 245define <vscale x 1 x float> @vfmerge_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x i1> %cond) {246; CHECK-LABEL: vfmerge_vv_nxv1f32:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma249; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0250; CHECK-NEXT: ret251 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x float> %va, <vscale x 1 x float> %vb252 ret <vscale x 1 x float> %vc253}254 255define <vscale x 1 x float> @vfmerge_fv_nxv1f32(<vscale x 1 x float> %va, float %b, <vscale x 1 x i1> %cond) {256; CHECK-LABEL: vfmerge_fv_nxv1f32:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma259; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0260; CHECK-NEXT: ret261 %head = insertelement <vscale x 1 x float> poison, float %b, i32 0262 %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer263 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x float> %splat, <vscale x 1 x float> %va264 ret <vscale x 1 x float> %vc265}266 267define <vscale x 2 x float> @vfmerge_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %cond) {268; CHECK-LABEL: vfmerge_vv_nxv2f32:269; CHECK: # %bb.0:270; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma271; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0272; CHECK-NEXT: ret273 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x float> %va, <vscale x 2 x float> %vb274 ret <vscale x 2 x float> %vc275}276 277define <vscale x 2 x float> @vfmerge_fv_nxv2f32(<vscale x 2 x float> %va, float %b, <vscale x 2 x i1> %cond) {278; CHECK-LABEL: vfmerge_fv_nxv2f32:279; CHECK: # %bb.0:280; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma281; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0282; CHECK-NEXT: ret283 %head = insertelement <vscale x 2 x float> poison, float %b, i32 0284 %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer285 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x float> %splat, <vscale x 2 x float> %va286 ret <vscale x 2 x float> %vc287}288 289define <vscale x 4 x float> @vfmerge_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x i1> %cond) {290; CHECK-LABEL: vfmerge_vv_nxv4f32:291; CHECK: # %bb.0:292; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma293; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0294; CHECK-NEXT: ret295 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %va, <vscale x 4 x float> %vb296 ret <vscale x 4 x float> %vc297}298 299define <vscale x 4 x float> @vfmerge_fv_nxv4f32(<vscale x 4 x float> %va, float %b, <vscale x 4 x i1> %cond) {300; CHECK-LABEL: vfmerge_fv_nxv4f32:301; CHECK: # %bb.0:302; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma303; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0304; CHECK-NEXT: ret305 %head = insertelement <vscale x 4 x float> poison, float %b, i32 0306 %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer307 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x float> %splat, <vscale x 4 x float> %va308 ret <vscale x 4 x float> %vc309}310 311define <vscale x 8 x float> @vfmerge_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x i1> %cond) {312; CHECK-LABEL: vfmerge_vv_nxv8f32:313; CHECK: # %bb.0:314; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma315; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0316; CHECK-NEXT: ret317 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> %va, <vscale x 8 x float> %vb318 ret <vscale x 8 x float> %vc319}320 321define <vscale x 8 x float> @vfmerge_fv_nxv8f32(<vscale x 8 x float> %va, float %b, <vscale x 8 x i1> %cond) {322; CHECK-LABEL: vfmerge_fv_nxv8f32:323; CHECK: # %bb.0:324; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma325; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0326; CHECK-NEXT: ret327 %head = insertelement <vscale x 8 x float> poison, float %b, i32 0328 %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer329 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> %splat, <vscale x 8 x float> %va330 ret <vscale x 8 x float> %vc331}332 333define <vscale x 8 x float> @vfmerge_zv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %cond) {334; CHECK-LABEL: vfmerge_zv_nxv8f32:335; CHECK: # %bb.0:336; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma337; CHECK-NEXT: vmerge.vim v8, v8, 0, v0338; CHECK-NEXT: ret339 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> splat (float zeroinitializer), <vscale x 8 x float> %va340 ret <vscale x 8 x float> %vc341}342 343define <vscale x 8 x float> @vfmerge_nzv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %cond) {344; CHECK-LABEL: vfmerge_nzv_nxv8f32:345; CHECK: # %bb.0:346; CHECK-NEXT: lui a0, 524288347; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma348; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0349; CHECK-NEXT: ret350 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x float> splat (float -0.0), <vscale x 8 x float> %va351 ret <vscale x 8 x float> %vc352}353 354define <vscale x 16 x float> @vfmerge_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x i1> %cond) {355; CHECK-LABEL: vfmerge_vv_nxv16f32:356; CHECK: # %bb.0:357; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma358; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0359; CHECK-NEXT: ret360 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x float> %va, <vscale x 16 x float> %vb361 ret <vscale x 16 x float> %vc362}363 364define <vscale x 16 x float> @vfmerge_fv_nxv16f32(<vscale x 16 x float> %va, float %b, <vscale x 16 x i1> %cond) {365; CHECK-LABEL: vfmerge_fv_nxv16f32:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma368; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0369; CHECK-NEXT: ret370 %head = insertelement <vscale x 16 x float> poison, float %b, i32 0371 %splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer372 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x float> %splat, <vscale x 16 x float> %va373 ret <vscale x 16 x float> %vc374}375 376define <vscale x 1 x double> @vfmerge_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %cond) {377; CHECK-LABEL: vfmerge_vv_nxv1f64:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma380; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0381; CHECK-NEXT: ret382 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x double> %va, <vscale x 1 x double> %vb383 ret <vscale x 1 x double> %vc384}385 386define <vscale x 1 x double> @vfmerge_fv_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %cond) {387; CHECK-LABEL: vfmerge_fv_nxv1f64:388; CHECK: # %bb.0:389; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma390; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0391; CHECK-NEXT: ret392 %head = insertelement <vscale x 1 x double> poison, double %b, i32 0393 %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer394 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x double> %splat, <vscale x 1 x double> %va395 ret <vscale x 1 x double> %vc396}397 398define <vscale x 2 x double> @vfmerge_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x i1> %cond) {399; CHECK-LABEL: vfmerge_vv_nxv2f64:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma402; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0403; CHECK-NEXT: ret404 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x double> %va, <vscale x 2 x double> %vb405 ret <vscale x 2 x double> %vc406}407 408define <vscale x 2 x double> @vfmerge_fv_nxv2f64(<vscale x 2 x double> %va, double %b, <vscale x 2 x i1> %cond) {409; CHECK-LABEL: vfmerge_fv_nxv2f64:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma412; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0413; CHECK-NEXT: ret414 %head = insertelement <vscale x 2 x double> poison, double %b, i32 0415 %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer416 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x double> %splat, <vscale x 2 x double> %va417 ret <vscale x 2 x double> %vc418}419 420define <vscale x 4 x double> @vfmerge_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x i1> %cond) {421; CHECK-LABEL: vfmerge_vv_nxv4f64:422; CHECK: # %bb.0:423; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma424; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0425; CHECK-NEXT: ret426 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x double> %va, <vscale x 4 x double> %vb427 ret <vscale x 4 x double> %vc428}429 430define <vscale x 4 x double> @vfmerge_fv_nxv4f64(<vscale x 4 x double> %va, double %b, <vscale x 4 x i1> %cond) {431; CHECK-LABEL: vfmerge_fv_nxv4f64:432; CHECK: # %bb.0:433; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma434; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0435; CHECK-NEXT: ret436 %head = insertelement <vscale x 4 x double> poison, double %b, i32 0437 %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer438 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x double> %splat, <vscale x 4 x double> %va439 ret <vscale x 4 x double> %vc440}441 442define <vscale x 8 x double> @vfmerge_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %cond) {443; CHECK-LABEL: vfmerge_vv_nxv8f64:444; CHECK: # %bb.0:445; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma446; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0447; CHECK-NEXT: ret448 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> %va, <vscale x 8 x double> %vb449 ret <vscale x 8 x double> %vc450}451 452define <vscale x 8 x double> @vfmerge_fv_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %cond) {453; CHECK-LABEL: vfmerge_fv_nxv8f64:454; CHECK: # %bb.0:455; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma456; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0457; CHECK-NEXT: ret458 %head = insertelement <vscale x 8 x double> poison, double %b, i32 0459 %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer460 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> %splat, <vscale x 8 x double> %va461 ret <vscale x 8 x double> %vc462}463 464define <vscale x 8 x double> @vfmerge_zv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %cond) {465; CHECK-LABEL: vfmerge_zv_nxv8f64:466; CHECK: # %bb.0:467; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma468; CHECK-NEXT: vmerge.vim v8, v8, 0, v0469; CHECK-NEXT: ret470 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> splat (double zeroinitializer), <vscale x 8 x double> %va471 ret <vscale x 8 x double> %vc472}473 474define <vscale x 8 x double> @vfmerge_nzv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %cond) {475; RV32-LABEL: vfmerge_nzv_nxv8f64:476; RV32: # %bb.0:477; RV32-NEXT: fcvt.d.w fa5, zero478; RV32-NEXT: fneg.d fa5, fa5479; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma480; RV32-NEXT: vfmerge.vfm v8, v8, fa5, v0481; RV32-NEXT: ret482;483; RV64-LABEL: vfmerge_nzv_nxv8f64:484; RV64: # %bb.0:485; RV64-NEXT: li a0, -1486; RV64-NEXT: slli a0, a0, 63487; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma488; RV64-NEXT: vmerge.vxm v8, v8, a0, v0489; RV64-NEXT: ret490 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x double> splat (double -0.0), <vscale x 8 x double> %va491 ret <vscale x 8 x double> %vc492}493 494define <vscale x 16 x double> @vselect_combine_regression(<vscale x 16 x i64> %va, <vscale x 16 x double> %vb) {495; CHECK-LABEL: vselect_combine_regression:496; CHECK: # %bb.0:497; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, mu498; CHECK-NEXT: vmv8r.v v24, v16499; CHECK-NEXT: vmseq.vi v0, v8, 0500; CHECK-NEXT: vmv.v.i v16, 0501; CHECK-NEXT: vmv.v.i v8, 0502; CHECK-NEXT: vle64.v v8, (a0), v0.t503; CHECK-NEXT: vmseq.vi v0, v24, 0504; CHECK-NEXT: csrr a1, vlenb505; CHECK-NEXT: slli a1, a1, 3506; CHECK-NEXT: add a0, a0, a1507; CHECK-NEXT: vle64.v v16, (a0), v0.t508; CHECK-NEXT: ret509 %cond = icmp eq <vscale x 16 x i64> %va, zeroinitializer510 %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %vb, <vscale x 16 x double> zeroinitializer511 ret <vscale x 16 x double> %sel512}513 514define void @vselect_legalize_regression(<vscale x 16 x double> %a, <vscale x 16 x i1> %ma, <vscale x 16 x i1> %mb, ptr %out) {515; CHECK-LABEL: vselect_legalize_regression:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma518; CHECK-NEXT: vlm.v v7, (a0)519; CHECK-NEXT: csrr a0, vlenb520; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma521; CHECK-NEXT: vmv.v.i v24, 0522; CHECK-NEXT: srli a2, a0, 3523; CHECK-NEXT: slli a0, a0, 3524; CHECK-NEXT: vsetvli a3, zero, e8, m2, ta, ma525; CHECK-NEXT: vmand.mm v7, v0, v7526; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma527; CHECK-NEXT: vslidedown.vx v0, v7, a2528; CHECK-NEXT: add a0, a1, a0529; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma530; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0531; CHECK-NEXT: vmv1r.v v0, v7532; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0533; CHECK-NEXT: vs8r.v v8, (a1)534; CHECK-NEXT: vs8r.v v16, (a0)535; CHECK-NEXT: ret536 %cond = and <vscale x 16 x i1> %ma, %mb537 %sel = select <vscale x 16 x i1> %cond, <vscale x 16 x double> %a, <vscale x 16 x double> zeroinitializer538 store <vscale x 16 x double> %sel, ptr %out539 ret void540}541