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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @vmerge_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %cond) {8; CHECK-LABEL: vmerge_vv_nxv1i8:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma11; CHECK-NEXT: vmerge.vvm v8, v9, v8, v012; CHECK-NEXT: ret13 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %va, <vscale x 1 x i8> %vb14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vmerge_xv_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b, <vscale x 1 x i1> %cond) {18; CHECK-LABEL: vmerge_xv_nxv1i8:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma21; CHECK-NEXT: vmerge.vxm v8, v8, a0, v022; CHECK-NEXT: ret23 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 024 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer25 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> %splat, <vscale x 1 x i8> %va26 ret <vscale x 1 x i8> %vc27}28 29define <vscale x 1 x i8> @vmerge_iv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %cond) {30; CHECK-LABEL: vmerge_iv_nxv1i8:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma33; CHECK-NEXT: vmerge.vim v8, v8, 3, v034; CHECK-NEXT: ret35 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i8> splat (i8 3), <vscale x 1 x i8> %va36 ret <vscale x 1 x i8> %vc37}38 39define <vscale x 2 x i8> @vmerge_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %cond) {40; CHECK-LABEL: vmerge_vv_nxv2i8:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma43; CHECK-NEXT: vmerge.vvm v8, v9, v8, v044; CHECK-NEXT: ret45 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> %va, <vscale x 2 x i8> %vb46 ret <vscale x 2 x i8> %vc47}48 49define <vscale x 2 x i8> @vmerge_xv_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b, <vscale x 2 x i1> %cond) {50; CHECK-LABEL: vmerge_xv_nxv2i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma53; CHECK-NEXT: vmerge.vxm v8, v8, a0, v054; CHECK-NEXT: ret55 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 056 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer57 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> %splat, <vscale x 2 x i8> %va58 ret <vscale x 2 x i8> %vc59}60 61define <vscale x 2 x i8> @vmerge_iv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %cond) {62; CHECK-LABEL: vmerge_iv_nxv2i8:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma65; CHECK-NEXT: vmerge.vim v8, v8, 3, v066; CHECK-NEXT: ret67 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i8> splat (i8 3), <vscale x 2 x i8> %va68 ret <vscale x 2 x i8> %vc69}70 71define <vscale x 3 x i8> @vmerge_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %cond) {72; CHECK-LABEL: vmerge_vv_nxv3i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma75; CHECK-NEXT: vmerge.vvm v8, v9, v8, v076; CHECK-NEXT: ret77 %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %va, <vscale x 3 x i8> %vb78 ret <vscale x 3 x i8> %vc79}80 81define <vscale x 3 x i8> @vmerge_xv_nxv3i8(<vscale x 3 x i8> %va, i8 signext %b, <vscale x 3 x i1> %cond) {82; CHECK-LABEL: vmerge_xv_nxv3i8:83; CHECK: # %bb.0:84; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma85; CHECK-NEXT: vmerge.vxm v8, v8, a0, v086; CHECK-NEXT: ret87 %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 088 %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer89 %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> %splat, <vscale x 3 x i8> %va90 ret <vscale x 3 x i8> %vc91}92 93define <vscale x 3 x i8> @vmerge_iv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i1> %cond) {94; CHECK-LABEL: vmerge_iv_nxv3i8:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma97; CHECK-NEXT: vmerge.vim v8, v8, 3, v098; CHECK-NEXT: ret99 %vc = select <vscale x 3 x i1> %cond, <vscale x 3 x i8> splat (i8 3), <vscale x 3 x i8> %va100 ret <vscale x 3 x i8> %vc101}102 103define <vscale x 4 x i8> @vmerge_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %cond) {104; CHECK-LABEL: vmerge_vv_nxv4i8:105; CHECK: # %bb.0:106; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma107; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0108; CHECK-NEXT: ret109 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> %va, <vscale x 4 x i8> %vb110 ret <vscale x 4 x i8> %vc111}112 113define <vscale x 4 x i8> @vmerge_xv_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b, <vscale x 4 x i1> %cond) {114; CHECK-LABEL: vmerge_xv_nxv4i8:115; CHECK: # %bb.0:116; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma117; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0118; CHECK-NEXT: ret119 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0120 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer121 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> %splat, <vscale x 4 x i8> %va122 ret <vscale x 4 x i8> %vc123}124 125define <vscale x 4 x i8> @vmerge_iv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %cond) {126; CHECK-LABEL: vmerge_iv_nxv4i8:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma129; CHECK-NEXT: vmerge.vim v8, v8, 3, v0130; CHECK-NEXT: ret131 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i8> splat (i8 3), <vscale x 4 x i8> %va132 ret <vscale x 4 x i8> %vc133}134 135define <vscale x 8 x i8> @vmerge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %cond) {136; CHECK-LABEL: vmerge_vv_nxv8i8:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma139; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0140; CHECK-NEXT: ret141 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> %va, <vscale x 8 x i8> %vb142 ret <vscale x 8 x i8> %vc143}144 145define <vscale x 8 x i8> @vmerge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b, <vscale x 8 x i1> %cond) {146; CHECK-LABEL: vmerge_xv_nxv8i8:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma149; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0150; CHECK-NEXT: ret151 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0152 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer153 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> %splat, <vscale x 8 x i8> %va154 ret <vscale x 8 x i8> %vc155}156 157define <vscale x 8 x i8> @vmerge_iv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %cond) {158; CHECK-LABEL: vmerge_iv_nxv8i8:159; CHECK: # %bb.0:160; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma161; CHECK-NEXT: vmerge.vim v8, v8, 3, v0162; CHECK-NEXT: ret163 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i8> splat (i8 3), <vscale x 8 x i8> %va164 ret <vscale x 8 x i8> %vc165}166 167define <vscale x 16 x i8> @vmerge_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %cond) {168; CHECK-LABEL: vmerge_vv_nxv16i8:169; CHECK: # %bb.0:170; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma171; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0172; CHECK-NEXT: ret173 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> %va, <vscale x 16 x i8> %vb174 ret <vscale x 16 x i8> %vc175}176 177define <vscale x 16 x i8> @vmerge_xv_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b, <vscale x 16 x i1> %cond) {178; CHECK-LABEL: vmerge_xv_nxv16i8:179; CHECK: # %bb.0:180; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma181; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0182; CHECK-NEXT: ret183 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0184 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer185 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> %splat, <vscale x 16 x i8> %va186 ret <vscale x 16 x i8> %vc187}188 189define <vscale x 16 x i8> @vmerge_iv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %cond) {190; CHECK-LABEL: vmerge_iv_nxv16i8:191; CHECK: # %bb.0:192; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma193; CHECK-NEXT: vmerge.vim v8, v8, 3, v0194; CHECK-NEXT: ret195 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i8> splat (i8 3), <vscale x 16 x i8> %va196 ret <vscale x 16 x i8> %vc197}198 199define <vscale x 32 x i8> @vmerge_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %cond) {200; CHECK-LABEL: vmerge_vv_nxv32i8:201; CHECK: # %bb.0:202; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma203; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0204; CHECK-NEXT: ret205 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> %va, <vscale x 32 x i8> %vb206 ret <vscale x 32 x i8> %vc207}208 209define <vscale x 32 x i8> @vmerge_xv_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b, <vscale x 32 x i1> %cond) {210; CHECK-LABEL: vmerge_xv_nxv32i8:211; CHECK: # %bb.0:212; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma213; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0214; CHECK-NEXT: ret215 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0216 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer217 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> %splat, <vscale x 32 x i8> %va218 ret <vscale x 32 x i8> %vc219}220 221define <vscale x 32 x i8> @vmerge_iv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %cond) {222; CHECK-LABEL: vmerge_iv_nxv32i8:223; CHECK: # %bb.0:224; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma225; CHECK-NEXT: vmerge.vim v8, v8, 3, v0226; CHECK-NEXT: ret227 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i8> splat (i8 3), <vscale x 32 x i8> %va228 ret <vscale x 32 x i8> %vc229}230 231define <vscale x 64 x i8> @vmerge_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %cond) {232; CHECK-LABEL: vmerge_vv_nxv64i8:233; CHECK: # %bb.0:234; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma235; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0236; CHECK-NEXT: ret237 %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> %va, <vscale x 64 x i8> %vb238 ret <vscale x 64 x i8> %vc239}240 241define <vscale x 64 x i8> @vmerge_xv_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b, <vscale x 64 x i1> %cond) {242; CHECK-LABEL: vmerge_xv_nxv64i8:243; CHECK: # %bb.0:244; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma245; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0246; CHECK-NEXT: ret247 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0248 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer249 %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> %splat, <vscale x 64 x i8> %va250 ret <vscale x 64 x i8> %vc251}252 253define <vscale x 64 x i8> @vmerge_iv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %cond) {254; CHECK-LABEL: vmerge_iv_nxv64i8:255; CHECK: # %bb.0:256; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma257; CHECK-NEXT: vmerge.vim v8, v8, 3, v0258; CHECK-NEXT: ret259 %vc = select <vscale x 64 x i1> %cond, <vscale x 64 x i8> splat (i8 3), <vscale x 64 x i8> %va260 ret <vscale x 64 x i8> %vc261}262 263define <vscale x 1 x i16> @vmerge_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %cond) {264; CHECK-LABEL: vmerge_vv_nxv1i16:265; CHECK: # %bb.0:266; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma267; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0268; CHECK-NEXT: ret269 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> %va, <vscale x 1 x i16> %vb270 ret <vscale x 1 x i16> %vc271}272 273define <vscale x 1 x i16> @vmerge_xv_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b, <vscale x 1 x i1> %cond) {274; CHECK-LABEL: vmerge_xv_nxv1i16:275; CHECK: # %bb.0:276; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma277; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0278; CHECK-NEXT: ret279 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0280 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer281 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> %splat, <vscale x 1 x i16> %va282 ret <vscale x 1 x i16> %vc283}284 285define <vscale x 1 x i16> @vmerge_iv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %cond) {286; CHECK-LABEL: vmerge_iv_nxv1i16:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma289; CHECK-NEXT: vmerge.vim v8, v8, 3, v0290; CHECK-NEXT: ret291 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i16> splat (i16 3), <vscale x 1 x i16> %va292 ret <vscale x 1 x i16> %vc293}294 295define <vscale x 2 x i16> @vmerge_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %cond) {296; CHECK-LABEL: vmerge_vv_nxv2i16:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma299; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0300; CHECK-NEXT: ret301 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> %va, <vscale x 2 x i16> %vb302 ret <vscale x 2 x i16> %vc303}304 305define <vscale x 2 x i16> @vmerge_xv_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b, <vscale x 2 x i1> %cond) {306; CHECK-LABEL: vmerge_xv_nxv2i16:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma309; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0310; CHECK-NEXT: ret311 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0312 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer313 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> %splat, <vscale x 2 x i16> %va314 ret <vscale x 2 x i16> %vc315}316 317define <vscale x 2 x i16> @vmerge_iv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %cond) {318; CHECK-LABEL: vmerge_iv_nxv2i16:319; CHECK: # %bb.0:320; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma321; CHECK-NEXT: vmerge.vim v8, v8, 3, v0322; CHECK-NEXT: ret323 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i16> splat (i16 3), <vscale x 2 x i16> %va324 ret <vscale x 2 x i16> %vc325}326 327define <vscale x 4 x i16> @vmerge_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %cond) {328; CHECK-LABEL: vmerge_vv_nxv4i16:329; CHECK: # %bb.0:330; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma331; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0332; CHECK-NEXT: ret333 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> %va, <vscale x 4 x i16> %vb334 ret <vscale x 4 x i16> %vc335}336 337define <vscale x 4 x i16> @vmerge_xv_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b, <vscale x 4 x i1> %cond) {338; CHECK-LABEL: vmerge_xv_nxv4i16:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma341; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0342; CHECK-NEXT: ret343 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0344 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer345 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> %splat, <vscale x 4 x i16> %va346 ret <vscale x 4 x i16> %vc347}348 349define <vscale x 4 x i16> @vmerge_iv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %cond) {350; CHECK-LABEL: vmerge_iv_nxv4i16:351; CHECK: # %bb.0:352; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma353; CHECK-NEXT: vmerge.vim v8, v8, 3, v0354; CHECK-NEXT: ret355 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i16> splat (i16 3), <vscale x 4 x i16> %va356 ret <vscale x 4 x i16> %vc357}358 359define <vscale x 8 x i16> @vmerge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %cond) {360; CHECK-LABEL: vmerge_vv_nxv8i16:361; CHECK: # %bb.0:362; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma363; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0364; CHECK-NEXT: ret365 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> %va, <vscale x 8 x i16> %vb366 ret <vscale x 8 x i16> %vc367}368 369define <vscale x 8 x i16> @vmerge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b, <vscale x 8 x i1> %cond) {370; CHECK-LABEL: vmerge_xv_nxv8i16:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma373; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0374; CHECK-NEXT: ret375 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0376 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer377 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> %splat, <vscale x 8 x i16> %va378 ret <vscale x 8 x i16> %vc379}380 381define <vscale x 8 x i16> @vmerge_iv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %cond) {382; CHECK-LABEL: vmerge_iv_nxv8i16:383; CHECK: # %bb.0:384; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma385; CHECK-NEXT: vmerge.vim v8, v8, 3, v0386; CHECK-NEXT: ret387 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i16> splat (i16 3), <vscale x 8 x i16> %va388 ret <vscale x 8 x i16> %vc389}390 391define <vscale x 16 x i16> @vmerge_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %cond) {392; CHECK-LABEL: vmerge_vv_nxv16i16:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma395; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0396; CHECK-NEXT: ret397 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> %va, <vscale x 16 x i16> %vb398 ret <vscale x 16 x i16> %vc399}400 401define <vscale x 16 x i16> @vmerge_xv_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b, <vscale x 16 x i1> %cond) {402; CHECK-LABEL: vmerge_xv_nxv16i16:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma405; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0406; CHECK-NEXT: ret407 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0408 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer409 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> %splat, <vscale x 16 x i16> %va410 ret <vscale x 16 x i16> %vc411}412 413define <vscale x 16 x i16> @vmerge_iv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %cond) {414; CHECK-LABEL: vmerge_iv_nxv16i16:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma417; CHECK-NEXT: vmerge.vim v8, v8, 3, v0418; CHECK-NEXT: ret419 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i16> splat (i16 3), <vscale x 16 x i16> %va420 ret <vscale x 16 x i16> %vc421}422 423define <vscale x 32 x i16> @vmerge_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %cond) {424; CHECK-LABEL: vmerge_vv_nxv32i16:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma427; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0428; CHECK-NEXT: ret429 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> %va, <vscale x 32 x i16> %vb430 ret <vscale x 32 x i16> %vc431}432 433define <vscale x 32 x i16> @vmerge_xv_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b, <vscale x 32 x i1> %cond) {434; CHECK-LABEL: vmerge_xv_nxv32i16:435; CHECK: # %bb.0:436; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma437; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0438; CHECK-NEXT: ret439 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0440 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer441 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> %splat, <vscale x 32 x i16> %va442 ret <vscale x 32 x i16> %vc443}444 445define <vscale x 32 x i16> @vmerge_iv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %cond) {446; CHECK-LABEL: vmerge_iv_nxv32i16:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma449; CHECK-NEXT: vmerge.vim v8, v8, 3, v0450; CHECK-NEXT: ret451 %vc = select <vscale x 32 x i1> %cond, <vscale x 32 x i16> splat (i16 3), <vscale x 32 x i16> %va452 ret <vscale x 32 x i16> %vc453}454 455define <vscale x 1 x i32> @vmerge_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %cond) {456; CHECK-LABEL: vmerge_vv_nxv1i32:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma459; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0460; CHECK-NEXT: ret461 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> %va, <vscale x 1 x i32> %vb462 ret <vscale x 1 x i32> %vc463}464 465define <vscale x 1 x i32> @vmerge_xv_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b, <vscale x 1 x i1> %cond) {466; CHECK-LABEL: vmerge_xv_nxv1i32:467; CHECK: # %bb.0:468; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma469; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0470; CHECK-NEXT: ret471 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0472 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer473 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> %splat, <vscale x 1 x i32> %va474 ret <vscale x 1 x i32> %vc475}476 477define <vscale x 1 x i32> @vmerge_iv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %cond) {478; CHECK-LABEL: vmerge_iv_nxv1i32:479; CHECK: # %bb.0:480; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma481; CHECK-NEXT: vmerge.vim v8, v8, 3, v0482; CHECK-NEXT: ret483 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i32> splat (i32 3), <vscale x 1 x i32> %va484 ret <vscale x 1 x i32> %vc485}486 487define <vscale x 2 x i32> @vmerge_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %cond) {488; CHECK-LABEL: vmerge_vv_nxv2i32:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma491; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0492; CHECK-NEXT: ret493 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> %va, <vscale x 2 x i32> %vb494 ret <vscale x 2 x i32> %vc495}496 497define <vscale x 2 x i32> @vmerge_xv_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b, <vscale x 2 x i1> %cond) {498; CHECK-LABEL: vmerge_xv_nxv2i32:499; CHECK: # %bb.0:500; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma501; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0502; CHECK-NEXT: ret503 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0504 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer505 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> %splat, <vscale x 2 x i32> %va506 ret <vscale x 2 x i32> %vc507}508 509define <vscale x 2 x i32> @vmerge_iv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %cond) {510; CHECK-LABEL: vmerge_iv_nxv2i32:511; CHECK: # %bb.0:512; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma513; CHECK-NEXT: vmerge.vim v8, v8, 3, v0514; CHECK-NEXT: ret515 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i32> splat (i32 3), <vscale x 2 x i32> %va516 ret <vscale x 2 x i32> %vc517}518 519define <vscale x 4 x i32> @vmerge_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %cond) {520; CHECK-LABEL: vmerge_vv_nxv4i32:521; CHECK: # %bb.0:522; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma523; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0524; CHECK-NEXT: ret525 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> %va, <vscale x 4 x i32> %vb526 ret <vscale x 4 x i32> %vc527}528 529define <vscale x 4 x i32> @vmerge_xv_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b, <vscale x 4 x i1> %cond) {530; CHECK-LABEL: vmerge_xv_nxv4i32:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma533; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0534; CHECK-NEXT: ret535 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0536 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer537 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> %splat, <vscale x 4 x i32> %va538 ret <vscale x 4 x i32> %vc539}540 541define <vscale x 4 x i32> @vmerge_iv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %cond) {542; CHECK-LABEL: vmerge_iv_nxv4i32:543; CHECK: # %bb.0:544; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma545; CHECK-NEXT: vmerge.vim v8, v8, 3, v0546; CHECK-NEXT: ret547 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> %va548 ret <vscale x 4 x i32> %vc549}550 551define <vscale x 8 x i32> @vmerge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %cond) {552; CHECK-LABEL: vmerge_vv_nxv8i32:553; CHECK: # %bb.0:554; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma555; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0556; CHECK-NEXT: ret557 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vb558 ret <vscale x 8 x i32> %vc559}560 561define <vscale x 8 x i32> @vmerge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %cond) {562; CHECK-LABEL: vmerge_xv_nxv8i32:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma565; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0566; CHECK-NEXT: ret567 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0568 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer569 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %va570 ret <vscale x 8 x i32> %vc571}572 573define <vscale x 8 x i32> @vmerge_iv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %cond) {574; CHECK-LABEL: vmerge_iv_nxv8i32:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma577; CHECK-NEXT: vmerge.vim v8, v8, 3, v0578; CHECK-NEXT: ret579 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i32> splat (i32 3), <vscale x 8 x i32> %va580 ret <vscale x 8 x i32> %vc581}582 583define <vscale x 16 x i32> @vmerge_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %cond) {584; CHECK-LABEL: vmerge_vv_nxv16i32:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma587; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0588; CHECK-NEXT: ret589 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> %va, <vscale x 16 x i32> %vb590 ret <vscale x 16 x i32> %vc591}592 593define <vscale x 16 x i32> @vmerge_xv_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b, <vscale x 16 x i1> %cond) {594; CHECK-LABEL: vmerge_xv_nxv16i32:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma597; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0598; CHECK-NEXT: ret599 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0600 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer601 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> %splat, <vscale x 16 x i32> %va602 ret <vscale x 16 x i32> %vc603}604 605define <vscale x 16 x i32> @vmerge_iv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %cond) {606; CHECK-LABEL: vmerge_iv_nxv16i32:607; CHECK: # %bb.0:608; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma609; CHECK-NEXT: vmerge.vim v8, v8, 3, v0610; CHECK-NEXT: ret611 %vc = select <vscale x 16 x i1> %cond, <vscale x 16 x i32> splat (i32 3), <vscale x 16 x i32> %va612 ret <vscale x 16 x i32> %vc613}614 615define <vscale x 1 x i64> @vmerge_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %cond) {616; CHECK-LABEL: vmerge_vv_nxv1i64:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma619; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0620; CHECK-NEXT: ret621 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %va, <vscale x 1 x i64> %vb622 ret <vscale x 1 x i64> %vc623}624 625define <vscale x 1 x i64> @vmerge_xv_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %cond) {626; RV32-LABEL: vmerge_xv_nxv1i64:627; RV32: # %bb.0:628; RV32-NEXT: addi sp, sp, -16629; RV32-NEXT: .cfi_def_cfa_offset 16630; RV32-NEXT: sw a0, 8(sp)631; RV32-NEXT: sw a1, 12(sp)632; RV32-NEXT: addi a0, sp, 8633; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, mu634; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t635; RV32-NEXT: addi sp, sp, 16636; RV32-NEXT: .cfi_def_cfa_offset 0637; RV32-NEXT: ret638;639; RV64-LABEL: vmerge_xv_nxv1i64:640; RV64: # %bb.0:641; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma642; RV64-NEXT: vmerge.vxm v8, v8, a0, v0643; RV64-NEXT: ret644 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0645 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer646 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> %splat, <vscale x 1 x i64> %va647 ret <vscale x 1 x i64> %vc648}649 650define <vscale x 1 x i64> @vmerge_iv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %cond) {651; CHECK-LABEL: vmerge_iv_nxv1i64:652; CHECK: # %bb.0:653; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma654; CHECK-NEXT: vmerge.vim v8, v8, 3, v0655; CHECK-NEXT: ret656 %vc = select <vscale x 1 x i1> %cond, <vscale x 1 x i64> splat (i64 3), <vscale x 1 x i64> %va657 ret <vscale x 1 x i64> %vc658}659 660define <vscale x 2 x i64> @vmerge_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %cond) {661; CHECK-LABEL: vmerge_vv_nxv2i64:662; CHECK: # %bb.0:663; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma664; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0665; CHECK-NEXT: ret666 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %va, <vscale x 2 x i64> %vb667 ret <vscale x 2 x i64> %vc668}669 670define <vscale x 2 x i64> @vmerge_xv_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %cond) {671; RV32-LABEL: vmerge_xv_nxv2i64:672; RV32: # %bb.0:673; RV32-NEXT: addi sp, sp, -16674; RV32-NEXT: .cfi_def_cfa_offset 16675; RV32-NEXT: sw a0, 8(sp)676; RV32-NEXT: sw a1, 12(sp)677; RV32-NEXT: addi a0, sp, 8678; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, mu679; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t680; RV32-NEXT: addi sp, sp, 16681; RV32-NEXT: .cfi_def_cfa_offset 0682; RV32-NEXT: ret683;684; RV64-LABEL: vmerge_xv_nxv2i64:685; RV64: # %bb.0:686; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma687; RV64-NEXT: vmerge.vxm v8, v8, a0, v0688; RV64-NEXT: ret689 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0690 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer691 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> %splat, <vscale x 2 x i64> %va692 ret <vscale x 2 x i64> %vc693}694 695define <vscale x 2 x i64> @vmerge_iv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %cond) {696; CHECK-LABEL: vmerge_iv_nxv2i64:697; CHECK: # %bb.0:698; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma699; CHECK-NEXT: vmerge.vim v8, v8, 3, v0700; CHECK-NEXT: ret701 %vc = select <vscale x 2 x i1> %cond, <vscale x 2 x i64> splat (i64 3), <vscale x 2 x i64> %va702 ret <vscale x 2 x i64> %vc703}704 705define <vscale x 4 x i64> @vmerge_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %cond) {706; CHECK-LABEL: vmerge_vv_nxv4i64:707; CHECK: # %bb.0:708; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma709; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0710; CHECK-NEXT: ret711 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %va, <vscale x 4 x i64> %vb712 ret <vscale x 4 x i64> %vc713}714 715define <vscale x 4 x i64> @vmerge_xv_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %cond) {716; RV32-LABEL: vmerge_xv_nxv4i64:717; RV32: # %bb.0:718; RV32-NEXT: addi sp, sp, -16719; RV32-NEXT: .cfi_def_cfa_offset 16720; RV32-NEXT: sw a0, 8(sp)721; RV32-NEXT: sw a1, 12(sp)722; RV32-NEXT: addi a0, sp, 8723; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, mu724; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t725; RV32-NEXT: addi sp, sp, 16726; RV32-NEXT: .cfi_def_cfa_offset 0727; RV32-NEXT: ret728;729; RV64-LABEL: vmerge_xv_nxv4i64:730; RV64: # %bb.0:731; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma732; RV64-NEXT: vmerge.vxm v8, v8, a0, v0733; RV64-NEXT: ret734 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0735 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer736 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> %splat, <vscale x 4 x i64> %va737 ret <vscale x 4 x i64> %vc738}739 740define <vscale x 4 x i64> @vmerge_iv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %cond) {741; CHECK-LABEL: vmerge_iv_nxv4i64:742; CHECK: # %bb.0:743; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma744; CHECK-NEXT: vmerge.vim v8, v8, 3, v0745; CHECK-NEXT: ret746 %vc = select <vscale x 4 x i1> %cond, <vscale x 4 x i64> splat (i64 3), <vscale x 4 x i64> %va747 ret <vscale x 4 x i64> %vc748}749 750define <vscale x 8 x i64> @vmerge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %cond) {751; CHECK-LABEL: vmerge_vv_nxv8i64:752; CHECK: # %bb.0:753; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma754; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0755; CHECK-NEXT: ret756 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb757 ret <vscale x 8 x i64> %vc758}759 760define <vscale x 8 x i64> @vmerge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %cond) {761; RV32-LABEL: vmerge_xv_nxv8i64:762; RV32: # %bb.0:763; RV32-NEXT: addi sp, sp, -16764; RV32-NEXT: .cfi_def_cfa_offset 16765; RV32-NEXT: sw a0, 8(sp)766; RV32-NEXT: sw a1, 12(sp)767; RV32-NEXT: addi a0, sp, 8768; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, mu769; RV32-NEXT: vlse64.v v8, (a0), zero, v0.t770; RV32-NEXT: addi sp, sp, 16771; RV32-NEXT: .cfi_def_cfa_offset 0772; RV32-NEXT: ret773;774; RV64-LABEL: vmerge_xv_nxv8i64:775; RV64: # %bb.0:776; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma777; RV64-NEXT: vmerge.vxm v8, v8, a0, v0778; RV64-NEXT: ret779 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0780 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer781 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> %splat, <vscale x 8 x i64> %va782 ret <vscale x 8 x i64> %vc783}784 785define <vscale x 8 x i64> @vmerge_iv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %cond) {786; CHECK-LABEL: vmerge_iv_nxv8i64:787; CHECK: # %bb.0:788; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma789; CHECK-NEXT: vmerge.vim v8, v8, 3, v0790; CHECK-NEXT: ret791 %vc = select <vscale x 8 x i1> %cond, <vscale x 8 x i64> splat (i64 3), <vscale x 8 x i64> %va792 ret <vscale x 8 x i64> %vc793}794 795define <vscale x 8 x i64> @vmerge_truelhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {796; CHECK-LABEL: vmerge_truelhs_nxv8i64_0:797; CHECK: # %bb.0:798; CHECK-NEXT: ret799 %vc = select <vscale x 8 x i1> splat (i1 1), <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb800 ret <vscale x 8 x i64> %vc801}802 803define <vscale x 8 x i64> @vmerge_falselhs_nxv8i64_0(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {804; CHECK-LABEL: vmerge_falselhs_nxv8i64_0:805; CHECK: # %bb.0:806; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma807; CHECK-NEXT: vmv8r.v v8, v16808; CHECK-NEXT: ret809 %vc = select <vscale x 8 x i1> zeroinitializer, <vscale x 8 x i64> %va, <vscale x 8 x i64> %vb810 ret <vscale x 8 x i64> %vc811}812