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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i1> @vselect_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %cc) {6; CHECK-LABEL: vselect_nxv1i1:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vmandn.mm v8, v8, v910; CHECK-NEXT: vmand.mm v9, v0, v911; CHECK-NEXT: vmor.mm v0, v9, v812; CHECK-NEXT: ret13 %v = select <vscale x 1 x i1> %cc, <vscale x 1 x i1> %a, <vscale x 1 x i1> %b14 ret <vscale x 1 x i1> %v15}16 17define <vscale x 2 x i1> @vselect_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %cc) {18; CHECK-LABEL: vselect_nxv2i1:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma21; CHECK-NEXT: vmandn.mm v8, v8, v922; CHECK-NEXT: vmand.mm v9, v0, v923; CHECK-NEXT: vmor.mm v0, v9, v824; CHECK-NEXT: ret25 %v = select <vscale x 2 x i1> %cc, <vscale x 2 x i1> %a, <vscale x 2 x i1> %b26 ret <vscale x 2 x i1> %v27}28 29define <vscale x 4 x i1> @vselect_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %cc) {30; CHECK-LABEL: vselect_nxv4i1:31; CHECK: # %bb.0:32; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma33; CHECK-NEXT: vmandn.mm v8, v8, v934; CHECK-NEXT: vmand.mm v9, v0, v935; CHECK-NEXT: vmor.mm v0, v9, v836; CHECK-NEXT: ret37 %v = select <vscale x 4 x i1> %cc, <vscale x 4 x i1> %a, <vscale x 4 x i1> %b38 ret <vscale x 4 x i1> %v39}40 41define <vscale x 8 x i1> @vselect_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %cc) {42; CHECK-LABEL: vselect_nxv8i1:43; CHECK: # %bb.0:44; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma45; CHECK-NEXT: vmandn.mm v8, v8, v946; CHECK-NEXT: vmand.mm v9, v0, v947; CHECK-NEXT: vmor.mm v0, v9, v848; CHECK-NEXT: ret49 %v = select <vscale x 8 x i1> %cc, <vscale x 8 x i1> %a, <vscale x 8 x i1> %b50 ret <vscale x 8 x i1> %v51}52 53define <vscale x 16 x i1> @vselect_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %cc) {54; CHECK-LABEL: vselect_nxv16i1:55; CHECK: # %bb.0:56; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma57; CHECK-NEXT: vmandn.mm v8, v8, v958; CHECK-NEXT: vmand.mm v9, v0, v959; CHECK-NEXT: vmor.mm v0, v9, v860; CHECK-NEXT: ret61 %v = select <vscale x 16 x i1> %cc, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b62 ret <vscale x 16 x i1> %v63}64 65define <vscale x 32 x i1> @vselect_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %cc) {66; CHECK-LABEL: vselect_nxv32i1:67; CHECK: # %bb.0:68; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma69; CHECK-NEXT: vmandn.mm v8, v8, v970; CHECK-NEXT: vmand.mm v9, v0, v971; CHECK-NEXT: vmor.mm v0, v9, v872; CHECK-NEXT: ret73 %v = select <vscale x 32 x i1> %cc, <vscale x 32 x i1> %a, <vscale x 32 x i1> %b74 ret <vscale x 32 x i1> %v75}76 77define <vscale x 64 x i1> @vselect_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %cc) {78; CHECK-LABEL: vselect_nxv64i1:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma81; CHECK-NEXT: vmandn.mm v8, v8, v982; CHECK-NEXT: vmand.mm v9, v0, v983; CHECK-NEXT: vmor.mm v0, v9, v884; CHECK-NEXT: ret85 %v = select <vscale x 64 x i1> %cc, <vscale x 64 x i1> %a, <vscale x 64 x i1> %b86 ret <vscale x 64 x i1> %v87}88