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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+v,+zvfbfmin -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s4; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+v,+zvfbfmin -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s6 7define <vscale x 1 x bfloat> @select_nxv1bf16(<vscale x 1 x i1> %a, <vscale x 1 x bfloat> %b, <vscale x 1 x bfloat> %c, i32 zeroext %evl) {8; CHECK-LABEL: select_nxv1bf16:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma11; CHECK-NEXT: vmerge.vvm v8, v9, v8, v012; CHECK-NEXT: ret13 %v = call <vscale x 1 x bfloat> @llvm.vp.select.nxv1bf16(<vscale x 1 x i1> %a, <vscale x 1 x bfloat> %b, <vscale x 1 x bfloat> %c, i32 %evl)14 ret <vscale x 1 x bfloat> %v15}16 17define <vscale x 2 x bfloat> @select_nxv2bf16(<vscale x 2 x i1> %a, <vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %c, i32 zeroext %evl) {18; CHECK-LABEL: select_nxv2bf16:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma21; CHECK-NEXT: vmerge.vvm v8, v9, v8, v022; CHECK-NEXT: ret23 %v = call <vscale x 2 x bfloat> @llvm.vp.select.nxv2bf16(<vscale x 2 x i1> %a, <vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %c, i32 %evl)24 ret <vscale x 2 x bfloat> %v25}26 27define <vscale x 4 x bfloat> @select_nxv4bf16(<vscale x 4 x i1> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, i32 zeroext %evl) {28; CHECK-LABEL: select_nxv4bf16:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma31; CHECK-NEXT: vmerge.vvm v8, v9, v8, v032; CHECK-NEXT: ret33 %v = call <vscale x 4 x bfloat> @llvm.vp.select.nxv4bf16(<vscale x 4 x i1> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, i32 %evl)34 ret <vscale x 4 x bfloat> %v35}36 37define <vscale x 8 x bfloat> @select_nxv8bf16(<vscale x 8 x i1> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 zeroext %evl) {38; CHECK-LABEL: select_nxv8bf16:39; CHECK: # %bb.0:40; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma41; CHECK-NEXT: vmerge.vvm v8, v10, v8, v042; CHECK-NEXT: ret43 %v = call <vscale x 8 x bfloat> @llvm.vp.select.nxv8bf16(<vscale x 8 x i1> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 %evl)44 ret <vscale x 8 x bfloat> %v45}46 47define <vscale x 16 x bfloat> @select_nxv16bf16(<vscale x 16 x i1> %a, <vscale x 16 x bfloat> %b, <vscale x 16 x bfloat> %c, i32 zeroext %evl) {48; CHECK-LABEL: select_nxv16bf16:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma51; CHECK-NEXT: vmerge.vvm v8, v12, v8, v052; CHECK-NEXT: ret53 %v = call <vscale x 16 x bfloat> @llvm.vp.select.nxv16bf16(<vscale x 16 x i1> %a, <vscale x 16 x bfloat> %b, <vscale x 16 x bfloat> %c, i32 %evl)54 ret <vscale x 16 x bfloat> %v55}56 57define <vscale x 32 x bfloat> @select_nxv32bf16(<vscale x 32 x i1> %a, <vscale x 32 x bfloat> %b, <vscale x 32 x bfloat> %c, i32 zeroext %evl) {58; CHECK-LABEL: select_nxv32bf16:59; CHECK: # %bb.0:60; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma61; CHECK-NEXT: vmerge.vvm v8, v16, v8, v062; CHECK-NEXT: ret63 %v = call <vscale x 32 x bfloat> @llvm.vp.select.nxv32bf16(<vscale x 32 x i1> %a, <vscale x 32 x bfloat> %b, <vscale x 32 x bfloat> %c, i32 %evl)64 ret <vscale x 32 x bfloat> %v65}66