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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfh,+v -target-abi=ilp32d \3; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfh,+v -target-abi=lp64d \5; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV646; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+zvfhmin,+v -target-abi=ilp32d \7; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV328; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+zvfhmin,+v -target-abi=lp64d \9; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV6410 11define <vscale x 1 x i1> @select_nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 zeroext %evl) {12; CHECK-LABEL: select_nxv1i1:13; CHECK: # %bb.0:14; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma15; CHECK-NEXT: vmandn.mm v9, v9, v016; CHECK-NEXT: vmand.mm v8, v8, v017; CHECK-NEXT: vmor.mm v0, v8, v918; CHECK-NEXT: ret19 %v = call <vscale x 1 x i1> @llvm.vp.select.nxv1i1(<vscale x 1 x i1> %a, <vscale x 1 x i1> %b, <vscale x 1 x i1> %c, i32 %evl)20 ret <vscale x 1 x i1> %v21}22 23define <vscale x 2 x i1> @select_nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 zeroext %evl) {24; CHECK-LABEL: select_nxv2i1:25; CHECK: # %bb.0:26; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma27; CHECK-NEXT: vmandn.mm v9, v9, v028; CHECK-NEXT: vmand.mm v8, v8, v029; CHECK-NEXT: vmor.mm v0, v8, v930; CHECK-NEXT: ret31 %v = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %a, <vscale x 2 x i1> %b, <vscale x 2 x i1> %c, i32 %evl)32 ret <vscale x 2 x i1> %v33}34 35define <vscale x 4 x i1> @select_nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 zeroext %evl) {36; CHECK-LABEL: select_nxv4i1:37; CHECK: # %bb.0:38; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma39; CHECK-NEXT: vmandn.mm v9, v9, v040; CHECK-NEXT: vmand.mm v8, v8, v041; CHECK-NEXT: vmor.mm v0, v8, v942; CHECK-NEXT: ret43 %v = call <vscale x 4 x i1> @llvm.vp.select.nxv4i1(<vscale x 4 x i1> %a, <vscale x 4 x i1> %b, <vscale x 4 x i1> %c, i32 %evl)44 ret <vscale x 4 x i1> %v45}46 47define <vscale x 8 x i1> @select_nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 zeroext %evl) {48; CHECK-LABEL: select_nxv8i1:49; CHECK: # %bb.0:50; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma51; CHECK-NEXT: vmandn.mm v9, v9, v052; CHECK-NEXT: vmand.mm v8, v8, v053; CHECK-NEXT: vmor.mm v0, v8, v954; CHECK-NEXT: ret55 %v = call <vscale x 8 x i1> @llvm.vp.select.nxv8i1(<vscale x 8 x i1> %a, <vscale x 8 x i1> %b, <vscale x 8 x i1> %c, i32 %evl)56 ret <vscale x 8 x i1> %v57}58 59define <vscale x 16 x i1> @select_nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 zeroext %evl) {60; CHECK-LABEL: select_nxv16i1:61; CHECK: # %bb.0:62; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma63; CHECK-NEXT: vmandn.mm v9, v9, v064; CHECK-NEXT: vmand.mm v8, v8, v065; CHECK-NEXT: vmor.mm v0, v8, v966; CHECK-NEXT: ret67 %v = call <vscale x 16 x i1> @llvm.vp.select.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b, <vscale x 16 x i1> %c, i32 %evl)68 ret <vscale x 16 x i1> %v69}70 71define <vscale x 32 x i1> @select_nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 zeroext %evl) {72; CHECK-LABEL: select_nxv32i1:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma75; CHECK-NEXT: vmandn.mm v9, v9, v076; CHECK-NEXT: vmand.mm v8, v8, v077; CHECK-NEXT: vmor.mm v0, v8, v978; CHECK-NEXT: ret79 %v = call <vscale x 32 x i1> @llvm.vp.select.nxv32i1(<vscale x 32 x i1> %a, <vscale x 32 x i1> %b, <vscale x 32 x i1> %c, i32 %evl)80 ret <vscale x 32 x i1> %v81}82 83define <vscale x 64 x i1> @select_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 zeroext %evl) {84; CHECK-LABEL: select_nxv64i1:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma87; CHECK-NEXT: vmandn.mm v9, v9, v088; CHECK-NEXT: vmand.mm v8, v8, v089; CHECK-NEXT: vmor.mm v0, v8, v990; CHECK-NEXT: ret91 %v = call <vscale x 64 x i1> @llvm.vp.select.nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b, <vscale x 64 x i1> %c, i32 %evl)92 ret <vscale x 64 x i1> %v93}94 95define <vscale x 8 x i7> @select_nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 zeroext %evl) {96; CHECK-LABEL: select_nxv8i7:97; CHECK: # %bb.0:98; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma99; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0100; CHECK-NEXT: ret101 %v = call <vscale x 8 x i7> @llvm.vp.select.nxv8i7(<vscale x 8 x i1> %a, <vscale x 8 x i7> %b, <vscale x 8 x i7> %c, i32 %evl)102 ret <vscale x 8 x i7> %v103}104 105define <vscale x 1 x i8> @select_nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 zeroext %evl) {106; CHECK-LABEL: select_nxv1i8:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma109; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0110; CHECK-NEXT: ret111 %v = call <vscale x 1 x i8> @llvm.vp.select.nxv1i8(<vscale x 1 x i1> %a, <vscale x 1 x i8> %b, <vscale x 1 x i8> %c, i32 %evl)112 ret <vscale x 1 x i8> %v113}114 115define <vscale x 2 x i8> @select_nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 zeroext %evl) {116; CHECK-LABEL: select_nxv2i8:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma119; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0120; CHECK-NEXT: ret121 %v = call <vscale x 2 x i8> @llvm.vp.select.nxv2i8(<vscale x 2 x i1> %a, <vscale x 2 x i8> %b, <vscale x 2 x i8> %c, i32 %evl)122 ret <vscale x 2 x i8> %v123}124 125define <vscale x 4 x i8> @select_nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 zeroext %evl) {126; CHECK-LABEL: select_nxv4i8:127; CHECK: # %bb.0:128; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma129; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0130; CHECK-NEXT: ret131 %v = call <vscale x 4 x i8> @llvm.vp.select.nxv4i8(<vscale x 4 x i1> %a, <vscale x 4 x i8> %b, <vscale x 4 x i8> %c, i32 %evl)132 ret <vscale x 4 x i8> %v133}134 135define <vscale x 8 x i8> @select_nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 zeroext %evl) {136; CHECK-LABEL: select_nxv8i8:137; CHECK: # %bb.0:138; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma139; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0140; CHECK-NEXT: ret141 %v = call <vscale x 8 x i8> @llvm.vp.select.nxv8i8(<vscale x 8 x i1> %a, <vscale x 8 x i8> %b, <vscale x 8 x i8> %c, i32 %evl)142 ret <vscale x 8 x i8> %v143}144 145define <vscale x 14 x i8> @select_nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 zeroext %evl) {146; CHECK-LABEL: select_nxv14i8:147; CHECK: # %bb.0:148; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma149; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0150; CHECK-NEXT: ret151 %v = call <vscale x 14 x i8> @llvm.vp.select.nxv14i8(<vscale x 14 x i1> %a, <vscale x 14 x i8> %b, <vscale x 14 x i8> %c, i32 %evl)152 ret <vscale x 14 x i8> %v153}154 155define <vscale x 16 x i8> @select_nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 zeroext %evl) {156; CHECK-LABEL: select_nxv16i8:157; CHECK: # %bb.0:158; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma159; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0160; CHECK-NEXT: ret161 %v = call <vscale x 16 x i8> @llvm.vp.select.nxv16i8(<vscale x 16 x i1> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, i32 %evl)162 ret <vscale x 16 x i8> %v163}164 165define <vscale x 32 x i8> @select_nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 zeroext %evl) {166; CHECK-LABEL: select_nxv32i8:167; CHECK: # %bb.0:168; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma169; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0170; CHECK-NEXT: ret171 %v = call <vscale x 32 x i8> @llvm.vp.select.nxv32i8(<vscale x 32 x i1> %a, <vscale x 32 x i8> %b, <vscale x 32 x i8> %c, i32 %evl)172 ret <vscale x 32 x i8> %v173}174 175define <vscale x 64 x i8> @select_nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 zeroext %evl) {176; CHECK-LABEL: select_nxv64i8:177; CHECK: # %bb.0:178; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma179; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0180; CHECK-NEXT: ret181 %v = call <vscale x 64 x i8> @llvm.vp.select.nxv64i8(<vscale x 64 x i1> %a, <vscale x 64 x i8> %b, <vscale x 64 x i8> %c, i32 %evl)182 ret <vscale x 64 x i8> %v183}184 185define <vscale x 1 x i16> @select_nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 zeroext %evl) {186; CHECK-LABEL: select_nxv1i16:187; CHECK: # %bb.0:188; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma189; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0190; CHECK-NEXT: ret191 %v = call <vscale x 1 x i16> @llvm.vp.select.nxv1i16(<vscale x 1 x i1> %a, <vscale x 1 x i16> %b, <vscale x 1 x i16> %c, i32 %evl)192 ret <vscale x 1 x i16> %v193}194 195define <vscale x 2 x i16> @select_nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 zeroext %evl) {196; CHECK-LABEL: select_nxv2i16:197; CHECK: # %bb.0:198; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma199; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0200; CHECK-NEXT: ret201 %v = call <vscale x 2 x i16> @llvm.vp.select.nxv2i16(<vscale x 2 x i1> %a, <vscale x 2 x i16> %b, <vscale x 2 x i16> %c, i32 %evl)202 ret <vscale x 2 x i16> %v203}204 205define <vscale x 4 x i16> @select_nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 zeroext %evl) {206; CHECK-LABEL: select_nxv4i16:207; CHECK: # %bb.0:208; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma209; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0210; CHECK-NEXT: ret211 %v = call <vscale x 4 x i16> @llvm.vp.select.nxv4i16(<vscale x 4 x i1> %a, <vscale x 4 x i16> %b, <vscale x 4 x i16> %c, i32 %evl)212 ret <vscale x 4 x i16> %v213}214 215define <vscale x 8 x i16> @select_nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 zeroext %evl) {216; CHECK-LABEL: select_nxv8i16:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma219; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0220; CHECK-NEXT: ret221 %v = call <vscale x 8 x i16> @llvm.vp.select.nxv8i16(<vscale x 8 x i1> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, i32 %evl)222 ret <vscale x 8 x i16> %v223}224 225define <vscale x 16 x i16> @select_nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 zeroext %evl) {226; CHECK-LABEL: select_nxv16i16:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma229; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0230; CHECK-NEXT: ret231 %v = call <vscale x 16 x i16> @llvm.vp.select.nxv16i16(<vscale x 16 x i1> %a, <vscale x 16 x i16> %b, <vscale x 16 x i16> %c, i32 %evl)232 ret <vscale x 16 x i16> %v233}234 235define <vscale x 32 x i16> @select_nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 zeroext %evl) {236; CHECK-LABEL: select_nxv32i16:237; CHECK: # %bb.0:238; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma239; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0240; CHECK-NEXT: ret241 %v = call <vscale x 32 x i16> @llvm.vp.select.nxv32i16(<vscale x 32 x i1> %a, <vscale x 32 x i16> %b, <vscale x 32 x i16> %c, i32 %evl)242 ret <vscale x 32 x i16> %v243}244 245define <vscale x 1 x i32> @select_nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 zeroext %evl) {246; CHECK-LABEL: select_nxv1i32:247; CHECK: # %bb.0:248; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma249; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0250; CHECK-NEXT: ret251 %v = call <vscale x 1 x i32> @llvm.vp.select.nxv1i32(<vscale x 1 x i1> %a, <vscale x 1 x i32> %b, <vscale x 1 x i32> %c, i32 %evl)252 ret <vscale x 1 x i32> %v253}254 255define <vscale x 2 x i32> @select_nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 zeroext %evl) {256; CHECK-LABEL: select_nxv2i32:257; CHECK: # %bb.0:258; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma259; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0260; CHECK-NEXT: ret261 %v = call <vscale x 2 x i32> @llvm.vp.select.nxv2i32(<vscale x 2 x i1> %a, <vscale x 2 x i32> %b, <vscale x 2 x i32> %c, i32 %evl)262 ret <vscale x 2 x i32> %v263}264 265define <vscale x 4 x i32> @select_nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 zeroext %evl) {266; CHECK-LABEL: select_nxv4i32:267; CHECK: # %bb.0:268; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma269; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0270; CHECK-NEXT: ret271 %v = call <vscale x 4 x i32> @llvm.vp.select.nxv4i32(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, i32 %evl)272 ret <vscale x 4 x i32> %v273}274 275define <vscale x 8 x i32> @select_nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 zeroext %evl) {276; CHECK-LABEL: select_nxv8i32:277; CHECK: # %bb.0:278; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma279; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0280; CHECK-NEXT: ret281 %v = call <vscale x 8 x i32> @llvm.vp.select.nxv8i32(<vscale x 8 x i1> %a, <vscale x 8 x i32> %b, <vscale x 8 x i32> %c, i32 %evl)282 ret <vscale x 8 x i32> %v283}284 285define <vscale x 16 x i32> @select_nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 zeroext %evl) {286; CHECK-LABEL: select_nxv16i32:287; CHECK: # %bb.0:288; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma289; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0290; CHECK-NEXT: ret291 %v = call <vscale x 16 x i32> @llvm.vp.select.nxv16i32(<vscale x 16 x i1> %a, <vscale x 16 x i32> %b, <vscale x 16 x i32> %c, i32 %evl)292 ret <vscale x 16 x i32> %v293}294 295define <vscale x 32 x i32> @select_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 zeroext %evl) {296; CHECK-LABEL: select_nxv32i32:297; CHECK: # %bb.0:298; CHECK-NEXT: addi sp, sp, -16299; CHECK-NEXT: .cfi_def_cfa_offset 16300; CHECK-NEXT: csrr a1, vlenb301; CHECK-NEXT: slli a1, a1, 3302; CHECK-NEXT: sub sp, sp, a1303; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb304; CHECK-NEXT: addi a1, sp, 16305; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill306; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma307; CHECK-NEXT: vmv1r.v v7, v0308; CHECK-NEXT: csrr a3, vlenb309; CHECK-NEXT: slli a4, a3, 3310; CHECK-NEXT: slli a1, a3, 1311; CHECK-NEXT: srli a3, a3, 2312; CHECK-NEXT: add a4, a0, a4313; CHECK-NEXT: sub a5, a2, a1314; CHECK-NEXT: vl8re32.v v24, (a4)315; CHECK-NEXT: sltu a4, a2, a5316; CHECK-NEXT: addi a4, a4, -1317; CHECK-NEXT: vl8re32.v v8, (a0)318; CHECK-NEXT: vslidedown.vx v0, v0, a3319; CHECK-NEXT: and a4, a4, a5320; CHECK-NEXT: vsetvli zero, a4, e32, m8, ta, ma321; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0322; CHECK-NEXT: bltu a2, a1, .LBB27_2323; CHECK-NEXT: # %bb.1:324; CHECK-NEXT: mv a2, a1325; CHECK-NEXT: .LBB27_2:326; CHECK-NEXT: vmv1r.v v0, v7327; CHECK-NEXT: addi a0, sp, 16328; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload329; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma330; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0331; CHECK-NEXT: csrr a0, vlenb332; CHECK-NEXT: slli a0, a0, 3333; CHECK-NEXT: add sp, sp, a0334; CHECK-NEXT: .cfi_def_cfa sp, 16335; CHECK-NEXT: addi sp, sp, 16336; CHECK-NEXT: .cfi_def_cfa_offset 0337; CHECK-NEXT: ret338 %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl)339 ret <vscale x 32 x i32> %v340}341 342define <vscale x 32 x i32> @select_evl_nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c) {343; RV32-LABEL: select_evl_nxv32i32:344; RV32: # %bb.0:345; RV32-NEXT: vl8re32.v v24, (a0)346; RV32-NEXT: csrr a1, vlenb347; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma348; RV32-NEXT: vmerge.vvm v8, v24, v8, v0349; RV32-NEXT: slli a2, a1, 3350; RV32-NEXT: add a0, a0, a2351; RV32-NEXT: slli a2, a1, 1352; RV32-NEXT: sub a2, a1, a2353; RV32-NEXT: vl8re32.v v24, (a0)354; RV32-NEXT: sltu a0, a1, a2355; RV32-NEXT: addi a0, a0, -1356; RV32-NEXT: srli a1, a1, 2357; RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma358; RV32-NEXT: vslidedown.vx v0, v0, a1359; RV32-NEXT: and a0, a0, a2360; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma361; RV32-NEXT: vmerge.vvm v16, v24, v16, v0362; RV32-NEXT: ret363;364; RV64-LABEL: select_evl_nxv32i32:365; RV64: # %bb.0:366; RV64-NEXT: addi sp, sp, -16367; RV64-NEXT: .cfi_def_cfa_offset 16368; RV64-NEXT: csrr a1, vlenb369; RV64-NEXT: slli a1, a1, 3370; RV64-NEXT: sub sp, sp, a1371; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb372; RV64-NEXT: addi a1, sp, 16373; RV64-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill374; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma375; RV64-NEXT: vmv1r.v v7, v0376; RV64-NEXT: csrr a1, vlenb377; RV64-NEXT: slli a3, a1, 3378; RV64-NEXT: slli a2, a1, 1379; RV64-NEXT: srli a4, a1, 2380; RV64-NEXT: add a3, a0, a3381; RV64-NEXT: sub a5, a1, a2382; RV64-NEXT: vl8re32.v v24, (a3)383; RV64-NEXT: sltu a3, a1, a5384; RV64-NEXT: addi a3, a3, -1385; RV64-NEXT: vl8re32.v v8, (a0)386; RV64-NEXT: vslidedown.vx v0, v0, a4387; RV64-NEXT: and a3, a3, a5388; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma389; RV64-NEXT: vmerge.vvm v16, v24, v16, v0390; RV64-NEXT: bltu a1, a2, .LBB28_2391; RV64-NEXT: # %bb.1:392; RV64-NEXT: mv a1, a2393; RV64-NEXT: .LBB28_2:394; RV64-NEXT: vmv1r.v v0, v7395; RV64-NEXT: addi a0, sp, 16396; RV64-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload397; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma398; RV64-NEXT: vmerge.vvm v8, v8, v24, v0399; RV64-NEXT: csrr a0, vlenb400; RV64-NEXT: slli a0, a0, 3401; RV64-NEXT: add sp, sp, a0402; RV64-NEXT: .cfi_def_cfa sp, 16403; RV64-NEXT: addi sp, sp, 16404; RV64-NEXT: .cfi_def_cfa_offset 0405; RV64-NEXT: ret406 %evl = call i32 @llvm.vscale.i32()407 %evl0 = mul i32 %evl, 8408 %v = call <vscale x 32 x i32> @llvm.vp.select.nxv32i32(<vscale x 32 x i1> %a, <vscale x 32 x i32> %b, <vscale x 32 x i32> %c, i32 %evl0)409 ret <vscale x 32 x i32> %v410}411 412define <vscale x 1 x i64> @select_nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 zeroext %evl) {413; CHECK-LABEL: select_nxv1i64:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma416; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0417; CHECK-NEXT: ret418 %v = call <vscale x 1 x i64> @llvm.vp.select.nxv1i64(<vscale x 1 x i1> %a, <vscale x 1 x i64> %b, <vscale x 1 x i64> %c, i32 %evl)419 ret <vscale x 1 x i64> %v420}421 422define <vscale x 2 x i64> @select_nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 zeroext %evl) {423; CHECK-LABEL: select_nxv2i64:424; CHECK: # %bb.0:425; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma426; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0427; CHECK-NEXT: ret428 %v = call <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, i32 %evl)429 ret <vscale x 2 x i64> %v430}431 432define <vscale x 2 x i64> @select_nxv2i64_constant_true(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, i32 zeroext %evl) {433; CHECK-LABEL: select_nxv2i64_constant_true:434; CHECK: # %bb.0:435; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma436; CHECK-NEXT: vmerge.vim v8, v8, -1, v0437; CHECK-NEXT: ret438 %v = call <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i64> %b, i32 %evl)439 ret <vscale x 2 x i64> %v440}441 442define <vscale x 2 x i64> @select_nxv2i64_constant_false(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, i32 zeroext %evl) {443; CHECK-LABEL: select_nxv2i64_constant_false:444; CHECK: # %bb.0:445; CHECK-NEXT: li a1, 100446; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma447; CHECK-NEXT: vmv.v.x v10, a1448; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0449; CHECK-NEXT: ret450 %v = call <vscale x 2 x i64> @llvm.vp.select.nxv2i64(<vscale x 2 x i1> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> splat (i64 100), i32 %evl)451 ret <vscale x 2 x i64> %v452}453 454define <vscale x 4 x i64> @select_nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 zeroext %evl) {455; CHECK-LABEL: select_nxv4i64:456; CHECK: # %bb.0:457; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma458; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0459; CHECK-NEXT: ret460 %v = call <vscale x 4 x i64> @llvm.vp.select.nxv4i64(<vscale x 4 x i1> %a, <vscale x 4 x i64> %b, <vscale x 4 x i64> %c, i32 %evl)461 ret <vscale x 4 x i64> %v462}463 464define <vscale x 8 x i64> @select_nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 zeroext %evl) {465; CHECK-LABEL: select_nxv8i64:466; CHECK: # %bb.0:467; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma468; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0469; CHECK-NEXT: ret470 %v = call <vscale x 8 x i64> @llvm.vp.select.nxv8i64(<vscale x 8 x i1> %a, <vscale x 8 x i64> %b, <vscale x 8 x i64> %c, i32 %evl)471 ret <vscale x 8 x i64> %v472}473 474define <vscale x 1 x half> @select_nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 zeroext %evl) {475; CHECK-LABEL: select_nxv1f16:476; CHECK: # %bb.0:477; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma478; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0479; CHECK-NEXT: ret480 %v = call <vscale x 1 x half> @llvm.vp.select.nxv1f16(<vscale x 1 x i1> %a, <vscale x 1 x half> %b, <vscale x 1 x half> %c, i32 %evl)481 ret <vscale x 1 x half> %v482}483 484define <vscale x 2 x half> @select_nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 zeroext %evl) {485; CHECK-LABEL: select_nxv2f16:486; CHECK: # %bb.0:487; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma488; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0489; CHECK-NEXT: ret490 %v = call <vscale x 2 x half> @llvm.vp.select.nxv2f16(<vscale x 2 x i1> %a, <vscale x 2 x half> %b, <vscale x 2 x half> %c, i32 %evl)491 ret <vscale x 2 x half> %v492}493 494define <vscale x 4 x half> @select_nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 zeroext %evl) {495; CHECK-LABEL: select_nxv4f16:496; CHECK: # %bb.0:497; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma498; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0499; CHECK-NEXT: ret500 %v = call <vscale x 4 x half> @llvm.vp.select.nxv4f16(<vscale x 4 x i1> %a, <vscale x 4 x half> %b, <vscale x 4 x half> %c, i32 %evl)501 ret <vscale x 4 x half> %v502}503 504define <vscale x 8 x half> @select_nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 zeroext %evl) {505; CHECK-LABEL: select_nxv8f16:506; CHECK: # %bb.0:507; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma508; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0509; CHECK-NEXT: ret510 %v = call <vscale x 8 x half> @llvm.vp.select.nxv8f16(<vscale x 8 x i1> %a, <vscale x 8 x half> %b, <vscale x 8 x half> %c, i32 %evl)511 ret <vscale x 8 x half> %v512}513 514define <vscale x 16 x half> @select_nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 zeroext %evl) {515; CHECK-LABEL: select_nxv16f16:516; CHECK: # %bb.0:517; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma518; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0519; CHECK-NEXT: ret520 %v = call <vscale x 16 x half> @llvm.vp.select.nxv16f16(<vscale x 16 x i1> %a, <vscale x 16 x half> %b, <vscale x 16 x half> %c, i32 %evl)521 ret <vscale x 16 x half> %v522}523 524define <vscale x 32 x half> @select_nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 zeroext %evl) {525; CHECK-LABEL: select_nxv32f16:526; CHECK: # %bb.0:527; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma528; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0529; CHECK-NEXT: ret530 %v = call <vscale x 32 x half> @llvm.vp.select.nxv32f16(<vscale x 32 x i1> %a, <vscale x 32 x half> %b, <vscale x 32 x half> %c, i32 %evl)531 ret <vscale x 32 x half> %v532}533 534define <vscale x 1 x float> @select_nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 zeroext %evl) {535; CHECK-LABEL: select_nxv1f32:536; CHECK: # %bb.0:537; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma538; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0539; CHECK-NEXT: ret540 %v = call <vscale x 1 x float> @llvm.vp.select.nxv1f32(<vscale x 1 x i1> %a, <vscale x 1 x float> %b, <vscale x 1 x float> %c, i32 %evl)541 ret <vscale x 1 x float> %v542}543 544define <vscale x 2 x float> @select_nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 zeroext %evl) {545; CHECK-LABEL: select_nxv2f32:546; CHECK: # %bb.0:547; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma548; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0549; CHECK-NEXT: ret550 %v = call <vscale x 2 x float> @llvm.vp.select.nxv2f32(<vscale x 2 x i1> %a, <vscale x 2 x float> %b, <vscale x 2 x float> %c, i32 %evl)551 ret <vscale x 2 x float> %v552}553 554define <vscale x 4 x float> @select_nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 zeroext %evl) {555; CHECK-LABEL: select_nxv4f32:556; CHECK: # %bb.0:557; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma558; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0559; CHECK-NEXT: ret560 %v = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> %a, <vscale x 4 x float> %b, <vscale x 4 x float> %c, i32 %evl)561 ret <vscale x 4 x float> %v562}563 564define <vscale x 8 x float> @select_nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 zeroext %evl) {565; CHECK-LABEL: select_nxv8f32:566; CHECK: # %bb.0:567; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma568; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0569; CHECK-NEXT: ret570 %v = call <vscale x 8 x float> @llvm.vp.select.nxv8f32(<vscale x 8 x i1> %a, <vscale x 8 x float> %b, <vscale x 8 x float> %c, i32 %evl)571 ret <vscale x 8 x float> %v572}573 574define <vscale x 16 x float> @select_nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 zeroext %evl) {575; CHECK-LABEL: select_nxv16f32:576; CHECK: # %bb.0:577; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma578; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0579; CHECK-NEXT: ret580 %v = call <vscale x 16 x float> @llvm.vp.select.nxv16f32(<vscale x 16 x i1> %a, <vscale x 16 x float> %b, <vscale x 16 x float> %c, i32 %evl)581 ret <vscale x 16 x float> %v582}583 584define <vscale x 1 x double> @select_nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 zeroext %evl) {585; CHECK-LABEL: select_nxv1f64:586; CHECK: # %bb.0:587; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma588; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0589; CHECK-NEXT: ret590 %v = call <vscale x 1 x double> @llvm.vp.select.nxv1f64(<vscale x 1 x i1> %a, <vscale x 1 x double> %b, <vscale x 1 x double> %c, i32 %evl)591 ret <vscale x 1 x double> %v592}593 594define <vscale x 2 x double> @select_nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 zeroext %evl) {595; CHECK-LABEL: select_nxv2f64:596; CHECK: # %bb.0:597; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma598; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0599; CHECK-NEXT: ret600 %v = call <vscale x 2 x double> @llvm.vp.select.nxv2f64(<vscale x 2 x i1> %a, <vscale x 2 x double> %b, <vscale x 2 x double> %c, i32 %evl)601 ret <vscale x 2 x double> %v602}603 604define <vscale x 4 x double> @select_nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 zeroext %evl) {605; CHECK-LABEL: select_nxv4f64:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma608; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0609; CHECK-NEXT: ret610 %v = call <vscale x 4 x double> @llvm.vp.select.nxv4f64(<vscale x 4 x i1> %a, <vscale x 4 x double> %b, <vscale x 4 x double> %c, i32 %evl)611 ret <vscale x 4 x double> %v612}613 614define <vscale x 8 x double> @select_nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 zeroext %evl) {615; CHECK-LABEL: select_nxv8f64:616; CHECK: # %bb.0:617; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma618; CHECK-NEXT: vmerge.vvm v8, v16, v8, v0619; CHECK-NEXT: ret620 %v = call <vscale x 8 x double> @llvm.vp.select.nxv8f64(<vscale x 8 x i1> %a, <vscale x 8 x double> %b, <vscale x 8 x double> %c, i32 %evl)621 ret <vscale x 8 x double> %v622}623 624define <vscale x 16 x double> @select_nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 zeroext %evl) {625; CHECK-LABEL: select_nxv16f64:626; CHECK: # %bb.0:627; CHECK-NEXT: addi sp, sp, -16628; CHECK-NEXT: .cfi_def_cfa_offset 16629; CHECK-NEXT: csrr a1, vlenb630; CHECK-NEXT: slli a1, a1, 3631; CHECK-NEXT: sub sp, sp, a1632; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb633; CHECK-NEXT: addi a1, sp, 16634; CHECK-NEXT: vs8r.v v8, (a1) # vscale x 64-byte Folded Spill635; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma636; CHECK-NEXT: vmv1r.v v7, v0637; CHECK-NEXT: csrr a1, vlenb638; CHECK-NEXT: slli a3, a1, 3639; CHECK-NEXT: sub a4, a2, a1640; CHECK-NEXT: add a3, a0, a3641; CHECK-NEXT: sltu a5, a2, a4642; CHECK-NEXT: vl8re64.v v24, (a3)643; CHECK-NEXT: addi a5, a5, -1644; CHECK-NEXT: srli a3, a1, 3645; CHECK-NEXT: vl8re64.v v8, (a0)646; CHECK-NEXT: vslidedown.vx v0, v0, a3647; CHECK-NEXT: and a4, a5, a4648; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma649; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0650; CHECK-NEXT: bltu a2, a1, .LBB50_2651; CHECK-NEXT: # %bb.1:652; CHECK-NEXT: mv a2, a1653; CHECK-NEXT: .LBB50_2:654; CHECK-NEXT: vmv1r.v v0, v7655; CHECK-NEXT: addi a0, sp, 16656; CHECK-NEXT: vl8r.v v24, (a0) # vscale x 64-byte Folded Reload657; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma658; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0659; CHECK-NEXT: csrr a0, vlenb660; CHECK-NEXT: slli a0, a0, 3661; CHECK-NEXT: add sp, sp, a0662; CHECK-NEXT: .cfi_def_cfa sp, 16663; CHECK-NEXT: addi sp, sp, 16664; CHECK-NEXT: .cfi_def_cfa_offset 0665; CHECK-NEXT: ret666 %v = call <vscale x 16 x double> @llvm.vp.select.nxv16f64(<vscale x 16 x i1> %a, <vscale x 16 x double> %b, <vscale x 16 x double> %c, i32 %evl)667 ret <vscale x 16 x double> %v668}669 670define <vscale x 2 x i1> @select_zero(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {671; CHECK-LABEL: select_zero:672; CHECK: # %bb.0:673; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma674; CHECK-NEXT: vmand.mm v0, v0, v8675; CHECK-NEXT: ret676 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> zeroinitializer, i32 %evl)677 ret <vscale x 2 x i1> %a678}679 680define <vscale x 2 x i1> @select_one(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {681; CHECK-LABEL: select_one:682; CHECK: # %bb.0:683; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma684; CHECK-NEXT: vmorn.mm v0, v8, v0685; CHECK-NEXT: ret686 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> splat (i1 true), i32 %evl)687 ret <vscale x 2 x i1> %a688}689 690define <vscale x 2 x i1> @select_x_zero(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {691; CHECK-LABEL: select_x_zero:692; CHECK: # %bb.0:693; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma694; CHECK-NEXT: vmand.mm v0, v0, v8695; CHECK-NEXT: ret696 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> zeroinitializer, i32 %evl)697 ret <vscale x 2 x i1> %a698}699 700define <vscale x 2 x i1> @select_x_one(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {701; CHECK-LABEL: select_x_one:702; CHECK: # %bb.0:703; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma704; CHECK-NEXT: vmorn.mm v0, v8, v0705; CHECK-NEXT: ret706 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> splat (i1 true), i32 %evl)707 ret <vscale x 2 x i1> %a708}709 710define <vscale x 2 x i1> @select_zero_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {711; CHECK-LABEL: select_zero_x:712; CHECK: # %bb.0:713; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma714; CHECK-NEXT: vmandn.mm v0, v8, v0715; CHECK-NEXT: ret716 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %y, i32 %evl)717 ret <vscale x 2 x i1> %a718}719 720define <vscale x 2 x i1> @select_one_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {721; CHECK-LABEL: select_one_x:722; CHECK: # %bb.0:723; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma724; CHECK-NEXT: vmor.mm v0, v0, v8725; CHECK-NEXT: ret726 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> splat (i1 true), <vscale x 2 x i1> %y, i32 %evl)727 ret <vscale x 2 x i1> %a728}729 730define <vscale x 2 x i1> @select_cond_cond_x(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {731; CHECK-LABEL: select_cond_cond_x:732; CHECK: # %bb.0:733; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma734; CHECK-NEXT: vmor.mm v0, v0, v8735; CHECK-NEXT: ret736 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 %evl)737 ret <vscale x 2 x i1> %a738}739 740define <vscale x 2 x i1> @select_cond_x_cond(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %m, i32 zeroext %evl) {741; CHECK-LABEL: select_cond_x_cond:742; CHECK: # %bb.0:743; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma744; CHECK-NEXT: vmand.mm v0, v0, v8745; CHECK-NEXT: ret746 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %x, i32 %evl)747 ret <vscale x 2 x i1> %a748}749 750define <vscale x 2 x i1> @select_undef_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {751; CHECK-LABEL: select_undef_T_F:752; CHECK: # %bb.0:753; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma754; CHECK-NEXT: vmv1r.v v0, v8755; CHECK-NEXT: ret756 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 %evl)757 ret <vscale x 2 x i1> %a758}759 760define <vscale x 2 x i1> @select_undef_undef_F(<vscale x 2 x i1> %x, i32 zeroext %evl) {761; CHECK-LABEL: select_undef_undef_F:762; CHECK: # %bb.0:763; CHECK-NEXT: ret764 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> poison, <vscale x 2 x i1> poison, <vscale x 2 x i1> %x, i32 %evl)765 ret <vscale x 2 x i1> %a766}767 768define <vscale x 2 x i1> @select_unknown_undef_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {769; CHECK-LABEL: select_unknown_undef_F:770; CHECK: # %bb.0:771; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma772; CHECK-NEXT: vmv1r.v v0, v8773; CHECK-NEXT: ret774 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> poison, <vscale x 2 x i1> %y, i32 %evl)775 ret <vscale x 2 x i1> %a776}777 778define <vscale x 2 x i1> @select_unknown_T_undef(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {779; CHECK-LABEL: select_unknown_T_undef:780; CHECK: # %bb.0:781; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma782; CHECK-NEXT: vmv1r.v v0, v8783; CHECK-NEXT: ret784 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> poison, i32 %evl)785 ret <vscale x 2 x i1> %a786}787 788define <vscale x 2 x i1> @select_false_T_F(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 zeroext %evl) {789; CHECK-LABEL: select_false_T_F:790; CHECK: # %bb.0:791; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma792; CHECK-NEXT: vmv1r.v v0, v9793; CHECK-NEXT: ret794 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> zeroinitializer, <vscale x 2 x i1> %y, <vscale x 2 x i1> %z, i32 %evl)795 ret <vscale x 2 x i1> %a796}797 798define <vscale x 2 x i1> @select_unknown_T_T(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, i32 zeroext %evl) {799; CHECK-LABEL: select_unknown_T_T:800; CHECK: # %bb.0:801; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma802; CHECK-NEXT: vmv1r.v v0, v8803; CHECK-NEXT: ret804 %a = call <vscale x 2 x i1> @llvm.vp.select.nxv2i1(<vscale x 2 x i1> %x, <vscale x 2 x i1> %y, <vscale x 2 x i1> %y, i32 %evl)805 ret <vscale x 2 x i1> %a806}807