635 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s3 4define signext i32 @vsetvl_sext() {5; CHECK-LABEL: vsetvl_sext:6; CHECK: # %bb.0:7; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma8; CHECK-NEXT: ret9 %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)10 %b = trunc i64 %a to i3211 ret i32 %b12}13 14define zeroext i32 @vsetvl_zext() {15; CHECK-LABEL: vsetvl_zext:16; CHECK: # %bb.0:17; CHECK-NEXT: vsetivli a0, 1, e16, m2, ta, ma18; CHECK-NEXT: ret19 %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 1, i64 1)20 %b = trunc i64 %a to i3221 ret i32 %b22}23 24define i64 @vsetvl_e8m1_and14bits(i64 %avl) {25; CHECK-LABEL: vsetvl_e8m1_and14bits:26; CHECK: # %bb.0:27; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, ma28; CHECK-NEXT: ret29 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 0)30 %b = and i64 %a, 1638331 ret i64 %b32}33 34define i64 @vsetvl_e8m1_and13bits(i64 %avl) {35; CHECK-LABEL: vsetvl_e8m1_and13bits:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetvli a0, a0, e8, m1, ta, ma38; CHECK-NEXT: slli a0, a0, 5139; CHECK-NEXT: srli a0, a0, 5140; CHECK-NEXT: ret41 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 0)42 %b = and i64 %a, 819143 ret i64 %b44}45 46define i64 @vsetvl_e8m1_constant_avl() {47; CHECK-LABEL: vsetvl_e8m1_constant_avl:48; CHECK: # %bb.0:49; CHECK-NEXT: vsetivli a0, 1, e8, m1, ta, ma50; CHECK-NEXT: ret51 %a = call i64 @llvm.riscv.vsetvli(i64 1, i64 0, i64 0)52 %b = and i64 %a, 153 ret i64 %b54}55 56define i64 @vsetvl_e8m2_and15bits(i64 %avl) {57; CHECK-LABEL: vsetvl_e8m2_and15bits:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetvli a0, a0, e8, m2, ta, ma60; CHECK-NEXT: ret61 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 1)62 %b = and i64 %a, 3276763 ret i64 %b64}65 66define i64 @vsetvl_e8m2_and14bits(i64 %avl) {67; CHECK-LABEL: vsetvl_e8m2_and14bits:68; CHECK: # %bb.0:69; CHECK-NEXT: vsetvli a0, a0, e8, m2, ta, ma70; CHECK-NEXT: slli a0, a0, 5071; CHECK-NEXT: srli a0, a0, 5072; CHECK-NEXT: ret73 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 1)74 %b = and i64 %a, 1638375 ret i64 %b76}77 78define i64 @vsetvl_e8m4_and16bits(i64 %avl) {79; CHECK-LABEL: vsetvl_e8m4_and16bits:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetvli a0, a0, e8, m4, ta, ma82; CHECK-NEXT: ret83 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 2)84 %b = and i64 %a, 6553585 ret i64 %b86}87 88define i64 @vsetvl_e8m4_and15bits(i64 %avl) {89; CHECK-LABEL: vsetvl_e8m4_and15bits:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli a0, a0, e8, m4, ta, ma92; CHECK-NEXT: slli a0, a0, 4993; CHECK-NEXT: srli a0, a0, 4994; CHECK-NEXT: ret95 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 2)96 %b = and i64 %a, 3276797 ret i64 %b98}99 100define i64 @vsetvl_e8m8_and17bits(i64 %avl) {101; CHECK-LABEL: vsetvl_e8m8_and17bits:102; CHECK: # %bb.0:103; CHECK-NEXT: vsetvli a0, a0, e8, m8, ta, ma104; CHECK-NEXT: ret105 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 3)106 %b = and i64 %a, 131071107 ret i64 %b108}109 110define i64 @vsetvl_e8m8_and16bits(i64 %avl) {111; CHECK-LABEL: vsetvl_e8m8_and16bits:112; CHECK: # %bb.0:113; CHECK-NEXT: vsetvli a0, a0, e8, m8, ta, ma114; CHECK-NEXT: slli a0, a0, 48115; CHECK-NEXT: srli a0, a0, 48116; CHECK-NEXT: ret117 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 3)118 %b = and i64 %a, 65535119 ret i64 %b120}121 122define i64 @vsetvl_e8mf2_and11bits(i64 %avl) {123; CHECK-LABEL: vsetvl_e8mf2_and11bits:124; CHECK: # %bb.0:125; CHECK-NEXT: vsetvli a0, a0, e8, mf8, ta, ma126; CHECK-NEXT: ret127 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 5)128 %b = and i64 %a, 2047129 ret i64 %b130}131 132define i64 @vsetvl_e8mf2_and10bits(i64 %avl) {133; CHECK-LABEL: vsetvl_e8mf2_and10bits:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli a0, a0, e8, mf8, ta, ma136; CHECK-NEXT: andi a0, a0, 1023137; CHECK-NEXT: ret138 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 5)139 %b = and i64 %a, 1023140 ret i64 %b141}142 143define i64 @vsetvl_e8mf4_and12bits(i64 %avl) {144; CHECK-LABEL: vsetvl_e8mf4_and12bits:145; CHECK: # %bb.0:146; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma147; CHECK-NEXT: ret148 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 6)149 %b = and i64 %a, 4095150 ret i64 %b151}152 153define i64 @vsetvl_e8mf4_and11bits(i64 %avl) {154; CHECK-LABEL: vsetvl_e8mf4_and11bits:155; CHECK: # %bb.0:156; CHECK-NEXT: vsetvli a0, a0, e8, mf4, ta, ma157; CHECK-NEXT: andi a0, a0, 2047158; CHECK-NEXT: ret159 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 6)160 %b = and i64 %a, 2047161 ret i64 %b162}163 164define i64 @vsetvl_e8mf8_and13bits(i64 %avl) {165; CHECK-LABEL: vsetvl_e8mf8_and13bits:166; CHECK: # %bb.0:167; CHECK-NEXT: vsetvli a0, a0, e8, mf2, ta, ma168; CHECK-NEXT: ret169 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 7)170 %b = and i64 %a, 8191171 ret i64 %b172}173 174define i64 @vsetvl_e8mf8_and12bits(i64 %avl) {175; CHECK-LABEL: vsetvl_e8mf8_and12bits:176; CHECK: # %bb.0:177; CHECK-NEXT: vsetvli a0, a0, e8, mf2, ta, ma178; CHECK-NEXT: slli a0, a0, 52179; CHECK-NEXT: srli a0, a0, 52180; CHECK-NEXT: ret181 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 0, i64 7)182 %b = and i64 %a, 4095183 ret i64 %b184}185 186define i64 @vsetvl_e16m1_and13bits(i64 %avl) {187; CHECK-LABEL: vsetvl_e16m1_and13bits:188; CHECK: # %bb.0:189; CHECK-NEXT: vsetvli a0, a0, e16, m1, ta, ma190; CHECK-NEXT: ret191 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 0)192 %b = and i64 %a, 8191193 ret i64 %b194}195 196define i64 @vsetvl_e16m1_and12bits(i64 %avl) {197; CHECK-LABEL: vsetvl_e16m1_and12bits:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetvli a0, a0, e16, m1, ta, ma200; CHECK-NEXT: slli a0, a0, 52201; CHECK-NEXT: srli a0, a0, 52202; CHECK-NEXT: ret203 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 0)204 %b = and i64 %a, 4095205 ret i64 %b206}207 208define i64 @vsetvl_e16m2_and14bits(i64 %avl) {209; CHECK-LABEL: vsetvl_e16m2_and14bits:210; CHECK: # %bb.0:211; CHECK-NEXT: vsetvli a0, a0, e16, m2, ta, ma212; CHECK-NEXT: ret213 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 1)214 %b = and i64 %a, 16383215 ret i64 %b216}217 218define i64 @vsetvl_e16m2_and13bits(i64 %avl) {219; CHECK-LABEL: vsetvl_e16m2_and13bits:220; CHECK: # %bb.0:221; CHECK-NEXT: vsetvli a0, a0, e16, m2, ta, ma222; CHECK-NEXT: slli a0, a0, 51223; CHECK-NEXT: srli a0, a0, 51224; CHECK-NEXT: ret225 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 1)226 %b = and i64 %a, 8191227 ret i64 %b228}229 230define i64 @vsetvl_e16m4_and15bits(i64 %avl) {231; CHECK-LABEL: vsetvl_e16m4_and15bits:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli a0, a0, e16, m4, ta, ma234; CHECK-NEXT: ret235 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 2)236 %b = and i64 %a, 32767237 ret i64 %b238}239 240define i64 @vsetvl_e16m4_and14bits(i64 %avl) {241; CHECK-LABEL: vsetvl_e16m4_and14bits:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli a0, a0, e16, m4, ta, ma244; CHECK-NEXT: slli a0, a0, 50245; CHECK-NEXT: srli a0, a0, 50246; CHECK-NEXT: ret247 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 2)248 %b = and i64 %a, 16383249 ret i64 %b250}251 252define i64 @vsetvl_e16m8_and16bits(i64 %avl) {253; CHECK-LABEL: vsetvl_e16m8_and16bits:254; CHECK: # %bb.0:255; CHECK-NEXT: vsetvli a0, a0, e16, m8, ta, ma256; CHECK-NEXT: ret257 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 3)258 %b = and i64 %a, 65535259 ret i64 %b260}261 262define i64 @vsetvl_e16m8_and15bits(i64 %avl) {263; CHECK-LABEL: vsetvl_e16m8_and15bits:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli a0, a0, e16, m8, ta, ma266; CHECK-NEXT: slli a0, a0, 49267; CHECK-NEXT: srli a0, a0, 49268; CHECK-NEXT: ret269 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 3)270 %b = and i64 %a, 32767271 ret i64 %b272}273 274define i64 @vsetvl_e16mf2_and10bits(i64 %avl) {275; CHECK-LABEL: vsetvl_e16mf2_and10bits:276; CHECK: # %bb.0:277; CHECK-NEXT: vsetvli a0, a0, e16, mf8, ta, ma278; CHECK-NEXT: ret279 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 5)280 %b = and i64 %a, 1023281 ret i64 %b282}283 284define i64 @vsetvl_e16mf2_and9bits(i64 %avl) {285; CHECK-LABEL: vsetvl_e16mf2_and9bits:286; CHECK: # %bb.0:287; CHECK-NEXT: vsetvli a0, a0, e16, mf8, ta, ma288; CHECK-NEXT: andi a0, a0, 511289; CHECK-NEXT: ret290 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 5)291 %b = and i64 %a, 511292 ret i64 %b293}294 295define i64 @vsetvl_e16mf4_and11bits(i64 %avl) {296; CHECK-LABEL: vsetvl_e16mf4_and11bits:297; CHECK: # %bb.0:298; CHECK-NEXT: vsetvli a0, a0, e16, mf4, ta, ma299; CHECK-NEXT: ret300 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 6)301 %b = and i64 %a, 2047302 ret i64 %b303}304 305define i64 @vsetvl_e16mf4_and10bits(i64 %avl) {306; CHECK-LABEL: vsetvl_e16mf4_and10bits:307; CHECK: # %bb.0:308; CHECK-NEXT: vsetvli a0, a0, e16, mf4, ta, ma309; CHECK-NEXT: andi a0, a0, 1023310; CHECK-NEXT: ret311 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 6)312 %b = and i64 %a, 1023313 ret i64 %b314}315 316define i64 @vsetvl_e16mf8_and12bits(i64 %avl) {317; CHECK-LABEL: vsetvl_e16mf8_and12bits:318; CHECK: # %bb.0:319; CHECK-NEXT: vsetvli a0, a0, e16, mf2, ta, ma320; CHECK-NEXT: ret321 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 7)322 %b = and i64 %a, 4095323 ret i64 %b324}325 326define i64 @vsetvl_e16mf8_and11bits(i64 %avl) {327; CHECK-LABEL: vsetvl_e16mf8_and11bits:328; CHECK: # %bb.0:329; CHECK-NEXT: vsetvli a0, a0, e16, mf2, ta, ma330; CHECK-NEXT: andi a0, a0, 2047331; CHECK-NEXT: ret332 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 1, i64 7)333 %b = and i64 %a, 2047334 ret i64 %b335}336 337define i64 @vsetvl_e32m1_and12bits(i64 %avl) {338; CHECK-LABEL: vsetvl_e32m1_and12bits:339; CHECK: # %bb.0:340; CHECK-NEXT: vsetvli a0, a0, e32, m1, ta, ma341; CHECK-NEXT: ret342 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)343 %b = and i64 %a, 4095344 ret i64 %b345}346 347define i64 @vsetvl_e32m1_and11bits(i64 %avl) {348; CHECK-LABEL: vsetvl_e32m1_and11bits:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a0, a0, e32, m1, ta, ma351; CHECK-NEXT: andi a0, a0, 2047352; CHECK-NEXT: ret353 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 0)354 %b = and i64 %a, 2047355 ret i64 %b356}357 358define i64 @vsetvl_e32m2_and13bits(i64 %avl) {359; CHECK-LABEL: vsetvl_e32m2_and13bits:360; CHECK: # %bb.0:361; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, ma362; CHECK-NEXT: ret363 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 1)364 %b = and i64 %a, 8191365 ret i64 %b366}367 368define i64 @vsetvl_e32m2_and12bits(i64 %avl) {369; CHECK-LABEL: vsetvl_e32m2_and12bits:370; CHECK: # %bb.0:371; CHECK-NEXT: vsetvli a0, a0, e32, m2, ta, ma372; CHECK-NEXT: slli a0, a0, 52373; CHECK-NEXT: srli a0, a0, 52374; CHECK-NEXT: ret375 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 1)376 %b = and i64 %a, 4095377 ret i64 %b378}379 380define i64 @vsetvl_e32m4_and14bits(i64 %avl) {381; CHECK-LABEL: vsetvl_e32m4_and14bits:382; CHECK: # %bb.0:383; CHECK-NEXT: vsetvli a0, a0, e32, m4, ta, ma384; CHECK-NEXT: ret385 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 2)386 %b = and i64 %a, 16383387 ret i64 %b388}389 390define i64 @vsetvl_e32m4_and13bits(i64 %avl) {391; CHECK-LABEL: vsetvl_e32m4_and13bits:392; CHECK: # %bb.0:393; CHECK-NEXT: vsetvli a0, a0, e32, m4, ta, ma394; CHECK-NEXT: slli a0, a0, 51395; CHECK-NEXT: srli a0, a0, 51396; CHECK-NEXT: ret397 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 2)398 %b = and i64 %a, 8191399 ret i64 %b400}401 402define i64 @vsetvl_e32m8_and15bits(i64 %avl) {403; CHECK-LABEL: vsetvl_e32m8_and15bits:404; CHECK: # %bb.0:405; CHECK-NEXT: vsetvli a0, a0, e32, m8, ta, ma406; CHECK-NEXT: ret407 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 3)408 %b = and i64 %a, 32767409 ret i64 %b410}411 412define i64 @vsetvl_e32m8_and14bits(i64 %avl) {413; CHECK-LABEL: vsetvl_e32m8_and14bits:414; CHECK: # %bb.0:415; CHECK-NEXT: vsetvli a0, a0, e32, m8, ta, ma416; CHECK-NEXT: slli a0, a0, 50417; CHECK-NEXT: srli a0, a0, 50418; CHECK-NEXT: ret419 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 3)420 %b = and i64 %a, 16383421 ret i64 %b422}423 424define i64 @vsetvl_e32mf2_and9bits(i64 %avl) {425; CHECK-LABEL: vsetvl_e32mf2_and9bits:426; CHECK: # %bb.0:427; CHECK-NEXT: vsetvli a0, a0, e32, mf8, ta, ma428; CHECK-NEXT: ret429 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 5)430 %b = and i64 %a, 511431 ret i64 %b432}433 434define i64 @vsetvl_e32mf2_and8bits(i64 %avl) {435; CHECK-LABEL: vsetvl_e32mf2_and8bits:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a0, a0, e32, mf8, ta, ma438; CHECK-NEXT: zext.b a0, a0439; CHECK-NEXT: ret440 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 5)441 %b = and i64 %a, 255442 ret i64 %b443}444 445define i64 @vsetvl_e32mf4_and10bits(i64 %avl) {446; CHECK-LABEL: vsetvl_e32mf4_and10bits:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, a0, e32, mf4, ta, ma449; CHECK-NEXT: ret450 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 6)451 %b = and i64 %a, 1023452 ret i64 %b453}454 455define i64 @vsetvl_e32mf4_and9bits(i64 %avl) {456; CHECK-LABEL: vsetvl_e32mf4_and9bits:457; CHECK: # %bb.0:458; CHECK-NEXT: vsetvli a0, a0, e32, mf4, ta, ma459; CHECK-NEXT: andi a0, a0, 511460; CHECK-NEXT: ret461 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 6)462 %b = and i64 %a, 511463 ret i64 %b464}465 466define i64 @vsetvl_e32mf8_and11bits(i64 %avl) {467; CHECK-LABEL: vsetvl_e32mf8_and11bits:468; CHECK: # %bb.0:469; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma470; CHECK-NEXT: ret471 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)472 %b = and i64 %a, 2047473 ret i64 %b474}475 476define i64 @vsetvl_e32mf8_and10bits(i64 %avl) {477; CHECK-LABEL: vsetvl_e32mf8_and10bits:478; CHECK: # %bb.0:479; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma480; CHECK-NEXT: andi a0, a0, 1023481; CHECK-NEXT: ret482 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)483 %b = and i64 %a, 1023484 ret i64 %b485}486 487define i64 @vsetvl_e64m1_and11bits(i64 %avl) {488; CHECK-LABEL: vsetvl_e64m1_and11bits:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma491; CHECK-NEXT: ret492 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)493 %b = and i64 %a, 2047494 ret i64 %b495}496 497define i64 @vsetvl_e64m1_and10bits(i64 %avl) {498; CHECK-LABEL: vsetvl_e64m1_and10bits:499; CHECK: # %bb.0:500; CHECK-NEXT: vsetvli a0, a0, e64, m1, ta, ma501; CHECK-NEXT: andi a0, a0, 1023502; CHECK-NEXT: ret503 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 0)504 %b = and i64 %a, 1023505 ret i64 %b506}507 508define i64 @vsetvl_e64m2_and12bits(i64 %avl) {509; CHECK-LABEL: vsetvl_e64m2_and12bits:510; CHECK: # %bb.0:511; CHECK-NEXT: vsetvli a0, a0, e64, m2, ta, ma512; CHECK-NEXT: ret513 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 1)514 %b = and i64 %a, 4095515 ret i64 %b516}517 518define i64 @vsetvl_e64m2_and11bits(i64 %avl) {519; CHECK-LABEL: vsetvl_e64m2_and11bits:520; CHECK: # %bb.0:521; CHECK-NEXT: vsetvli a0, a0, e64, m2, ta, ma522; CHECK-NEXT: andi a0, a0, 2047523; CHECK-NEXT: ret524 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 1)525 %b = and i64 %a, 2047526 ret i64 %b527}528 529define i64 @vsetvl_e64m4_and13bits(i64 %avl) {530; CHECK-LABEL: vsetvl_e64m4_and13bits:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a0, a0, e64, m4, ta, ma533; CHECK-NEXT: ret534 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 2)535 %b = and i64 %a, 8191536 ret i64 %b537}538 539define i64 @vsetvl_e64m4_and12bits(i64 %avl) {540; CHECK-LABEL: vsetvl_e64m4_and12bits:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli a0, a0, e64, m4, ta, ma543; CHECK-NEXT: slli a0, a0, 52544; CHECK-NEXT: srli a0, a0, 52545; CHECK-NEXT: ret546 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 2)547 %b = and i64 %a, 4095548 ret i64 %b549}550 551define i64 @vsetvl_e64m8_and14bits(i64 %avl) {552; CHECK-LABEL: vsetvl_e64m8_and14bits:553; CHECK: # %bb.0:554; CHECK-NEXT: vsetvli a0, a0, e64, m8, ta, ma555; CHECK-NEXT: ret556 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 3)557 %b = and i64 %a, 16383558 ret i64 %b559}560 561define i64 @vsetvl_e64m8_and13bits(i64 %avl) {562; CHECK-LABEL: vsetvl_e64m8_and13bits:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli a0, a0, e64, m8, ta, ma565; CHECK-NEXT: slli a0, a0, 51566; CHECK-NEXT: srli a0, a0, 51567; CHECK-NEXT: ret568 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 3)569 %b = and i64 %a, 8191570 ret i64 %b571}572 573define i64 @vsetvl_e64mf2_and8bits(i64 %avl) {574; CHECK-LABEL: vsetvl_e64mf2_and8bits:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli a0, a0, e64, mf8, ta, ma577; CHECK-NEXT: ret578 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 5)579 %b = and i64 %a, 255580 ret i64 %b581}582 583define i64 @vsetvl_e64mf2_and7bits(i64 %avl) {584; CHECK-LABEL: vsetvl_e64mf2_and7bits:585; CHECK: # %bb.0:586; CHECK-NEXT: vsetvli a0, a0, e64, mf8, ta, ma587; CHECK-NEXT: andi a0, a0, 127588; CHECK-NEXT: ret589 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 5)590 %b = and i64 %a, 127591 ret i64 %b592}593 594define i64 @vsetvl_e64mf4_and9bits(i64 %avl) {595; CHECK-LABEL: vsetvl_e64mf4_and9bits:596; CHECK: # %bb.0:597; CHECK-NEXT: vsetvli a0, a0, e64, mf4, ta, ma598; CHECK-NEXT: ret599 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 6)600 %b = and i64 %a, 511601 ret i64 %b602}603 604define i64 @vsetvl_e64mf4_and8bits(i64 %avl) {605; CHECK-LABEL: vsetvl_e64mf4_and8bits:606; CHECK: # %bb.0:607; CHECK-NEXT: vsetvli a0, a0, e64, mf4, ta, ma608; CHECK-NEXT: zext.b a0, a0609; CHECK-NEXT: ret610 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 6)611 %b = and i64 %a, 255612 ret i64 %b613}614 615define i64 @vsetvl_e64mf8_and10bits(i64 %avl) {616; CHECK-LABEL: vsetvl_e64mf8_and10bits:617; CHECK: # %bb.0:618; CHECK-NEXT: vsetvli a0, a0, e64, mf2, ta, ma619; CHECK-NEXT: ret620 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)621 %b = and i64 %a, 1023622 ret i64 %b623}624 625define i64 @vsetvl_e64mf8_and9bits(i64 %avl) {626; CHECK-LABEL: vsetvl_e64mf8_and9bits:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetvli a0, a0, e64, mf2, ta, ma629; CHECK-NEXT: andi a0, a0, 511630; CHECK-NEXT: ret631 %a = call i64 @llvm.riscv.vsetvli(i64 %avl, i64 3, i64 7)632 %b = and i64 %a, 511633 ret i64 %b634}635