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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+m,+f,+d,+a,+c,+v \3; RUN: -target-abi=lp64d -verify-machineinstrs -O0 < %s | FileCheck %s4 5define <2 x double> @fixed_length(<2 x double> %a, <2 x double> %b) nounwind {6; CHECK-LABEL: fixed_length:7; CHECK: # %bb.0: # %entry8; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma9; CHECK-NEXT: vmv1r.v v10, v910; CHECK-NEXT: # kill: def $v11 killed $v1011; CHECK-NEXT: # kill: def $v9 killed $v812; CHECK-NEXT: # implicit-def: $v913; CHECK-NEXT: vfadd.vv v9, v8, v1014; CHECK-NEXT: # implicit-def: $v815; CHECK-NEXT: vfadd.vv v8, v9, v1016; CHECK-NEXT: ret17entry:18 %1 = fadd <2 x double> %a, %b19 %2 = fadd <2 x double> %1, %b20 ret <2 x double> %221}22 23define <vscale x 1 x double> @scalable(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {24; CHECK-LABEL: scalable:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma27; CHECK-NEXT: vmv1r.v v10, v928; CHECK-NEXT: # implicit-def: $v929; CHECK-NEXT: vfadd.vv v9, v8, v1030; CHECK-NEXT: # implicit-def: $v831; CHECK-NEXT: vfadd.vv v8, v9, v1032; CHECK-NEXT: ret33entry:34 %1 = fadd <vscale x 1 x double> %a, %b35 %2 = fadd <vscale x 1 x double> %1, %b36 ret <vscale x 1 x double> %237}38 39define <vscale x 1 x double> @intrinsic_same_vlmax(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {40; CHECK-LABEL: intrinsic_same_vlmax:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma43; CHECK-NEXT: vmv1r.v v10, v944; CHECK-NEXT: # implicit-def: $v945; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma46; CHECK-NEXT: vfadd.vv v9, v8, v1047; CHECK-NEXT: # implicit-def: $v848; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma49; CHECK-NEXT: vfadd.vv v8, v9, v1050; CHECK-NEXT: ret51entry:52 %0 = tail call i64 @llvm.riscv.vsetvlimax(i64 2, i64 7)53 %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(54 <vscale x 1 x double> poison,55 <vscale x 1 x double> %a,56 <vscale x 1 x double> %b,57 i64 7, i64 %0)58 %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(59 <vscale x 1 x double> poison,60 <vscale x 1 x double> %1,61 <vscale x 1 x double> %b,62 i64 7, i64 %0)63 ret <vscale x 1 x double> %264}65 66define <vscale x 1 x double> @intrinsic_same_avl_imm(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {67; CHECK-LABEL: intrinsic_same_avl_imm:68; CHECK: # %bb.0: # %entry69; CHECK-NEXT: vsetivli a0, 2, e32, mf2, ta, ma70; CHECK-NEXT: vmv1r.v v10, v971; CHECK-NEXT: # implicit-def: $v972; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma73; CHECK-NEXT: vfadd.vv v9, v8, v1074; CHECK-NEXT: # implicit-def: $v875; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma76; CHECK-NEXT: vfadd.vv v8, v9, v1077; CHECK-NEXT: ret78entry:79 %0 = tail call i64 @llvm.riscv.vsetvli(i64 2, i64 2, i64 7)80 %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(81 <vscale x 1 x double> poison,82 <vscale x 1 x double> %a,83 <vscale x 1 x double> %b,84 i64 7, i64 %0)85 %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(86 <vscale x 1 x double> poison,87 <vscale x 1 x double> %1,88 <vscale x 1 x double> %b,89 i64 7, i64 %0)90 ret <vscale x 1 x double> %291}92 93define <vscale x 1 x double> @intrinsic_same_avl_reg(i64 %avl, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {94; CHECK-LABEL: intrinsic_same_avl_reg:95; CHECK: # %bb.0: # %entry96; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma97; CHECK-NEXT: vmv1r.v v10, v998; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma99; CHECK-NEXT: # implicit-def: $v9100; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma101; CHECK-NEXT: vfadd.vv v9, v8, v10102; CHECK-NEXT: # implicit-def: $v8103; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma104; CHECK-NEXT: vfadd.vv v8, v9, v10105; CHECK-NEXT: ret106entry:107 %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)108 %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(109 <vscale x 1 x double> poison,110 <vscale x 1 x double> %a,111 <vscale x 1 x double> %b,112 i64 7, i64 %0)113 %2 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(114 <vscale x 1 x double> poison,115 <vscale x 1 x double> %1,116 <vscale x 1 x double> %b,117 i64 7, i64 %0)118 ret <vscale x 1 x double> %2119}120 121define <vscale x 1 x double> @intrinsic_diff_avl_reg(i64 %avl, i64 %avl2, <vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {122; CHECK-LABEL: intrinsic_diff_avl_reg:123; CHECK: # %bb.0: # %entry124; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma125; CHECK-NEXT: vmv1r.v v10, v9126; CHECK-NEXT: vsetvli a0, a0, e32, mf2, ta, ma127; CHECK-NEXT: # implicit-def: $v9128; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma129; CHECK-NEXT: vfadd.vv v9, v8, v10130; CHECK-NEXT: vsetvli a0, a1, e32, mf2, ta, ma131; CHECK-NEXT: # implicit-def: $v8132; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma133; CHECK-NEXT: vfadd.vv v8, v9, v10134; CHECK-NEXT: ret135entry:136 %0 = tail call i64 @llvm.riscv.vsetvli(i64 %avl, i64 2, i64 7)137 %1 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(138 <vscale x 1 x double> poison,139 <vscale x 1 x double> %a,140 <vscale x 1 x double> %b,141 i64 7, i64 %0)142 %2 = tail call i64 @llvm.riscv.vsetvli(i64 %avl2, i64 2, i64 7)143 %3 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(144 <vscale x 1 x double> poison,145 <vscale x 1 x double> %1,146 <vscale x 1 x double> %b,147 i64 7, i64 %2)148 ret <vscale x 1 x double> %3149}150