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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -verify-machineinstrs \3# RUN: -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s4 5--- |6 source_filename = "vsetvli-insert.ll"7 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"8 target triple = "riscv64"9 10 define <vscale x 1 x i64> @load_add_or_sub(i8 zeroext %cond, ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {11 entry:12 %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)13 %tobool = icmp eq i8 %cond, 014 br i1 %tobool, label %if.else, label %if.then15 16 if.then: ; preds = %entry17 %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)18 br label %if.end19 20 if.else: ; preds = %entry21 %c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)22 br label %if.end23 24 if.end: ; preds = %if.else, %if.then25 %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]26 ret <vscale x 1 x i64> %d27 }28 29 define void @load_zext_or_sext(i8 zeroext %cond, ptr %0, ptr %1, i64 %2) #0 {30 entry:31 %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr %0, i64 %2)32 %tobool = icmp eq i8 %cond, 033 br i1 %tobool, label %if.else, label %if.then34 35 if.then: ; preds = %entry36 %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)37 br label %if.end38 39 if.else: ; preds = %entry40 %c = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %2)41 br label %if.end42 43 if.end: ; preds = %if.else, %if.then44 %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]45 call void @llvm.riscv.vse.nxv1i64.i64(<vscale x 1 x i64> %d, ptr %1, i64 %2)46 ret void47 }48 49 define i64 @vmv_x_s(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {50 entry:51 %tobool = icmp eq i8 %cond, 052 br i1 %tobool, label %if.else, label %if.then53 54 if.then: ; preds = %entry55 %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)56 br label %if.end57 58 if.else: ; preds = %entry59 %b = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %1, <vscale x 1 x i64> %1, i64 %2)60 br label %if.end61 62 if.end: ; preds = %if.else, %if.then63 %c = phi <vscale x 1 x i64> [ %a, %if.then ], [ %b, %if.else ]64 %d = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %c)65 ret i64 %d66 }67 68 define <vscale x 1 x i64> @vsetvli_add_or_sub(i8 zeroext %cond, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {69 entry:70 %vl = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)71 %tobool = icmp eq i8 %cond, 072 br i1 %tobool, label %if.else, label %if.then73 74 if.then: ; preds = %entry75 %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)76 br label %if.end77 78 if.else: ; preds = %entry79 %c = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %vl)80 br label %if.end81 82 if.end: ; preds = %if.else, %if.then83 %d = phi <vscale x 1 x i64> [ %b, %if.then ], [ %c, %if.else ]84 ret <vscale x 1 x i64> %d85 }86 87 define void @vsetvli_vcpop() {88 ret void89 }90 91 define void @vsetvli_loop_store() {92 ret void93 }94 95 define void @vsetvli_loop_store2() {96 ret void97 }98 99 define void @redusum_loop(ptr nocapture noundef readonly %a, i32 noundef signext %n, ptr nocapture noundef writeonly %res) #0 {100 entry:101 br label %vector.body102 103 vector.body: ; preds = %vector.body, %entry104 %lsr.iv1 = phi ptr [ %scevgep, %vector.body ], [ %a, %entry ]105 %lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ 2048, %entry ]106 %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %0, %vector.body ]107 %lsr.iv12 = bitcast ptr %lsr.iv1 to ptr108 %wide.load = load <4 x i32>, ptr %lsr.iv12, align 4109 %0 = add <4 x i32> %wide.load, %vec.phi110 %lsr.iv.next = add nsw i64 %lsr.iv, -4111 %scevgep = getelementptr i32, ptr %lsr.iv1, i64 4112 %1 = icmp eq i64 %lsr.iv.next, 0113 br i1 %1, label %middle.block, label %vector.body114 115 middle.block: ; preds = %vector.body116 %2 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %0)117 store i32 %2, ptr %res, align 4118 ret void119 }120 121 define void @vsetvli_vluxei64_regression() {122 ret void123 }124 125 define void @if_in_loop() {126 ret void127 }128 129 define void @pre_undemanded_vl() {130 ret void131 }132 133 define void @clobberred_forwarded_avl() {134 ret void135 }136 137 define void @clobberred_forwarded_phi_avl() {138 ret void139 }140 141 define void @avl_is_last_instr() {142 ret void143 }144 145 attributes #0 = { "target-features"="+v" }146 147...148---149name: load_add_or_sub150alignment: 4151tracksRegLiveness: true152registers:153 - { id: 0, class: vr }154 - { id: 1, class: vr }155 - { id: 2, class: vr }156 - { id: 3, class: vr }157 - { id: 4, class: gpr }158 - { id: 5, class: gpr }159 - { id: 6, class: vr }160 - { id: 7, class: gprnox0 }161 - { id: 8, class: gpr }162liveins:163 - { reg: '$x10', virtual-reg: '%4' }164 - { reg: '$x11', virtual-reg: '%5' }165 - { reg: '$v8', virtual-reg: '%6' }166 - { reg: '$x12', virtual-reg: '%7' }167frameInfo:168 maxAlignment: 1169machineFunctionInfo: {}170body: |171 ; CHECK-LABEL: name: load_add_or_sub172 ; CHECK: bb.0.entry:173 ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)174 ; CHECK-NEXT: liveins: $x10, $x11, $v8, $x12175 ; CHECK-NEXT: {{ $}}176 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12177 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8178 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11179 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10180 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype181 ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype182 ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2183 ; CHECK-NEXT: PseudoBR %bb.1184 ; CHECK-NEXT: {{ $}}185 ; CHECK-NEXT: bb.1.if.then:186 ; CHECK-NEXT: successors: %bb.3(0x80000000)187 ; CHECK-NEXT: {{ $}}188 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype189 ; CHECK-NEXT: PseudoBR %bb.3190 ; CHECK-NEXT: {{ $}}191 ; CHECK-NEXT: bb.2.if.else:192 ; CHECK-NEXT: successors: %bb.3(0x80000000)193 ; CHECK-NEXT: {{ $}}194 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype195 ; CHECK-NEXT: {{ $}}196 ; CHECK-NEXT: bb.3.if.end:197 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]198 ; CHECK-NEXT: PseudoRET implicit $v8199 bb.0.entry:200 successors: %bb.2(0x30000000), %bb.1(0x50000000)201 liveins: $x10, $x11, $v8, $x12202 203 %7:gprnox0 = COPY $x12204 %6:vr = COPY $v8205 %5:gpr = COPY $x11206 %4:gpr = COPY $x10207 %0:vr = PseudoVLE64_V_M1 undef $noreg, %5, %7, 6, 0208 %8:gpr = COPY $x0209 BEQ %4, %8, %bb.2210 PseudoBR %bb.1211 212 bb.1.if.then:213 %1:vr = PseudoVADD_VV_M1 undef $noreg, %0, %6, %7, 6, 0214 PseudoBR %bb.3215 216 bb.2.if.else:217 %2:vr = PseudoVSUB_VV_M1 undef $noreg, %0, %6, %7, 6, 0218 219 bb.3.if.end:220 %3:vr = PHI %1, %bb.1, %2, %bb.2221 $v8 = COPY %3222 PseudoRET implicit $v8223 224...225---226name: load_zext_or_sext227alignment: 4228tracksRegLiveness: true229registers:230 - { id: 0, class: vr }231 - { id: 1, class: vr }232 - { id: 2, class: vr }233 - { id: 3, class: vr }234 - { id: 4, class: gpr }235 - { id: 5, class: gpr }236 - { id: 6, class: gpr }237 - { id: 7, class: gprnox0 }238 - { id: 8, class: gpr }239liveins:240 - { reg: '$x10', virtual-reg: '%4' }241 - { reg: '$x11', virtual-reg: '%5' }242 - { reg: '$x12', virtual-reg: '%6' }243 - { reg: '$x13', virtual-reg: '%7' }244frameInfo:245 maxAlignment: 1246machineFunctionInfo: {}247body: |248 ; CHECK-LABEL: name: load_zext_or_sext249 ; CHECK: bb.0.entry:250 ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)251 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13252 ; CHECK-NEXT: {{ $}}253 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x13254 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12255 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11256 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10257 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype258 ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY2]], $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype259 ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2260 ; CHECK-NEXT: PseudoBR %bb.1261 ; CHECK-NEXT: {{ $}}262 ; CHECK-NEXT: bb.1.if.then:263 ; CHECK-NEXT: successors: %bb.3(0x80000000)264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl266 ; CHECK-NEXT: early-clobber %9:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype267 ; CHECK-NEXT: PseudoBR %bb.3268 ; CHECK-NEXT: {{ $}}269 ; CHECK-NEXT: bb.2.if.else:270 ; CHECK-NEXT: successors: %bb.3(0x80000000)271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl273 ; CHECK-NEXT: early-clobber %9:vr = PseudoVSEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: bb.3.if.end:276 ; CHECK-NEXT: PseudoVSE64_V_M1 %9, [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype277 ; CHECK-NEXT: PseudoRET278 bb.0.entry:279 successors: %bb.2(0x30000000), %bb.1(0x50000000)280 liveins: $x10, $x11, $x12, $x13281 282 %7:gprnox0 = COPY $x13283 %6:gpr = COPY $x12284 %5:gpr = COPY $x11285 %4:gpr = COPY $x10286 %0:vr = PseudoVLE32_V_MF2 undef $noreg, %5, %7, 5, 0287 %8:gpr = COPY $x0288 BEQ %4, %8, %bb.2289 PseudoBR %bb.1290 291 bb.1.if.then:292 early-clobber %1:vr = PseudoVZEXT_VF2_M1 undef $noreg, %0, %7, 6, 0293 PseudoBR %bb.3294 295 bb.2.if.else:296 early-clobber %2:vr = PseudoVSEXT_VF2_M1 undef $noreg, %0, %7, 6, 0297 298 bb.3.if.end:299 %3:vr = PHI %1, %bb.1, %2, %bb.2300 PseudoVSE64_V_M1 %3, %6, %7, 6301 PseudoRET302 303...304---305name: vmv_x_s306alignment: 4307tracksRegLiveness: true308registers:309 - { id: 0, class: vr }310 - { id: 1, class: vr }311 - { id: 2, class: vr }312 - { id: 3, class: gpr }313 - { id: 4, class: vr }314 - { id: 5, class: vr }315 - { id: 6, class: gprnox0 }316 - { id: 7, class: gpr }317 - { id: 8, class: gpr }318liveins:319 - { reg: '$x10', virtual-reg: '%3' }320 - { reg: '$v8', virtual-reg: '%4' }321 - { reg: '$v9', virtual-reg: '%5' }322 - { reg: '$x11', virtual-reg: '%6' }323frameInfo:324 maxAlignment: 1325machineFunctionInfo: {}326body: |327 ; CHECK-LABEL: name: vmv_x_s328 ; CHECK: bb.0.entry:329 ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)330 ; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11331 ; CHECK-NEXT: {{ $}}332 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11333 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9334 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8335 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10336 ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2337 ; CHECK-NEXT: PseudoBR %bb.1338 ; CHECK-NEXT: {{ $}}339 ; CHECK-NEXT: bb.1.if.then:340 ; CHECK-NEXT: successors: %bb.3(0x80000000)341 ; CHECK-NEXT: {{ $}}342 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype343 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype344 ; CHECK-NEXT: PseudoBR %bb.3345 ; CHECK-NEXT: {{ $}}346 ; CHECK-NEXT: bb.2.if.else:347 ; CHECK-NEXT: successors: %bb.3(0x80000000)348 ; CHECK-NEXT: {{ $}}349 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype350 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype351 ; CHECK-NEXT: {{ $}}352 ; CHECK-NEXT: bb.3.if.end:353 ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVADD_VV_M1_]], 6 /* e64 */, implicit $vtype354 ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]355 ; CHECK-NEXT: PseudoRET implicit $x10356 bb.0.entry:357 successors: %bb.2(0x30000000), %bb.1(0x50000000)358 liveins: $x10, $v8, $v9, $x11359 360 %6:gprnox0 = COPY $x11361 %5:vr = COPY $v9362 %4:vr = COPY $v8363 %3:gpr = COPY $x10364 %7:gpr = COPY $x0365 BEQ %3, %7, %bb.2366 PseudoBR %bb.1367 368 bb.1.if.then:369 %0:vr = PseudoVADD_VV_M1 undef $noreg, %4, %5, %6, 6, 0370 PseudoBR %bb.3371 372 bb.2.if.else:373 %1:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %5, %6, 6, 0374 375 bb.3.if.end:376 %2:vr = PHI %0, %bb.1, %1, %bb.2377 %8:gpr = PseudoVMV_X_S %2, 6378 $x10 = COPY %8379 PseudoRET implicit $x10380 381...382---383name: vsetvli_add_or_sub384alignment: 4385tracksRegLiveness: true386registers:387 - { id: 0, class: gprnox0 }388 - { id: 1, class: vr }389 - { id: 2, class: vr }390 - { id: 3, class: vr }391 - { id: 4, class: gpr }392 - { id: 5, class: vr }393 - { id: 6, class: vr }394 - { id: 7, class: gprnox0 }395 - { id: 8, class: gpr }396liveins:397 - { reg: '$x10', virtual-reg: '%4' }398 - { reg: '$v8', virtual-reg: '%5' }399 - { reg: '$v9', virtual-reg: '%6' }400 - { reg: '$x11', virtual-reg: '%7' }401frameInfo:402 maxAlignment: 1403machineFunctionInfo: {}404body: |405 ; CHECK-LABEL: name: vsetvli_add_or_sub406 ; CHECK: bb.0.entry:407 ; CHECK-NEXT: successors: %bb.2(0x30000000), %bb.1(0x50000000)408 ; CHECK-NEXT: liveins: $x10, $v8, $v9, $x11409 ; CHECK-NEXT: {{ $}}410 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11411 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9412 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8413 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10414 ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype415 ; CHECK-NEXT: BEQ [[COPY3]], $x0, %bb.2416 ; CHECK-NEXT: PseudoBR %bb.1417 ; CHECK-NEXT: {{ $}}418 ; CHECK-NEXT: bb.1.if.then:419 ; CHECK-NEXT: successors: %bb.3(0x80000000)420 ; CHECK-NEXT: {{ $}}421 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype422 ; CHECK-NEXT: PseudoBR %bb.3423 ; CHECK-NEXT: {{ $}}424 ; CHECK-NEXT: bb.2.if.else:425 ; CHECK-NEXT: successors: %bb.3(0x80000000)426 ; CHECK-NEXT: {{ $}}427 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype428 ; CHECK-NEXT: {{ $}}429 ; CHECK-NEXT: bb.3.if.end:430 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]431 ; CHECK-NEXT: PseudoRET implicit $v8432 bb.0.entry:433 successors: %bb.2(0x30000000), %bb.1(0x50000000)434 liveins: $x10, $v8, $v9, $x11435 436 %7:gprnox0 = COPY $x11437 %6:vr = COPY $v9438 %5:vr = COPY $v8439 %4:gpr = COPY $x10440 %0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype441 %8:gpr = COPY $x0442 BEQ %4, %8, %bb.2443 PseudoBR %bb.1444 445 bb.1.if.then:446 %1:vr = PseudoVADD_VV_M1 undef $noreg, %5, %6, %0, 6, 0447 PseudoBR %bb.3448 449 bb.2.if.else:450 %2:vr = PseudoVSUB_VV_M1 undef $noreg, %5, %6, %0, 6, 0451 452 bb.3.if.end:453 %3:vr = PHI %1, %bb.1, %2, %bb.2454 $v8 = COPY %3455 PseudoRET implicit $v8456 457...458---459name: vsetvli_vcpop460tracksRegLiveness: true461registers:462 - { id: 0, class: gpr, preferred-register: '' }463 - { id: 1, class: gpr, preferred-register: '' }464 - { id: 2, class: gpr, preferred-register: '' }465 - { id: 3, class: vr, preferred-register: '' }466 - { id: 4, class: vrnov0, preferred-register: '' }467 - { id: 5, class: vmv0, preferred-register: '' }468 - { id: 6, class: vrnov0, preferred-register: '' }469 - { id: 7, class: gpr, preferred-register: '' }470 - { id: 8, class: gpr, preferred-register: '' }471 - { id: 9, class: gpr, preferred-register: '' }472 - { id: 10, class: gpr, preferred-register: '' }473 - { id: 11, class: vr, preferred-register: '' }474body: |475 ; CHECK-LABEL: name: vsetvli_vcpop476 ; CHECK: bb.0:477 ; CHECK-NEXT: successors: %bb.1(0x80000000)478 ; CHECK-NEXT: liveins: $x10, $x11479 ; CHECK-NEXT: {{ $}}480 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11481 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10482 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 223 /* e64, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype483 ; CHECK-NEXT: [[PseudoVID_V_MF2_:%[0-9]+]]:vr = PseudoVID_V_MF2 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype484 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype485 ; CHECK-NEXT: [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype486 ; CHECK-NEXT: {{ $}}487 ; CHECK-NEXT: bb.1:488 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)489 ; CHECK-NEXT: {{ $}}490 ; CHECK-NEXT: [[PseudoVMSEQ_VI_MF2_:%[0-9]+]]:vmv0 = PseudoVMSEQ_VI_MF2 [[PseudoVID_V_MF2_]], 0, -1, 5 /* e32 */, implicit $vl, implicit $vtype491 ; CHECK-NEXT: $v0 = COPY [[PseudoVMSEQ_VI_MF2_]]492 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 23 /* e32, mf2, tu, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl493 ; CHECK-NEXT: [[PseudoVLE32_V_MF2_MASK:%[0-9]+]]:vrnov0 = PseudoVLE32_V_MF2_MASK [[PseudoVMV_V_I_MF2_]], [[COPY]], $v0, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype494 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl495 ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSEQ_VI_MF2_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype496 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = IMPLICIT_DEF497 ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3498 ; CHECK-NEXT: PseudoBR %bb.2499 ; CHECK-NEXT: {{ $}}500 ; CHECK-NEXT: bb.2:501 ; CHECK-NEXT: successors: %bb.3(0x80000000)502 ; CHECK-NEXT: {{ $}}503 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr = LWU [[COPY1]], 0504 ; CHECK-NEXT: {{ $}}505 ; CHECK-NEXT: bb.3:506 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl507 ; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 undef $noreg, [[PseudoVLE32_V_MF2_MASK]], [[DEF]], -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype508 ; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]]509 ; CHECK-NEXT: PseudoRET implicit $v0510 bb.0:511 successors: %bb.1(0x80000000)512 liveins: $x10, $x11513 514 %0:gpr = COPY $x11515 %1:gpr = COPY $x10516 %2:gpr = IMPLICIT_DEF517 %3:vr = PseudoVID_V_MF2 undef $noreg, -1, 6, 0518 %4:vrnov0 = PseudoVMV_V_I_MF2 undef $noreg, 0, -1, 5, 0519 520 bb.1:521 successors: %bb.2(0x40000000), %bb.3(0x40000000)522 523 %5:vmv0 = PseudoVMSEQ_VI_MF2 killed %3, 0, -1, 5524 $v0 = COPY %5525 %6:vrnov0 = PseudoVLE32_V_MF2_MASK %4, killed %0, $v0, -1, 5, 0526 %7:gpr = PseudoVCPOP_M_B64 %5, -1, 0527 %8:gpr = COPY $x0528 BEQ killed %7, %8, %bb.3529 PseudoBR %bb.2530 531 bb.2:532 successors: %bb.3(0x80000000)533 534 %9:gpr = LWU %1, 0535 536 bb.3:537 %10:gpr = PHI %2, %bb.1, %9, %bb.2538 %11:vr = nsw PseudoVADD_VX_MF2 undef $noreg, %6, %10, -1, 5, 0539 $v0 = COPY %11540 PseudoRET implicit $v0541...542---543name: vsetvli_loop_store544tracksRegLiveness: true545registers:546 - { id: 0, class: gpr, preferred-register: '' }547 - { id: 1, class: gpr, preferred-register: '' }548 - { id: 2, class: gpr, preferred-register: '' }549 - { id: 3, class: gpr, preferred-register: '' }550 - { id: 4, class: vr, preferred-register: '' }551 - { id: 5, class: gpr, preferred-register: '' }552 - { id: 6, class: gpr, preferred-register: '' }553 - { id: 7, class: vr, preferred-register: '' }554 - { id: 8, class: gpr, preferred-register: '' }555 - { id: 9, class: gpr, preferred-register: '' }556 - { id: 10, class: gpr, preferred-register: '' }557body: |558 ; CHECK-LABEL: name: vsetvli_loop_store559 ; CHECK: bb.0:560 ; CHECK-NEXT: successors: %bb.1(0x80000000)561 ; CHECK-NEXT: liveins: $x10, $x11562 ; CHECK-NEXT: {{ $}}563 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10564 ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB565 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3566 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11567 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype568 ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype569 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0570 ; CHECK-NEXT: {{ $}}571 ; CHECK-NEXT: bb.1:572 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)573 ; CHECK-NEXT: {{ $}}574 ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype575 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]]576 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]577 ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype578 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1579 ; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1580 ; CHECK-NEXT: PseudoBR %bb.2581 ; CHECK-NEXT: {{ $}}582 ; CHECK-NEXT: bb.2:583 ; CHECK-NEXT: PseudoRET584 bb.0:585 liveins: $x10, $x11586 %0:gpr = COPY $x10587 %1:gpr = PseudoReadVLENB588 %2:gpr = SRLI %1:gpr, 3589 %3:gpr = COPY $x11590 %4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0591 %5:gpr = COPY $x0592 593 bb.1:594 successors: %bb.1, %bb.2595 596 %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.1597 %7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0598 %8:gpr = MUL %6:gpr, %2:gpr599 %9:gpr = ADD %0:gpr, %8:gpr600 PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5601 %10:gpr = ADDI %6:gpr, 1602 BLTU %10:gpr, %3:gpr, %bb.1603 PseudoBR %bb.2604 605 bb.2:606 607 PseudoRET608...609---610name: vsetvli_loop_store2611tracksRegLiveness: true612registers:613 - { id: 0, class: gpr, preferred-register: '' }614 - { id: 1, class: gpr, preferred-register: '' }615 - { id: 2, class: gpr, preferred-register: '' }616 - { id: 3, class: gpr, preferred-register: '' }617 - { id: 4, class: vr, preferred-register: '' }618 - { id: 5, class: gpr, preferred-register: '' }619 - { id: 6, class: gpr, preferred-register: '' }620 - { id: 7, class: vr, preferred-register: '' }621 - { id: 8, class: gpr, preferred-register: '' }622 - { id: 9, class: gpr, preferred-register: '' }623 - { id: 10, class: gpr, preferred-register: '' }624body: |625 ; CHECK-LABEL: name: vsetvli_loop_store2626 ; CHECK: bb.0:627 ; CHECK-NEXT: successors: %bb.1(0x80000000)628 ; CHECK-NEXT: liveins: $x10, $x11629 ; CHECK-NEXT: {{ $}}630 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10631 ; CHECK-NEXT: [[PseudoReadVLENB:%[0-9]+]]:gpr = PseudoReadVLENB632 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[PseudoReadVLENB]], 3633 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11634 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype635 ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype636 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0637 ; CHECK-NEXT: {{ $}}638 ; CHECK-NEXT: bb.1:639 ; CHECK-NEXT: successors: %bb.2(0x80000000)640 ; CHECK-NEXT: {{ $}}641 ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[COPY2]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype642 ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY2]], [[SRLI]]643 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]644 ; CHECK-NEXT: PseudoVSE32_V_MF2 [[PseudoVADD_VX_M1_]], [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype645 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = ADDI [[COPY2]], 1646 ; CHECK-NEXT: {{ $}}647 ; CHECK-NEXT: bb.2:648 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)649 ; CHECK-NEXT: {{ $}}650 ; CHECK-NEXT: BLTU [[COPY2]], [[COPY1]], %bb.1651 ; CHECK-NEXT: PseudoBR %bb.3652 ; CHECK-NEXT: {{ $}}653 ; CHECK-NEXT: bb.3:654 ; CHECK-NEXT: PseudoRET655 bb.0:656 liveins: $x10, $x11657 %0:gpr = COPY $x10658 %1:gpr = PseudoReadVLENB659 %2:gpr = SRLI %1:gpr, 3660 %3:gpr = COPY $x11661 %4:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 3662 %5:gpr = COPY $x0663 664 bb.1:665 successors: %bb.3666 667 %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.3668 %7:vr = PseudoVADD_VX_M1 undef $noreg, %4:vr, %6:gpr, -1, 6, 0669 %8:gpr = MUL %6:gpr, %2:gpr670 %9:gpr = ADD %0:gpr, %8:gpr671 PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5672 %10:gpr = ADDI %6:gpr, 1673 674 bb.3:675 successors: %bb.1, %bb.2676 BLTU %10:gpr, %3:gpr, %bb.1677 PseudoBR %bb.2678 679 bb.2:680 681 PseudoRET682...683---684name: redusum_loop685alignment: 4686tracksRegLiveness: true687registers:688 - { id: 0, class: gpr }689 - { id: 1, class: gpr }690 - { id: 2, class: vr }691 - { id: 3, class: vr }692 - { id: 4, class: gpr }693 - { id: 5, class: gpr }694 - { id: 6, class: gpr }695 - { id: 7, class: gpr }696 - { id: 8, class: gpr }697 - { id: 9, class: gpr }698 - { id: 10, class: vr }699 - { id: 11, class: vr }700 - { id: 12, class: vr }701 - { id: 13, class: gpr }702 - { id: 14, class: vr }703 - { id: 15, class: vr }704 - { id: 16, class: vr }705 - { id: 17, class: vr }706 - { id: 18, class: gpr }707 - { id: 19, class: gpr }708 - { id: 20, class: vr }709 - { id: 21, class: vr }710 - { id: 22, class: vr }711 - { id: 23, class: vr }712 - { id: 24, class: vr }713liveins:714 - { reg: '$x10', virtual-reg: '%6' }715 - { reg: '$x12', virtual-reg: '%8' }716frameInfo:717 maxAlignment: 1718machineFunctionInfo: {}719body: |720 ; CHECK-LABEL: name: redusum_loop721 ; CHECK: bb.0.entry:722 ; CHECK-NEXT: successors: %bb.1(0x80000000)723 ; CHECK-NEXT: liveins: $x10, $x12724 ; CHECK-NEXT: {{ $}}725 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12726 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10727 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype728 ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype729 ; CHECK-NEXT: [[LUI:%[0-9]+]]:gpr = LUI 1730 ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[LUI]], -2048731 ; CHECK-NEXT: {{ $}}732 ; CHECK-NEXT: bb.1.vector.body:733 ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)734 ; CHECK-NEXT: {{ $}}735 ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 undef $noreg, [[COPY1]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)736 ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE32_V_M1_]], [[PseudoVMV_V_I_M1_]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype737 ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = nsw ADDI [[ADDIW]], -4738 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = ADDI [[COPY1]], 16739 ; CHECK-NEXT: BNE [[ADDIW]], $x0, %bb.1740 ; CHECK-NEXT: PseudoBR %bb.2741 ; CHECK-NEXT: {{ $}}742 ; CHECK-NEXT: bb.2.middle.block:743 ; CHECK-NEXT: [[PseudoVMV_S_X:%[0-9]+]]:vr = PseudoVMV_S_X undef $noreg, $x0, 1, 5 /* e32 */, implicit $vl, implicit $vtype744 ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVMV_V_I_M1_]], [[PseudoVMV_S_X]], 4, 5 /* e32 */, 1 /* ta, mu */, implicit $vl, implicit $vtype745 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype746 ; CHECK-NEXT: PseudoVSE32_V_M1 [[PseudoVREDSUM_VS_M1_E8_]], [[COPY]], 1, 5 /* e32 */, implicit $vl, implicit $vtype :: (store (s32) into %ir.res)747 ; CHECK-NEXT: PseudoRET748 bb.0.entry:749 liveins: $x10, $x12750 751 %8:gpr = COPY $x12752 %6:gpr = COPY $x10753 %11:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 4, 5, 0754 %12:vr = COPY %11755 %10:vr = COPY %12756 %13:gpr = LUI 1757 %9:gpr = ADDIW killed %13, -2048758 759 bb.1.vector.body:760 successors: %bb.2(0x04000000), %bb.1(0x7c000000)761 762 %0:gpr = PHI %6, %bb.0, %5, %bb.1763 %1:gpr = PHI %9, %bb.0, %4, %bb.1764 %2:vr = PHI %10, %bb.0, %16, %bb.1765 %14:vr = PseudoVLE32_V_M1 undef $noreg, %0, 4, 5, 0 :: (load (s128) from %ir.lsr.iv12, align 4)766 %16:vr = PseudoVADD_VV_M1 undef $noreg, killed %14, %2, 4, 5, 0767 %4:gpr = nsw ADDI %1, -4768 %5:gpr = ADDI %0, 16769 %18:gpr = COPY $x0770 BNE %4, %18, %bb.1771 PseudoBR %bb.2772 773 bb.2.middle.block:774 %19:gpr = COPY $x0775 %20:vr = PseudoVMV_S_X undef $noreg, %19, 1, 5776 %23:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, %16, killed %20, 4, 5, 1777 PseudoVSE32_V_M1 killed %23, %8, 1, 5 :: (store (s32) into %ir.res)778 PseudoRET779 780...781---782name: vsetvli_vluxei64_regression783tracksRegLiveness: true784body: |785 ; CHECK-LABEL: name: vsetvli_vluxei64_regression786 ; CHECK: bb.0:787 ; CHECK-NEXT: successors: %bb.1(0x80000000)788 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3789 ; CHECK-NEXT: {{ $}}790 ; CHECK-NEXT: %a:gpr = COPY $x10791 ; CHECK-NEXT: %b:gpr = COPY $x11792 ; CHECK-NEXT: %inaddr:gpr = COPY $x12793 ; CHECK-NEXT: %idxs:vr = COPY $v0794 ; CHECK-NEXT: %t1:vr = COPY $v1795 ; CHECK-NEXT: %t3:vr = COPY $v2796 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrnov0 = COPY $v3797 ; CHECK-NEXT: %t5:vrnov0 = COPY $v1798 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype799 ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype800 ; CHECK-NEXT: PseudoBR %bb.1801 ; CHECK-NEXT: {{ $}}802 ; CHECK-NEXT: bb.1:803 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)804 ; CHECK-NEXT: {{ $}}805 ; CHECK-NEXT: %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype806 ; CHECK-NEXT: BEQ %a, $x0, %bb.3807 ; CHECK-NEXT: PseudoBR %bb.2808 ; CHECK-NEXT: {{ $}}809 ; CHECK-NEXT: bb.2:810 ; CHECK-NEXT: successors: %bb.3(0x80000000)811 ; CHECK-NEXT: {{ $}}812 ; CHECK-NEXT: $v0 = COPY %mask813 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl814 ; CHECK-NEXT: early-clobber [[COPY]]:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, %inaddr, %idxs, $v0, -1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype815 ; CHECK-NEXT: PseudoBR %bb.3816 ; CHECK-NEXT: {{ $}}817 ; CHECK-NEXT: bb.3:818 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_1:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype819 ; CHECK-NEXT: $v0 = COPY %mask820 ; CHECK-NEXT: PseudoVSOXEI64_V_M1_MF8_MASK [[COPY]], %b, %idxs, $v0, -1, 3 /* e8 */, implicit $vl, implicit $vtype821 ; CHECK-NEXT: PseudoRET822 bb.0:823 successors: %bb.1824 liveins: $x10, $x11, $x12, $v0, $v1, $v2, $v3825 826 %a:gpr = COPY $x10827 %b:gpr = COPY $x11828 %inaddr:gpr = COPY $x12829 %idxs:vr = COPY $v0830 %t1:vr = COPY $v1831 %t3:vr = COPY $v2832 %t4:vr = COPY $v3833 %t5:vrnov0 = COPY $v1834 %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6835 PseudoBR %bb.1836 837 bb.1:838 successors: %bb.3, %bb.2839 840 %mask:vr = PseudoVMANDN_MM_B64 %t6, %t3, -1, 0841 %t2:gpr = COPY $x0842 BEQ %a, %t2, %bb.3843 PseudoBR %bb.2844 845 bb.2:846 successors: %bb.3847 848 $v0 = COPY %mask849 early-clobber %t0:vrnov0 = PseudoVLUXEI64_V_M1_MF8_MASK %t5, killed %inaddr, %idxs, $v0, -1, 3, 1850 %ldval:vr = COPY %t0851 PseudoBR %bb.3852 853 bb.3:854 %stval:vr = PHI %t4, %bb.1, %ldval, %bb.2855 $v0 = COPY %mask856 PseudoVSOXEI64_V_M1_MF8_MASK killed %stval, killed %b, %idxs, $v0, -1, 3857 PseudoRET858 859...860---861name: if_in_loop862tracksRegLiveness: true863body: |864 ; CHECK-LABEL: name: if_in_loop865 ; CHECK: bb.0:866 ; CHECK-NEXT: successors: %bb.1(0x80000000)867 ; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15868 ; CHECK-NEXT: {{ $}}869 ; CHECK-NEXT: %dst:gpr = COPY $x10870 ; CHECK-NEXT: %src:gpr = COPY $x11871 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x12872 ; CHECK-NEXT: %tc:gpr = COPY $x13873 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14874 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15875 ; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB876 ; CHECK-NEXT: %inc:gpr = SRLI %vlenb, 3877 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype878 ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 undef $noreg, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype879 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0880 ; CHECK-NEXT: PseudoBR %bb.1881 ; CHECK-NEXT: {{ $}}882 ; CHECK-NEXT: bb.1:883 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)884 ; CHECK-NEXT: {{ $}}885 ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[COPY3]]886 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl887 ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 undef $noreg, [[PseudoVID_V_M1_]], [[ADD]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype888 ; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype889 ; CHECK-NEXT: [[PseudoVCPOP_M_B64_:%[0-9]+]]:gpr = PseudoVCPOP_M_B64 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype890 ; CHECK-NEXT: BEQ [[PseudoVCPOP_M_B64_]], $x0, %bb.3891 ; CHECK-NEXT: PseudoBR %bb.2892 ; CHECK-NEXT: {{ $}}893 ; CHECK-NEXT: bb.2:894 ; CHECK-NEXT: successors: %bb.3(0x80000000)895 ; CHECK-NEXT: {{ $}}896 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[COPY3]]897 ; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, [[ADD1]], -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype898 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl899 ; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype900 ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[COPY3]]901 ; CHECK-NEXT: PseudoVSE8_V_MF8 [[PseudoVADD_VI_MF8_]], [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype902 ; CHECK-NEXT: {{ $}}903 ; CHECK-NEXT: bb.3:904 ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)905 ; CHECK-NEXT: {{ $}}906 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = ADD [[COPY3]], %inc907 ; CHECK-NEXT: BLTU [[COPY3]], %tc, %bb.1908 ; CHECK-NEXT: PseudoBR %bb.4909 ; CHECK-NEXT: {{ $}}910 ; CHECK-NEXT: bb.4:911 ; CHECK-NEXT: PseudoRET912 bb.0:913 successors: %bb.1(0x80000000)914 liveins: $x10, $x11, $x12, $x13, $x14, $x15915 916 %dst:gpr = COPY $x10917 %src:gpr = COPY $x11918 %48:gpr = COPY $x12919 %tc:gpr = COPY $x13920 %11:gpr = COPY $x14921 %12:gpr = COPY $x15922 %vlenb:gpr = PseudoReadVLENB923 %inc:gpr = SRLI killed %vlenb, 3924 %10:vr = PseudoVID_V_M1 undef $noreg, -1, 6, 0925 %59:gpr = COPY $x0926 PseudoBR %bb.1927 928 bb.1:929 successors: %bb.2(0x40000000), %bb.3(0x40000000)930 931 %26:gpr = PHI %59, %bb.0, %28, %bb.3932 %61:gpr = ADD %12, %26933 %27:vr = PseudoVADD_VX_M1 undef $noreg, %10, killed %61, -1, 6, 0934 %62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6935 %63:gpr = PseudoVCPOP_M_B64 %62, -1, 0936 %64:gpr = COPY $x0937 BEQ killed %63, %64, %bb.3938 PseudoBR %bb.2939 940 bb.2:941 successors: %bb.3(0x80000000)942 943 %66:gpr = ADD %src, %26944 %67:vrnov0 = PseudoVLE8_V_MF8 undef $noreg, killed %66, -1, 3, 0945 %76:vrnov0 = PseudoVADD_VI_MF8 undef $noreg, %67, 4, -1, 3, 0946 %77:gpr = ADD %dst, %26947 PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3948 949 bb.3:950 successors: %bb.1(0x7c000000), %bb.4(0x04000000)951 952 %28:gpr = ADD %26, %inc953 BLTU %28, %tc, %bb.1954 PseudoBR %bb.4955 956 bb.4:957 PseudoRET958 959...960---961name: pre_undemanded_vl962body: |963 ; CHECK-LABEL: name: pre_undemanded_vl964 ; CHECK: bb.0:965 ; CHECK-NEXT: successors: %bb.1(0x80000000)966 ; CHECK-NEXT: {{ $}}967 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype968 ; CHECK-NEXT: PseudoBR %bb.1969 ; CHECK-NEXT: {{ $}}970 ; CHECK-NEXT: bb.1:971 ; CHECK-NEXT: successors: %bb.1(0x80000000)972 ; CHECK-NEXT: {{ $}}973 ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S undef $noreg, 6 /* e64 */, implicit $vtype974 ; CHECK-NEXT: PseudoBR %bb.1975 bb.0:976 PseudoBR %bb.1977 bb.1:978 %x:gpr = PseudoVMV_X_S undef $noreg, 6979 PseudoBR %bb.1980...981---982name: clobberred_forwarded_avl983tracksRegLiveness: true984body: |985 ; CHECK-LABEL: name: clobberred_forwarded_avl986 ; CHECK: bb.0:987 ; CHECK-NEXT: successors: %bb.1(0x80000000)988 ; CHECK-NEXT: liveins: $x10, $v8m2989 ; CHECK-NEXT: {{ $}}990 ; CHECK-NEXT: %avl:gprnox0 = COPY $x10991 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl992 ; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI %avl, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype993 ; CHECK-NEXT: {{ $}}994 ; CHECK-NEXT: bb.1:995 ; CHECK-NEXT: successors: %bb.2(0x80000000)996 ; CHECK-NEXT: liveins: $v8m2997 ; CHECK-NEXT: {{ $}}998 ; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, 1999 ; CHECK-NEXT: {{ $}}1000 ; CHECK-NEXT: bb.2:1001 ; CHECK-NEXT: liveins: $v8m21002 ; CHECK-NEXT: {{ $}}1003 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype1004 ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype1005 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype1006 ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, renamable $v8m2, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype1007 ; CHECK-NEXT: PseudoRET implicit $v8m21008 bb.0:1009 liveins: $x10, $v8m21010 %avl:gprnox0 = COPY $x101011 %outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype1012 1013 bb.1:1014 liveins: $v8m21015 %avl:gprnox0 = ADDI %avl:gprnox0, 11016 1017 bb.2:1018 liveins: $v8m21019 renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, renamable $v8m2, renamable $v8m2, -1, 5, 01020 renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed renamable $v8m2, %outvl:gprnox0, 5, 01021 PseudoRET implicit $v8m21022...1023---1024name: clobberred_forwarded_phi_avl1025tracksRegLiveness: true1026body: |1027 ; CHECK-LABEL: name: clobberred_forwarded_phi_avl1028 ; CHECK: bb.0:1029 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)1030 ; CHECK-NEXT: liveins: $x10, $x11, $v8m21031 ; CHECK-NEXT: {{ $}}1032 ; CHECK-NEXT: %v:vrm2 = COPY $v8m21033 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 11034 ; CHECK-NEXT: %x:gpr = COPY $x101035 ; CHECK-NEXT: %y:gpr = COPY $x111036 ; CHECK-NEXT: BEQ %x, %y, %bb.21037 ; CHECK-NEXT: {{ $}}1038 ; CHECK-NEXT: bb.1:1039 ; CHECK-NEXT: successors: %bb.2(0x80000000)1040 ; CHECK-NEXT: {{ $}}1041 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gprnox0 = ADDI $x0, 21042 ; CHECK-NEXT: {{ $}}1043 ; CHECK-NEXT: bb.2:1044 ; CHECK-NEXT: successors: %bb.3(0x80000000)1045 ; CHECK-NEXT: {{ $}}1046 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY [[ADDI]]1047 ; CHECK-NEXT: dead %outvl:gprnox0 = PseudoVSETVLI [[ADDI]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype1048 ; CHECK-NEXT: {{ $}}1049 ; CHECK-NEXT: bb.3:1050 ; CHECK-NEXT: successors: %bb.4(0x80000000)1051 ; CHECK-NEXT: {{ $}}1052 ; CHECK-NEXT: dead [[ADDI:%[0-9]+]]:gprnox0 = ADDI [[ADDI]], 11053 ; CHECK-NEXT: {{ $}}1054 ; CHECK-NEXT: bb.4:1055 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype1056 ; CHECK-NEXT: renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype1057 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype1058 ; CHECK-NEXT: renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, %v, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype1059 ; CHECK-NEXT: PseudoRET implicit $v8m21060 bb.0:1061 liveins: $x10, $x11, $v8m21062 %v:vrm2 = COPY $v8m21063 %a:gpr = ADDI $x0, 11064 %x:gpr = COPY $x101065 %y:gpr = COPY $x111066 BEQ %x, %y, %bb.21067 1068 bb.1:1069 %b:gpr = ADDI $x0, 21070 1071 bb.2:1072 %avl:gprnox0 = PHI %a, %bb.0, %b, %bb.11073 %outvl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype1074 1075 bb.3:1076 %avl:gprnox0 = ADDI %avl:gprnox0, 11077 1078 bb.4:1079 renamable $v10m2 = PseudoVADD_VV_M2 undef renamable $v10m2, %v, %v, -1, 5, 01080 renamable $v8m2 = PseudoVADD_VV_M2 undef renamable $v8m2, killed renamable $v10m2, killed %v, %outvl:gprnox0, 5, 01081 PseudoRET implicit $v8m21082...1083---1084name: avl_is_last_instr1085tracksRegLiveness: true1086body: |1087 ; CHECK-LABEL: name: avl_is_last_instr1088 ; CHECK: bb.0:1089 ; CHECK-NEXT: successors: %bb.1(0x80000000)1090 ; CHECK-NEXT: liveins: $x101091 ; CHECK-NEXT: {{ $}}1092 ; CHECK-NEXT: %avl:gprnox0 = COPY $x101093 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY %avl1094 ; CHECK-NEXT: {{ $}}1095 ; CHECK-NEXT: bb.1:1096 ; CHECK-NEXT: dead %avl:gprnox0 = ADDI %avl, -11097 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype1098 ; CHECK-NEXT: $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1, 3 /* e8 */, implicit $vl, implicit $vtype1099 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype1100 ; CHECK-NEXT: $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, $noreg, 3 /* e8 */, 3 /* ta, ma */, implicit $vl, implicit $vtype1101 bb.0:1102 liveins: $x101103 %avl:gprnox0 = COPY $x101104 1105 bb.1:1106 %vl:gprnox0 = PseudoVSETVLI %avl:gprnox0, 192, implicit-def dead $vl, implicit-def dead $vtype1107 %avl:gprnox0 = ADDI %avl:gprnox0, -11108 $v8 = PseudoVMV_S_X undef renamable $v8, $x0, 1, 31109 $v8 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, %vl:gprnox0, 3, 31110