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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc %s -o - -mtriple=riscv64 -mattr=v -run-pass=liveintervals,riscv-insert-vsetvli \3# RUN: -verify-machineinstrs | FileCheck %s4 5--- |6 source_filename = "vsetvli-insert.ll"7 target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"8 target triple = "riscv64"9 10 define <vscale x 1 x i64> @add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) #0 {11 entry:12 %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2)13 ret <vscale x 1 x i64> %a14 }15 16 define <vscale x 1 x i64> @load_add(ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {17 entry:18 %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)19 %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)20 ret <vscale x 1 x i64> %b21 }22 23 define <vscale x 1 x i64> @load_zext(ptr %0, i64 %1) #0 {24 entry:25 %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.i64(<vscale x 1 x i32> undef, ptr %0, i64 %1)26 %b = call <vscale x 1 x i64> @llvm.riscv.vzext.nxv1i64.nxv1i32.i64(<vscale x 1 x i64> undef, <vscale x 1 x i32> %a, i64 %1)27 ret <vscale x 1 x i64> %b28 }29 30 define i64 @vmv_x_s(<vscale x 1 x i64> %0) #0 {31 entry:32 %a = call i64 @llvm.riscv.vmv.x.s.nxv1i64(<vscale x 1 x i64> %0)33 ret i64 %a34 }35 36 define void @add_v2i64(ptr %x, ptr %y) #0 {37 %a = load <2 x i64>, ptr %x, align 1638 %b = load <2 x i64>, ptr %y, align 1639 %c = add <2 x i64> %a, %b40 store <2 x i64> %c, ptr %x, align 1641 ret void42 }43 44 define i64 @vreduce_add_v2i64(ptr %x) #0 {45 %v = load <2 x i64>, ptr %x, align 1646 %red = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %v)47 ret i64 %red48 }49 50 define <vscale x 1 x i64> @vsetvli_add(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %avl) #0 {51 entry:52 %a = call i64 @llvm.riscv.vsetvli.i64(i64 %avl, i64 3, i64 0)53 %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %a)54 ret <vscale x 1 x i64> %b55 }56 57 define <vscale x 1 x i64> @load_add_inlineasm(ptr %0, <vscale x 1 x i64> %1, i64 %2) #0 {58 entry:59 %a = call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> undef, ptr %0, i64 %2)60 call void asm sideeffect "", ""()61 %b = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, <vscale x 1 x i64> %1, i64 %2)62 ret <vscale x 1 x i64> %b63 }64 65 define void @vmv_v_i_different_lmuls() {66 ret void67 }68 69 define void @pre_same_sewlmul_ratio() {70 ret void71 }72 73 define void @postpass_modify_vl() {74 ret void75 }76 77 define void @coalesce_dead_avl_addi() {78 ret void79 }80 81 define void @coalesce_dead_avl_nonvolatile_load() {82 ret void83 }84 85 define void @coalesce_dead_avl_volatile_load() {86 ret void87 }88 89 define void @coalesce_shrink_removed_vsetvlis_uses() {90 ret void91 }92 93 define void @coalesce_vl_avl_same_reg() {94 ret void95 }96 97 define void @coalesce_vl_clobber() {98 ret void99 }100 101 define void @vsetvli_vleff() {102 ret void103 }104 105 define void @non_li_addi() {106 ret void107 }108 109 attributes #0 = { "target-features"="+v" }110 111...112---113name: add114alignment: 4115tracksRegLiveness: true116registers:117 - { id: 0, class: vr }118 - { id: 1, class: vr }119 - { id: 2, class: gprnox0 }120 - { id: 3, class: vr }121liveins:122 - { reg: '$v8', virtual-reg: '%0' }123 - { reg: '$v9', virtual-reg: '%1' }124 - { reg: '$x10', virtual-reg: '%2' }125frameInfo:126 maxAlignment: 1127machineFunctionInfo: {}128body: |129 bb.0.entry:130 liveins: $v8, $v9, $x10131 132 ; CHECK-LABEL: name: add133 ; CHECK: liveins: $v8, $v9, $x10134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10136 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9137 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8138 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype139 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype140 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype141 ; CHECK-NEXT: PseudoRET implicit $v8142 %2:gprnox0 = COPY $x10143 %1:vr = COPY $v9144 %0:vr = COPY $v8145 %3:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, %2, 6, 0146 $v8 = COPY %3147 PseudoRET implicit $v8148 149...150---151name: load_add152alignment: 4153tracksRegLiveness: true154registers:155 - { id: 0, class: gpr }156 - { id: 1, class: vr }157 - { id: 2, class: gprnox0 }158 - { id: 3, class: vr }159 - { id: 4, class: vr }160liveins:161 - { reg: '$x10', virtual-reg: '%0' }162 - { reg: '$v8', virtual-reg: '%1' }163 - { reg: '$x11', virtual-reg: '%2' }164frameInfo:165 maxAlignment: 1166machineFunctionInfo: {}167body: |168 bb.0.entry:169 liveins: $x10, $v8, $x11170 171 ; CHECK-LABEL: name: load_add172 ; CHECK: liveins: $x10, $v8, $x11173 ; CHECK-NEXT: {{ $}}174 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11175 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8176 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10177 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype178 ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype179 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype180 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype181 ; CHECK-NEXT: PseudoRET implicit $v8182 %2:gprnox0 = COPY $x11183 %1:vr = COPY $v8184 %0:gpr = COPY $x10185 %3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0186 %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0187 $v8 = COPY %4188 PseudoRET implicit $v8189 190...191---192name: load_zext193alignment: 4194tracksRegLiveness: true195registers:196 - { id: 0, class: gpr }197 - { id: 1, class: gprnox0 }198 - { id: 2, class: vr }199 - { id: 3, class: vr }200liveins:201 - { reg: '$x10', virtual-reg: '%0' }202 - { reg: '$x11', virtual-reg: '%1' }203frameInfo:204 maxAlignment: 1205machineFunctionInfo: {}206body: |207 bb.0.entry:208 liveins: $x10, $x11209 210 ; CHECK-LABEL: name: load_zext211 ; CHECK: liveins: $x10, $x11212 ; CHECK-NEXT: {{ $}}213 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11214 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10215 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype216 ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 undef $noreg, [[COPY1]], $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype217 ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype218 ; CHECK-NEXT: $v8 = COPY %3, implicit $vtype219 ; CHECK-NEXT: PseudoRET implicit $v8220 %1:gprnox0 = COPY $x11221 %0:gpr = COPY $x10222 %2:vr = PseudoVLE32_V_MF2 undef $noreg, %0, %1, 5, 0223 early-clobber %3:vr = PseudoVZEXT_VF2_M1 undef $noreg, killed %2, %1, 6, 0224 $v8 = COPY %3225 PseudoRET implicit $v8226 227...228---229name: vmv_x_s230alignment: 4231tracksRegLiveness: true232registers:233 - { id: 0, class: vr }234 - { id: 1, class: gpr }235liveins:236 - { reg: '$v8', virtual-reg: '%0' }237frameInfo:238 maxAlignment: 1239machineFunctionInfo: {}240body: |241 bb.0.entry:242 liveins: $v8243 244 ; CHECK-LABEL: name: vmv_x_s245 ; CHECK: liveins: $v8246 ; CHECK-NEXT: {{ $}}247 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v8248 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype249 ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[COPY]], 6 /* e64 */, implicit $vtype250 ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]251 ; CHECK-NEXT: PseudoRET implicit $x10252 %0:vr = COPY $v8253 %1:gpr = PseudoVMV_X_S %0, 6254 $x10 = COPY %1255 PseudoRET implicit $x10256 257...258---259name: add_v2i64260alignment: 4261tracksRegLiveness: true262registers:263 - { id: 0, class: gpr }264 - { id: 1, class: gpr }265 - { id: 2, class: vr }266 - { id: 3, class: vr }267 - { id: 4, class: vr }268liveins:269 - { reg: '$x10', virtual-reg: '%0' }270 - { reg: '$x11', virtual-reg: '%1' }271frameInfo:272 maxAlignment: 1273machineFunctionInfo: {}274body: |275 bb.0 (%ir-block.0):276 liveins: $x10, $x11277 278 ; CHECK-LABEL: name: add_v2i64279 ; CHECK: liveins: $x10, $x11280 ; CHECK-NEXT: {{ $}}281 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11282 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10283 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype284 ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)285 ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y)286 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype287 ; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x)288 ; CHECK-NEXT: PseudoRET289 %1:gpr = COPY $x11290 %0:gpr = COPY $x10291 %2:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x)292 %3:vr = PseudoVLE64_V_M1 undef $noreg, %1, 2, 6, 0 :: (load (s128) from %ir.y)293 %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %2, killed %3, 2, 6, 0294 PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store (s128) into %ir.x)295 PseudoRET296 297...298---299name: vreduce_add_v2i64300alignment: 4301tracksRegLiveness: true302registers:303 - { id: 0, class: gpr }304 - { id: 1, class: vr }305 - { id: 2, class: vr }306 - { id: 3, class: vr }307 - { id: 4, class: vr }308 - { id: 5, class: gpr }309liveins:310 - { reg: '$x10', virtual-reg: '%0' }311frameInfo:312 maxAlignment: 1313machineFunctionInfo: {}314body: |315 bb.0 (%ir-block.0):316 liveins: $x10317 318 ; CHECK-LABEL: name: vreduce_add_v2i64319 ; CHECK: liveins: $x10320 ; CHECK-NEXT: {{ $}}321 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10322 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype323 ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)324 ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gprnox0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype325 ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype326 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype327 ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype328 ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype329 ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]]330 ; CHECK-NEXT: PseudoRET implicit $x10331 %0:gpr = COPY $x10332 %1:vr = PseudoVLE64_V_M1 undef $noreg, %0, 2, 6, 0 :: (load (s128) from %ir.x)333 %2:vr = PseudoVMV_V_I_M1 undef $noreg, 0, -1, 6, 0334 %3:vr = PseudoVREDSUM_VS_M1_E8 undef $noreg, killed %1, killed %2, 2, 6, 1335 %5:gpr = PseudoVMV_X_S killed %3, 6336 $x10 = COPY %5337 PseudoRET implicit $x10338 339...340---341name: vsetvli_add342alignment: 4343tracksRegLiveness: true344registers:345 - { id: 0, class: vr }346 - { id: 1, class: vr }347 - { id: 2, class: gprnox0 }348 - { id: 3, class: gprnox0 }349 - { id: 4, class: vr }350liveins:351 - { reg: '$v8', virtual-reg: '%0' }352 - { reg: '$v9', virtual-reg: '%1' }353 - { reg: '$x10', virtual-reg: '%2' }354frameInfo:355 maxAlignment: 1356machineFunctionInfo: {}357body: |358 bb.0.entry:359 liveins: $v8, $v9, $x10360 361 ; CHECK-LABEL: name: vsetvli_add362 ; CHECK: liveins: $v8, $v9, $x10363 ; CHECK-NEXT: {{ $}}364 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10365 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9366 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8367 ; CHECK-NEXT: dead [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype368 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype369 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype370 ; CHECK-NEXT: PseudoRET implicit $v8371 %2:gprnox0 = COPY $x10372 %1:vr = COPY $v9373 %0:vr = COPY $v8374 %3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype375 %4:vr = PseudoVADD_VV_M1 undef $noreg, %0, %1, killed %3, 6, 0376 $v8 = COPY %4377 PseudoRET implicit $v8378 379...380---381name: load_add_inlineasm382alignment: 4383tracksRegLiveness: true384registers:385 - { id: 0, class: gpr }386 - { id: 1, class: vr }387 - { id: 2, class: gprnox0 }388 - { id: 3, class: vr }389 - { id: 4, class: vr }390liveins:391 - { reg: '$x10', virtual-reg: '%0' }392 - { reg: '$v8', virtual-reg: '%1' }393 - { reg: '$x11', virtual-reg: '%2' }394frameInfo:395 maxAlignment: 1396machineFunctionInfo: {}397body: |398 bb.0.entry:399 liveins: $x10, $v8, $x11400 401 ; CHECK-LABEL: name: load_add_inlineasm402 ; CHECK: liveins: $x10, $v8, $x11403 ; CHECK-NEXT: {{ $}}404 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11405 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8406 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10407 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype408 ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 undef $noreg, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype409 ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, implicit-def $vl, implicit-def $vtype410 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype411 ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype412 ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]], implicit $vtype413 ; CHECK-NEXT: PseudoRET implicit $v8414 %2:gprnox0 = COPY $x11415 %1:vr = COPY $v8416 %0:gpr = COPY $x10417 %3:vr = PseudoVLE64_V_M1 undef $noreg, %0, %2, 6, 0418 INLINEASM &"", 1 /* sideeffect attdialect */419 %4:vr = PseudoVADD_VV_M1 undef $noreg, killed %3, %1, %2, 6, 0420 $v8 = COPY %4421 PseudoRET implicit $v8422 423...424---425name: vmv_v_i_different_lmuls426tracksRegLiveness: true427body: |428 bb.0:429 liveins: $x10, $v8, $x11430 431 ; CHECK-LABEL: name: vmv_v_i_different_lmuls432 ; CHECK: liveins: $x10, $v8, $x11433 ; CHECK-NEXT: {{ $}}434 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 217 /* e64, m2, ta, ma */, implicit-def $vl, implicit-def $vtype435 ; CHECK-NEXT: dead [[PseudoVID_V_M2_:%[0-9]+]]:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype436 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 198 /* e8, mf4, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl437 ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF4_:%[0-9]+]]:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype438 ; CHECK-NEXT: PseudoRET439 %0:vrm2 = PseudoVID_V_M2 undef $noreg, 4, 6, 3440 %4:vr = PseudoVMV_V_I_MF4 undef $noreg, 0, 4, 3, 0441 PseudoRET442...443---444# make sure we don't try to perform PRE when one of the blocks is sew/lmul ratio445# only446name: pre_same_sewlmul_ratio447tracksRegLiveness: true448body: |449 ; CHECK-LABEL: name: pre_same_sewlmul_ratio450 ; CHECK: bb.0:451 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)452 ; CHECK-NEXT: liveins: $x10453 ; CHECK-NEXT: {{ $}}454 ; CHECK-NEXT: %cond:gpr = COPY $x10455 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype456 ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype457 ; CHECK-NEXT: BEQ %cond, $x0, %bb.2458 ; CHECK-NEXT: {{ $}}459 ; CHECK-NEXT: bb.1:460 ; CHECK-NEXT: successors: %bb.2(0x80000000)461 ; CHECK-NEXT: {{ $}}462 ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0X0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl463 ; CHECK-NEXT: dead [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype464 ; CHECK-NEXT: {{ $}}465 ; CHECK-NEXT: bb.2:466 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)467 ; CHECK-NEXT: {{ $}}468 ; CHECK-NEXT: BEQ %cond, $x0, %bb.4469 ; CHECK-NEXT: {{ $}}470 ; CHECK-NEXT: bb.3:471 ; CHECK-NEXT: successors: %bb.4(0x80000000)472 ; CHECK-NEXT: {{ $}}473 ; CHECK-NEXT: PseudoCALL $noreg, csr_ilp32_lp64474 ; CHECK-NEXT: {{ $}}475 ; CHECK-NEXT: bb.4:476 ; CHECK-NEXT: $x0 = PseudoVSETIVLI 2, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype477 ; CHECK-NEXT: dead [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S undef $noreg, 5 /* e32 */, implicit $vtype478 ; CHECK-NEXT: dead [[PseudoVMV_V_I_MF2_1:%[0-9]+]]:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype479 ; CHECK-NEXT: PseudoRET480 bb.0:481 liveins: $x10482 %cond:gpr = COPY $x10483 %1:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0484 BEQ %cond, $x0, %bb.2485 bb.1:486 %2:vr = PseudoVMV_V_I_M1 undef $noreg, 1, 2, 6, 0487 bb.2: ; the exit info here should have sew/lmul ratio only488 BEQ %cond, $x0, %bb.4489 bb.3:490 PseudoCALL $noreg, csr_ilp32_lp64491 bb.4: ; this block will have PRE attempted on it492 %4:gpr = PseudoVMV_X_S undef $noreg, 5493 %5:vr = PseudoVMV_V_I_MF2 undef $noreg, 1, 2, 5, 0494 PseudoRET495...496---497name: postpass_modify_vl498tracksRegLiveness: true499body: |500 bb.0:501 liveins: $x1502 ; CHECK-LABEL: name: postpass_modify_vl503 ; CHECK: liveins: $x1504 ; CHECK-NEXT: {{ $}}505 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype506 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $vtype507 ; CHECK-NEXT: $vl = COPY $x1508 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype509 ; CHECK-NEXT: dead [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype510 ; CHECK-NEXT: PseudoRET511 dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype512 %1:gpr = COPY $vtype513 $vl = COPY $x1514 dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype515 %4:vr = PseudoVADD_VV_M1 undef $noreg, undef $noreg, undef $noreg, 3, 6, 0516 PseudoRET517...518---519name: coalesce_dead_avl_addi520tracksRegLiveness: true521body: |522 bb.0:523 ; CHECK-LABEL: name: coalesce_dead_avl_addi524 ; CHECK: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype525 ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype526 ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype527 ; CHECK-NEXT: PseudoRET528 %avl:gprnox0 = ADDI $x0, 42529 dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype530 %x:gpr = PseudoVMV_X_S $noreg, 6531 dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype532 $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0533 PseudoRET534...535---536name: coalesce_dead_avl_nonvolatile_load537tracksRegLiveness: true538body: |539 bb.0:540 liveins: $x1541 ; CHECK-LABEL: name: coalesce_dead_avl_nonvolatile_load542 ; CHECK: liveins: $x1543 ; CHECK-NEXT: {{ $}}544 ; CHECK-NEXT: %ptr:gpr = COPY $x1545 ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (dereferenceable load (s32))546 ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype547 ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype548 ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype549 ; CHECK-NEXT: PseudoRET550 %ptr:gpr = COPY $x1551 %avl:gprnox0 = LW killed %ptr, 0 :: (dereferenceable load (s32))552 dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype553 %x:gpr = PseudoVMV_X_S $noreg, 6554 dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype555 $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0556 PseudoRET557...558---559name: coalesce_dead_avl_volatile_load560tracksRegLiveness: true561body: |562 bb.0:563 liveins: $x1564 ; CHECK-LABEL: name: coalesce_dead_avl_volatile_load565 ; CHECK: liveins: $x1566 ; CHECK-NEXT: {{ $}}567 ; CHECK-NEXT: %ptr:gpr = COPY $x1568 ; CHECK-NEXT: dead %avl:gprnox0 = LW %ptr, 0 :: (volatile dereferenceable load (s32))569 ; CHECK-NEXT: $x0 = PseudoVSETIVLI 3, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype570 ; CHECK-NEXT: dead %x:gpr = PseudoVMV_X_S $noreg, 6 /* e64 */, implicit $vtype571 ; CHECK-NEXT: $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype572 ; CHECK-NEXT: PseudoRET573 %ptr:gpr = COPY $x1574 %avl:gprnox0 = LW killed %ptr, 0 :: (volatile dereferenceable load (s32))575 dead $x0 = PseudoVSETVLI killed %avl, 216, implicit-def $vl, implicit-def $vtype576 %x:gpr = PseudoVMV_X_S $noreg, 6577 dead $x0 = PseudoVSETIVLI 3, 216, implicit-def $vl, implicit-def $vtype578 $v0 = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 3, 6, 0579 PseudoRET580...581---582name: coalesce_shrink_removed_vsetvlis_uses583tracksRegLiveness: true584body: |585 bb.0:586 liveins: $x10, $v8587 ; CHECK-LABEL: name: coalesce_shrink_removed_vsetvlis_uses588 ; CHECK: liveins: $x10, $v8589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: %avl2:gprnox0 = ADDI $x0, 2591 ; CHECK-NEXT: dead $x0 = PseudoVSETVLI %avl2, 209 /* e32, m2, ta, ma */, implicit-def $vl, implicit-def $vtype592 ; CHECK-NEXT: %x:gpr = COPY $x10593 ; CHECK-NEXT: renamable $v8 = PseudoVMV_S_X undef renamable $v8, %x, 1, 5 /* e32 */, implicit $vl, implicit $vtype594 ; CHECK-NEXT: PseudoRET implicit $v8595 %avl1:gprnox0 = ADDI $x0, 1596 dead $x0 = PseudoVSETVLI %avl1:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype597 %avl2:gprnox0 = ADDI $x0, 2598 dead $x0 = PseudoVSETVLI %avl2:gprnox0, 209, implicit-def dead $vl, implicit-def dead $vtype599 %x:gpr = COPY $x10600 renamable $v8 = PseudoVMV_S_X undef renamable $v8, killed renamable %x, 1, 5601 PseudoRET implicit $v8602...603---604name: coalesce_vl_avl_same_reg605tracksRegLiveness: true606body: |607 bb.0:608 liveins: $x8, $v8609 ; CHECK-LABEL: name: coalesce_vl_avl_same_reg610 ; CHECK: liveins: $x8, $v8611 ; CHECK-NEXT: {{ $}}612 ; CHECK-NEXT: %x:gprnox0 = COPY $x8613 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype614 ; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype615 ; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype616 %x:gprnox0 = COPY $x8617 dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype618 %v:vr = COPY $v8, implicit $vtype619 %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype620...621---622# Because of the %y:gprnox0 = COPY %x, we can't extend the live range of %x from623# the second vsetvli to the first vsetvli when coalescing.624name: coalesce_vl_clobber625tracksRegLiveness: true626body: |627 bb.0:628 liveins: $x8, $v8629 ; CHECK-LABEL: name: coalesce_vl_clobber630 ; CHECK: liveins: $x8, $v8631 ; CHECK-NEXT: {{ $}}632 ; CHECK-NEXT: %x:gprnox0 = COPY $x8633 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype634 ; CHECK-NEXT: dead %y:gprnox0 = COPY %x635 ; CHECK-NEXT: dead %v:vr = COPY $v8, implicit $vtype636 ; CHECK-NEXT: dead %x:gprnox0 = PseudoVSETVLI %x, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype637 %x:gprnox0 = COPY $x8638 dead $x0 = PseudoVSETIVLI 1, 208, implicit-def $vl, implicit-def $vtype639 %y:gprnox0 = COPY %x640 %v:vr = COPY $v8, implicit $vtype641 %x = PseudoVSETVLI %x, 208, implicit-def $vl, implicit-def $vtype642...643---644name: vsetvli_vleff645tracksRegLiveness: true646body: |647 ; CHECK-LABEL: name: vsetvli_vleff648 ; CHECK: bb.0:649 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)650 ; CHECK-NEXT: {{ $}}651 ; CHECK-NEXT: %vl:gpr = COPY $x0652 ; CHECK-NEXT: BNE $x0, $x0, %bb.2653 ; CHECK-NEXT: PseudoBR %bb.1654 ; CHECK-NEXT: {{ $}}655 ; CHECK-NEXT: bb.1:656 ; CHECK-NEXT: successors: %bb.2(0x80000000)657 ; CHECK-NEXT: {{ $}}658 ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 200 /* e16, m1, ta, ma */, implicit-def $vl, implicit-def $vtype659 ; CHECK-NEXT: $noreg, $x0 = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */, implicit $vl, implicit $vtype, implicit-def $vl660 ; CHECK-NEXT: %vl:gpr = PseudoReadVL implicit $vl661 ; CHECK-NEXT: {{ $}}662 ; CHECK-NEXT: bb.2:663 ; CHECK-NEXT: $x10 = COPY %vl664 ; CHECK-NEXT: PseudoRET implicit killed $x10665 bb.0:666 successors: %bb.1(0x40000000), %bb.2(0x40000000)667 668 %vl:gpr = COPY $x0669 BNE $x0, $x0, %bb.2670 PseudoBR %bb.1671 672 bb.1:673 successors: %bb.2(0x80000000)674 675 $noreg, %vl:gpr = PseudoVLE16FF_V_M1 $noreg, $noreg, 0, 4 /* e16 */, 2 /* tu, ma */676 677 bb.2:678 $x10 = COPY %vl679 PseudoRET implicit killed $x10680...681---682# The two vsetvlis will be coalesced so the ADDI will be made dead and removed.683# Make sure we shrink the live interval of %0.684name: non_li_addi685tracksRegLiveness: true686body: |687 bb.0:688 liveins: $x10689 ; CHECK-LABEL: name: non_li_addi690 ; CHECK: liveins: $x10691 ; CHECK-NEXT: {{ $}}692 ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:gpr = COPY $x10693 ; CHECK-NEXT: dead [[PseudoVSETIVLI:%[0-9]+]]:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype694 ; CHECK-NEXT: PseudoRET695 %0:gpr = COPY $x10696 %1:gprnox0 = ADDI %0, 1697 %2:gprnox0 = PseudoVSETVLI %1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype698 %3:gprnox0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype699 PseudoRET700