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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple riscv64 -mattr=+64bit,+m,+d,+zve64f,+zvfh \3; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefix=CHECK-NO-FELEN644; RUN: llc -mtriple riscv64 -mattr=+64bit,+m,+d,+zve64d,+zvfh \5; RUN: -target-abi=lp64d < %s | FileCheck %s --check-prefix=CHECK-FELEN646 7define void @foo(half %y, ptr %i64p) {8; CHECK-NO-FELEN64-LABEL: foo:9; CHECK-NO-FELEN64: # %bb.0: # %entry10; CHECK-NO-FELEN64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma11; CHECK-NO-FELEN64-NEXT: vle64.v v8, (a0)12; CHECK-NO-FELEN64-NEXT: vfmv.s.f v9, fa013; CHECK-NO-FELEN64-NEXT: #APP14; CHECK-NO-FELEN64-NEXT: # use v8 v915; CHECK-NO-FELEN64-NEXT: #NO_APP16; CHECK-NO-FELEN64-NEXT: ret17;18; CHECK-FELEN64-LABEL: foo:19; CHECK-FELEN64: # %bb.0: # %entry20; CHECK-FELEN64-NEXT: vsetivli zero, 1, e64, m1, ta, ma21; CHECK-FELEN64-NEXT: vle64.v v8, (a0)22; CHECK-FELEN64-NEXT: vfmv.s.f v9, fa023; CHECK-FELEN64-NEXT: #APP24; CHECK-FELEN64-NEXT: # use v8 v925; CHECK-FELEN64-NEXT: #NO_APP26; CHECK-FELEN64-NEXT: ret27entry:28 %0 = tail call <vscale x 1 x i64> @llvm.riscv.vle.nxv1i64.i64(<vscale x 1 x i64> poison, ptr %i64p, i64 1)29 %1 = tail call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16.i64(<vscale x 4 x half> poison, half %y, i64 1)30 tail call void asm sideeffect "# use $0 $1", "^vr,^vr"(<vscale x 1 x i64> %0, <vscale x 4 x half> %1)31 ret void32}33 34define void @bar(half %y, ptr %i32p) {35; CHECK-NO-FELEN64-LABEL: bar:36; CHECK-NO-FELEN64: # %bb.0: # %entry37; CHECK-NO-FELEN64-NEXT: vsetivli zero, 1, e32, m1, ta, ma38; CHECK-NO-FELEN64-NEXT: vle32.v v8, (a0)39; CHECK-NO-FELEN64-NEXT: vfmv.s.f v9, fa040; CHECK-NO-FELEN64-NEXT: #APP41; CHECK-NO-FELEN64-NEXT: # use v8 v942; CHECK-NO-FELEN64-NEXT: #NO_APP43; CHECK-NO-FELEN64-NEXT: ret44;45; CHECK-FELEN64-LABEL: bar:46; CHECK-FELEN64: # %bb.0: # %entry47; CHECK-FELEN64-NEXT: vsetivli zero, 1, e32, m1, ta, ma48; CHECK-FELEN64-NEXT: vle32.v v8, (a0)49; CHECK-FELEN64-NEXT: vfmv.s.f v9, fa050; CHECK-FELEN64-NEXT: #APP51; CHECK-FELEN64-NEXT: # use v8 v952; CHECK-FELEN64-NEXT: #NO_APP53; CHECK-FELEN64-NEXT: ret54entry:55 %0 = tail call <vscale x 2 x i32> @llvm.riscv.vle.nxv2i32.i64(<vscale x 2 x i32> poison, ptr %i32p, i64 1)56 %1 = tail call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16.i64(<vscale x 4 x half> poison, half %y, i64 1)57 tail call void asm sideeffect "# use $0 $1", "^vr,^vr"(<vscale x 2 x i32> %0, <vscale x 4 x half> %1)58 ret void59}60 61