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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v < %s | FileCheck %s4 5define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {6; CHECK-LABEL: vsext_nxv2i8_nxv2i16:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma9; CHECK-NEXT: vsext.vf2 v9, v8, v0.t10; CHECK-NEXT: vmv1r.v v8, v911; CHECK-NEXT: ret12 %v = call <vscale x 2 x i16> @llvm.vp.sext.nxv2i16.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)13 ret <vscale x 2 x i16> %v14}15 16define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {17; CHECK-LABEL: vsext_nxv2i8_nxv2i16_unmasked:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma20; CHECK-NEXT: vsext.vf2 v9, v821; CHECK-NEXT: vmv1r.v v8, v922; CHECK-NEXT: ret23 %v = call <vscale x 2 x i16> @llvm.vp.sext.nxv2i16.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)24 ret <vscale x 2 x i16> %v25}26 27define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {28; CHECK-LABEL: vsext_nxv2i8_nxv2i32:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma31; CHECK-NEXT: vsext.vf4 v9, v8, v0.t32; CHECK-NEXT: vmv.v.v v8, v933; CHECK-NEXT: ret34 %v = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)35 ret <vscale x 2 x i32> %v36}37 38define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {39; CHECK-LABEL: vsext_nxv2i8_nxv2i32_unmasked:40; CHECK: # %bb.0:41; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma42; CHECK-NEXT: vsext.vf4 v9, v843; CHECK-NEXT: vmv.v.v v8, v944; CHECK-NEXT: ret45 %v = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)46 ret <vscale x 2 x i32> %v47}48 49define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {50; CHECK-LABEL: vsext_nxv2i8_nxv2i64:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma53; CHECK-NEXT: vmv1r.v v10, v854; CHECK-NEXT: vsext.vf8 v8, v10, v0.t55; CHECK-NEXT: ret56 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> %m, i32 %vl)57 ret <vscale x 2 x i64> %v58}59 60define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64_unmasked(<vscale x 2 x i8> %a, i32 zeroext %vl) {61; CHECK-LABEL: vsext_nxv2i8_nxv2i64_unmasked:62; CHECK: # %bb.0:63; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma64; CHECK-NEXT: vmv1r.v v10, v865; CHECK-NEXT: vsext.vf8 v8, v1066; CHECK-NEXT: ret67 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i8(<vscale x 2 x i8> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)68 ret <vscale x 2 x i64> %v69}70 71define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {72; CHECK-LABEL: vsext_nxv2i16_nxv2i32:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma75; CHECK-NEXT: vsext.vf2 v9, v8, v0.t76; CHECK-NEXT: vmv.v.v v8, v977; CHECK-NEXT: ret78 %v = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)79 ret <vscale x 2 x i32> %v80}81 82define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {83; CHECK-LABEL: vsext_nxv2i16_nxv2i32_unmasked:84; CHECK: # %bb.0:85; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma86; CHECK-NEXT: vsext.vf2 v9, v887; CHECK-NEXT: vmv.v.v v8, v988; CHECK-NEXT: ret89 %v = call <vscale x 2 x i32> @llvm.vp.sext.nxv2i32.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)90 ret <vscale x 2 x i32> %v91}92 93define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {94; CHECK-LABEL: vsext_nxv2i16_nxv2i64:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma97; CHECK-NEXT: vmv1r.v v10, v898; CHECK-NEXT: vsext.vf4 v8, v10, v0.t99; CHECK-NEXT: ret100 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> %m, i32 %vl)101 ret <vscale x 2 x i64> %v102}103 104define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64_unmasked(<vscale x 2 x i16> %a, i32 zeroext %vl) {105; CHECK-LABEL: vsext_nxv2i16_nxv2i64_unmasked:106; CHECK: # %bb.0:107; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma108; CHECK-NEXT: vmv1r.v v10, v8109; CHECK-NEXT: vsext.vf4 v8, v10110; CHECK-NEXT: ret111 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i16(<vscale x 2 x i16> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)112 ret <vscale x 2 x i64> %v113}114 115define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {116; CHECK-LABEL: vsext_nxv2i32_nxv2i64:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma119; CHECK-NEXT: vmv1r.v v10, v8120; CHECK-NEXT: vsext.vf2 v8, v10, v0.t121; CHECK-NEXT: ret122 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 %vl)123 ret <vscale x 2 x i64> %v124}125 126define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64_unmasked(<vscale x 2 x i32> %a, i32 zeroext %vl) {127; CHECK-LABEL: vsext_nxv2i32_nxv2i64_unmasked:128; CHECK: # %bb.0:129; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma130; CHECK-NEXT: vmv1r.v v10, v8131; CHECK-NEXT: vsext.vf2 v8, v10132; CHECK-NEXT: ret133 %v = call <vscale x 2 x i64> @llvm.vp.sext.nxv2i64.nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i1> splat (i1 true), i32 %vl)134 ret <vscale x 2 x i64> %v135}136 137define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 zeroext %vl) {138; CHECK-LABEL: vsext_nxv32i8_nxv32i32:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma141; CHECK-NEXT: vmv1r.v v12, v0142; CHECK-NEXT: csrr a1, vlenb143; CHECK-NEXT: srli a2, a1, 2144; CHECK-NEXT: slli a1, a1, 1145; CHECK-NEXT: vslidedown.vx v0, v0, a2146; CHECK-NEXT: sub a2, a0, a1147; CHECK-NEXT: sltu a3, a0, a2148; CHECK-NEXT: addi a3, a3, -1149; CHECK-NEXT: and a2, a3, a2150; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma151; CHECK-NEXT: vsext.vf4 v16, v10, v0.t152; CHECK-NEXT: bltu a0, a1, .LBB12_2153; CHECK-NEXT: # %bb.1:154; CHECK-NEXT: mv a0, a1155; CHECK-NEXT: .LBB12_2:156; CHECK-NEXT: vmv1r.v v0, v12157; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma158; CHECK-NEXT: vsext.vf4 v24, v8, v0.t159; CHECK-NEXT: vmv.v.v v8, v24160; CHECK-NEXT: ret161 %v = call <vscale x 32 x i32> @llvm.vp.sext.nxv32i32.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i1> %m, i32 %vl)162 ret <vscale x 32 x i32> %v163}164 165define <vscale x 32 x i32> @vsext_nxv32i8_nxv32i32_unmasked(<vscale x 32 x i8> %a, i32 zeroext %vl) {166; CHECK-LABEL: vsext_nxv32i8_nxv32i32_unmasked:167; CHECK: # %bb.0:168; CHECK-NEXT: csrr a1, vlenb169; CHECK-NEXT: slli a1, a1, 1170; CHECK-NEXT: sub a2, a0, a1171; CHECK-NEXT: sltu a3, a0, a2172; CHECK-NEXT: addi a3, a3, -1173; CHECK-NEXT: and a2, a3, a2174; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma175; CHECK-NEXT: vsext.vf4 v16, v10176; CHECK-NEXT: bltu a0, a1, .LBB13_2177; CHECK-NEXT: # %bb.1:178; CHECK-NEXT: mv a0, a1179; CHECK-NEXT: .LBB13_2:180; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma181; CHECK-NEXT: vsext.vf4 v24, v8182; CHECK-NEXT: vmv.v.v v8, v24183; CHECK-NEXT: ret184 %v = call <vscale x 32 x i32> @llvm.vp.sext.nxv32i32.nxv32i8(<vscale x 32 x i8> %a, <vscale x 32 x i1> splat (i1 true), i32 %vl)185 ret <vscale x 32 x i32> %v186}187