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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6 7define <vscale x 1 x i64> @intrinsic_vsext_vf8_nxv1i64(<vscale x 1 x i8> %0, iXLen %1) nounwind {8; CHECK-LABEL: intrinsic_vsext_vf8_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma11; CHECK-NEXT: vsext.vf8 v9, v812; CHECK-NEXT: vmv.v.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i8(16 <vscale x 1 x i64> poison,17 <vscale x 1 x i8> %0,18 iXLen %1)19 20 ret <vscale x 1 x i64> %a21}22 23define <vscale x 1 x i64> @intrinsic_vsext_mask_vf8_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {24; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv1i64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu27; CHECK-NEXT: vsext.vf8 v8, v9, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i8(31 <vscale x 1 x i64> %1,32 <vscale x 1 x i8> %2,33 <vscale x 1 x i1> %0,34 iXLen %3, iXLen 1)35 36 ret <vscale x 1 x i64> %a37}38 39define <vscale x 2 x i64> @intrinsic_vsext_vf8_nxv2i64(<vscale x 2 x i8> %0, iXLen %1) nounwind {40; CHECK-LABEL: intrinsic_vsext_vf8_nxv2i64:41; CHECK: # %bb.0: # %entry42; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma43; CHECK-NEXT: vmv1r.v v10, v844; CHECK-NEXT: vsext.vf8 v8, v1045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i8(48 <vscale x 2 x i64> poison,49 <vscale x 2 x i8> %0,50 iXLen %1)51 52 ret <vscale x 2 x i64> %a53}54 55define <vscale x 2 x i64> @intrinsic_vsext_mask_vf8_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {56; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv2i64:57; CHECK: # %bb.0: # %entry58; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu59; CHECK-NEXT: vsext.vf8 v8, v10, v0.t60; CHECK-NEXT: ret61entry:62 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i8(63 <vscale x 2 x i64> %1,64 <vscale x 2 x i8> %2,65 <vscale x 2 x i1> %0,66 iXLen %3, iXLen 1)67 68 ret <vscale x 2 x i64> %a69}70 71define <vscale x 4 x i64> @intrinsic_vsext_vf8_nxv4i64(<vscale x 4 x i8> %0, iXLen %1) nounwind {72; CHECK-LABEL: intrinsic_vsext_vf8_nxv4i64:73; CHECK: # %bb.0: # %entry74; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma75; CHECK-NEXT: vmv1r.v v12, v876; CHECK-NEXT: vsext.vf8 v8, v1277; CHECK-NEXT: ret78entry:79 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i8(80 <vscale x 4 x i64> poison,81 <vscale x 4 x i8> %0,82 iXLen %1)83 84 ret <vscale x 4 x i64> %a85}86 87define <vscale x 4 x i64> @intrinsic_vsext_mask_vf8_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {88; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv4i64:89; CHECK: # %bb.0: # %entry90; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu91; CHECK-NEXT: vsext.vf8 v8, v12, v0.t92; CHECK-NEXT: ret93entry:94 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i8(95 <vscale x 4 x i64> %1,96 <vscale x 4 x i8> %2,97 <vscale x 4 x i1> %0,98 iXLen %3, iXLen 1)99 100 ret <vscale x 4 x i64> %a101}102 103define <vscale x 8 x i64> @intrinsic_vsext_vf8_nxv8i64(<vscale x 8 x i8> %0, iXLen %1) nounwind {104; CHECK-LABEL: intrinsic_vsext_vf8_nxv8i64:105; CHECK: # %bb.0: # %entry106; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma107; CHECK-NEXT: vmv1r.v v16, v8108; CHECK-NEXT: vsext.vf8 v8, v16109; CHECK-NEXT: ret110entry:111 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i8(112 <vscale x 8 x i64> poison,113 <vscale x 8 x i8> %0,114 iXLen %1)115 116 ret <vscale x 8 x i64> %a117}118 119define <vscale x 8 x i64> @intrinsic_vsext_mask_vf8_nxv8i64(<vscale x 8 x i1> %0, <vscale x 8 x i64> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {120; CHECK-LABEL: intrinsic_vsext_mask_vf8_nxv8i64:121; CHECK: # %bb.0: # %entry122; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu123; CHECK-NEXT: vsext.vf8 v8, v16, v0.t124; CHECK-NEXT: ret125entry:126 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i8(127 <vscale x 8 x i64> %1,128 <vscale x 8 x i8> %2,129 <vscale x 8 x i1> %0,130 iXLen %3, iXLen 1)131 132 ret <vscale x 8 x i64> %a133}134 135define <vscale x 1 x i64> @intrinsic_vsext_vf4_nxv1i64(<vscale x 1 x i16> %0, iXLen %1) nounwind {136; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i64:137; CHECK: # %bb.0: # %entry138; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma139; CHECK-NEXT: vsext.vf4 v9, v8140; CHECK-NEXT: vmv.v.v v8, v9141; CHECK-NEXT: ret142entry:143 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i16(144 <vscale x 1 x i64> poison,145 <vscale x 1 x i16> %0,146 iXLen %1)147 148 ret <vscale x 1 x i64> %a149}150 151define <vscale x 1 x i64> @intrinsic_vsext_mask_vf4_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {152; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv1i64:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu155; CHECK-NEXT: vsext.vf4 v8, v9, v0.t156; CHECK-NEXT: ret157entry:158 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i16(159 <vscale x 1 x i64> %1,160 <vscale x 1 x i16> %2,161 <vscale x 1 x i1> %0,162 iXLen %3, iXLen 1)163 164 ret <vscale x 1 x i64> %a165}166 167define <vscale x 2 x i64> @intrinsic_vsext_vf4_nxv2i64(<vscale x 2 x i16> %0, iXLen %1) nounwind {168; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i64:169; CHECK: # %bb.0: # %entry170; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma171; CHECK-NEXT: vmv1r.v v10, v8172; CHECK-NEXT: vsext.vf4 v8, v10173; CHECK-NEXT: ret174entry:175 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i16(176 <vscale x 2 x i64> poison,177 <vscale x 2 x i16> %0,178 iXLen %1)179 180 ret <vscale x 2 x i64> %a181}182 183define <vscale x 2 x i64> @intrinsic_vsext_mask_vf4_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {184; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv2i64:185; CHECK: # %bb.0: # %entry186; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu187; CHECK-NEXT: vsext.vf4 v8, v10, v0.t188; CHECK-NEXT: ret189entry:190 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i16(191 <vscale x 2 x i64> %1,192 <vscale x 2 x i16> %2,193 <vscale x 2 x i1> %0,194 iXLen %3, iXLen 1)195 196 ret <vscale x 2 x i64> %a197}198 199define <vscale x 4 x i64> @intrinsic_vsext_vf4_nxv4i64(<vscale x 4 x i16> %0, iXLen %1) nounwind {200; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i64:201; CHECK: # %bb.0: # %entry202; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma203; CHECK-NEXT: vmv1r.v v12, v8204; CHECK-NEXT: vsext.vf4 v8, v12205; CHECK-NEXT: ret206entry:207 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i16(208 <vscale x 4 x i64> poison,209 <vscale x 4 x i16> %0,210 iXLen %1)211 212 ret <vscale x 4 x i64> %a213}214 215define <vscale x 4 x i64> @intrinsic_vsext_mask_vf4_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {216; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv4i64:217; CHECK: # %bb.0: # %entry218; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu219; CHECK-NEXT: vsext.vf4 v8, v12, v0.t220; CHECK-NEXT: ret221entry:222 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i16(223 <vscale x 4 x i64> %1,224 <vscale x 4 x i16> %2,225 <vscale x 4 x i1> %0,226 iXLen %3, iXLen 1)227 228 ret <vscale x 4 x i64> %a229}230 231define <vscale x 8 x i64> @intrinsic_vsext_vf4_nxv8i64(<vscale x 8 x i16> %0, iXLen %1) nounwind {232; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i64:233; CHECK: # %bb.0: # %entry234; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma235; CHECK-NEXT: vmv2r.v v16, v8236; CHECK-NEXT: vsext.vf4 v8, v16237; CHECK-NEXT: ret238entry:239 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i16(240 <vscale x 8 x i64> poison,241 <vscale x 8 x i16> %0,242 iXLen %1)243 244 ret <vscale x 8 x i64> %a245}246 247define <vscale x 8 x i64> @intrinsic_vsext_mask_vf4_nxv8i64(<vscale x 8 x i1> %0, <vscale x 8 x i64> %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {248; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv8i64:249; CHECK: # %bb.0: # %entry250; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu251; CHECK-NEXT: vsext.vf4 v8, v16, v0.t252; CHECK-NEXT: ret253entry:254 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i16(255 <vscale x 8 x i64> %1,256 <vscale x 8 x i16> %2,257 <vscale x 8 x i1> %0,258 iXLen %3, iXLen 1)259 260 ret <vscale x 8 x i64> %a261}262 263define <vscale x 1 x i32> @intrinsic_vsext_vf4_nxv1i32(<vscale x 1 x i8> %0, iXLen %1) nounwind {264; CHECK-LABEL: intrinsic_vsext_vf4_nxv1i32:265; CHECK: # %bb.0: # %entry266; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma267; CHECK-NEXT: vsext.vf4 v9, v8268; CHECK-NEXT: vmv1r.v v8, v9269; CHECK-NEXT: ret270entry:271 %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i8(272 <vscale x 1 x i32> poison,273 <vscale x 1 x i8> %0,274 iXLen %1)275 276 ret <vscale x 1 x i32> %a277}278 279define <vscale x 1 x i32> @intrinsic_vsext_mask_vf4_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv1i32:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu283; CHECK-NEXT: vsext.vf4 v8, v9, v0.t284; CHECK-NEXT: ret285entry:286 %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i8(287 <vscale x 1 x i32> %1,288 <vscale x 1 x i8> %2,289 <vscale x 1 x i1> %0,290 iXLen %3, iXLen 1)291 292 ret <vscale x 1 x i32> %a293}294 295define <vscale x 2 x i32> @intrinsic_vsext_vf4_nxv2i32(<vscale x 2 x i8> %0, iXLen %1) nounwind {296; CHECK-LABEL: intrinsic_vsext_vf4_nxv2i32:297; CHECK: # %bb.0: # %entry298; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma299; CHECK-NEXT: vsext.vf4 v9, v8300; CHECK-NEXT: vmv.v.v v8, v9301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i8(304 <vscale x 2 x i32> poison,305 <vscale x 2 x i8> %0,306 iXLen %1)307 308 ret <vscale x 2 x i32> %a309}310 311define <vscale x 2 x i32> @intrinsic_vsext_mask_vf4_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {312; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv2i32:313; CHECK: # %bb.0: # %entry314; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu315; CHECK-NEXT: vsext.vf4 v8, v9, v0.t316; CHECK-NEXT: ret317entry:318 %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i8(319 <vscale x 2 x i32> %1,320 <vscale x 2 x i8> %2,321 <vscale x 2 x i1> %0,322 iXLen %3, iXLen 1)323 324 ret <vscale x 2 x i32> %a325}326 327define <vscale x 4 x i32> @intrinsic_vsext_vf4_nxv4i32(<vscale x 4 x i8> %0, iXLen %1) nounwind {328; CHECK-LABEL: intrinsic_vsext_vf4_nxv4i32:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma331; CHECK-NEXT: vmv1r.v v10, v8332; CHECK-NEXT: vsext.vf4 v8, v10333; CHECK-NEXT: ret334entry:335 %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i8(336 <vscale x 4 x i32> poison,337 <vscale x 4 x i8> %0,338 iXLen %1)339 340 ret <vscale x 4 x i32> %a341}342 343define <vscale x 4 x i32> @intrinsic_vsext_mask_vf4_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {344; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv4i32:345; CHECK: # %bb.0: # %entry346; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu347; CHECK-NEXT: vsext.vf4 v8, v10, v0.t348; CHECK-NEXT: ret349entry:350 %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i8(351 <vscale x 4 x i32> %1,352 <vscale x 4 x i8> %2,353 <vscale x 4 x i1> %0,354 iXLen %3, iXLen 1)355 356 ret <vscale x 4 x i32> %a357}358 359define <vscale x 8 x i32> @intrinsic_vsext_vf4_nxv8i32(<vscale x 8 x i8> %0, iXLen %1) nounwind {360; CHECK-LABEL: intrinsic_vsext_vf4_nxv8i32:361; CHECK: # %bb.0: # %entry362; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma363; CHECK-NEXT: vmv1r.v v12, v8364; CHECK-NEXT: vsext.vf4 v8, v12365; CHECK-NEXT: ret366entry:367 %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i8(368 <vscale x 8 x i32> poison,369 <vscale x 8 x i8> %0,370 iXLen %1)371 372 ret <vscale x 8 x i32> %a373}374 375define <vscale x 8 x i32> @intrinsic_vsext_mask_vf4_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {376; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv8i32:377; CHECK: # %bb.0: # %entry378; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu379; CHECK-NEXT: vsext.vf4 v8, v12, v0.t380; CHECK-NEXT: ret381entry:382 %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i8(383 <vscale x 8 x i32> %1,384 <vscale x 8 x i8> %2,385 <vscale x 8 x i1> %0,386 iXLen %3, iXLen 1)387 388 ret <vscale x 8 x i32> %a389}390 391define <vscale x 16 x i32> @intrinsic_vsext_vf4_nxv16i32(<vscale x 16 x i8> %0, iXLen %1) nounwind {392; CHECK-LABEL: intrinsic_vsext_vf4_nxv16i32:393; CHECK: # %bb.0: # %entry394; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma395; CHECK-NEXT: vmv2r.v v16, v8396; CHECK-NEXT: vsext.vf4 v8, v16397; CHECK-NEXT: ret398entry:399 %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i8(400 <vscale x 16 x i32> poison,401 <vscale x 16 x i8> %0,402 iXLen %1)403 404 ret <vscale x 16 x i32> %a405}406 407define <vscale x 16 x i32> @intrinsic_vsext_mask_vf4_nxv16i32(<vscale x 16 x i1> %0, <vscale x 16 x i32> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {408; CHECK-LABEL: intrinsic_vsext_mask_vf4_nxv16i32:409; CHECK: # %bb.0: # %entry410; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu411; CHECK-NEXT: vsext.vf4 v8, v16, v0.t412; CHECK-NEXT: ret413entry:414 %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i8(415 <vscale x 16 x i32> %1,416 <vscale x 16 x i8> %2,417 <vscale x 16 x i1> %0,418 iXLen %3, iXLen 1)419 420 ret <vscale x 16 x i32> %a421}422 423define <vscale x 1 x i64> @intrinsic_vsext_vf2_nxv1i64(<vscale x 1 x i32> %0, iXLen %1) nounwind {424; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i64:425; CHECK: # %bb.0: # %entry426; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma427; CHECK-NEXT: vsext.vf2 v9, v8428; CHECK-NEXT: vmv.v.v v8, v9429; CHECK-NEXT: ret430entry:431 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.nxv1i64.nxv1i32(432 <vscale x 1 x i64> poison,433 <vscale x 1 x i32> %0,434 iXLen %1)435 436 ret <vscale x 1 x i64> %a437}438 439define <vscale x 1 x i64> @intrinsic_vsext_mask_vf2_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i32> %2, iXLen %3) nounwind {440; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i64:441; CHECK: # %bb.0: # %entry442; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu443; CHECK-NEXT: vsext.vf2 v8, v9, v0.t444; CHECK-NEXT: ret445entry:446 %a = call <vscale x 1 x i64> @llvm.riscv.vsext.mask.nxv1i64.nxv1i32(447 <vscale x 1 x i64> %1,448 <vscale x 1 x i32> %2,449 <vscale x 1 x i1> %0,450 iXLen %3, iXLen 1)451 452 ret <vscale x 1 x i64> %a453}454 455define <vscale x 2 x i64> @intrinsic_vsext_vf2_nxv2i64(<vscale x 2 x i32> %0, iXLen %1) nounwind {456; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i64:457; CHECK: # %bb.0: # %entry458; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma459; CHECK-NEXT: vmv1r.v v10, v8460; CHECK-NEXT: vsext.vf2 v8, v10461; CHECK-NEXT: ret462entry:463 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.nxv2i64.nxv2i32(464 <vscale x 2 x i64> poison,465 <vscale x 2 x i32> %0,466 iXLen %1)467 468 ret <vscale x 2 x i64> %a469}470 471define <vscale x 2 x i64> @intrinsic_vsext_mask_vf2_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i32> %2, iXLen %3) nounwind {472; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i64:473; CHECK: # %bb.0: # %entry474; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu475; CHECK-NEXT: vsext.vf2 v8, v10, v0.t476; CHECK-NEXT: ret477entry:478 %a = call <vscale x 2 x i64> @llvm.riscv.vsext.mask.nxv2i64.nxv2i32(479 <vscale x 2 x i64> %1,480 <vscale x 2 x i32> %2,481 <vscale x 2 x i1> %0,482 iXLen %3, iXLen 1)483 484 ret <vscale x 2 x i64> %a485}486 487define <vscale x 4 x i64> @intrinsic_vsext_vf2_nxv4i64(<vscale x 4 x i32> %0, iXLen %1) nounwind {488; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i64:489; CHECK: # %bb.0: # %entry490; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma491; CHECK-NEXT: vmv2r.v v12, v8492; CHECK-NEXT: vsext.vf2 v8, v12493; CHECK-NEXT: ret494entry:495 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.nxv4i64.nxv4i32(496 <vscale x 4 x i64> poison,497 <vscale x 4 x i32> %0,498 iXLen %1)499 500 ret <vscale x 4 x i64> %a501}502 503define <vscale x 4 x i64> @intrinsic_vsext_mask_vf2_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {504; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i64:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu507; CHECK-NEXT: vsext.vf2 v8, v12, v0.t508; CHECK-NEXT: ret509entry:510 %a = call <vscale x 4 x i64> @llvm.riscv.vsext.mask.nxv4i64.nxv4i32(511 <vscale x 4 x i64> %1,512 <vscale x 4 x i32> %2,513 <vscale x 4 x i1> %0,514 iXLen %3, iXLen 1)515 516 ret <vscale x 4 x i64> %a517}518 519define <vscale x 8 x i64> @intrinsic_vsext_vf2_nxv8i64(<vscale x 8 x i32> %0, iXLen %1) nounwind {520; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i64:521; CHECK: # %bb.0: # %entry522; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma523; CHECK-NEXT: vmv4r.v v16, v8524; CHECK-NEXT: vsext.vf2 v8, v16525; CHECK-NEXT: ret526entry:527 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.nxv8i64.nxv8i32(528 <vscale x 8 x i64> poison,529 <vscale x 8 x i32> %0,530 iXLen %1)531 532 ret <vscale x 8 x i64> %a533}534 535define <vscale x 8 x i64> @intrinsic_vsext_mask_vf2_nxv8i64(<vscale x 8 x i1> %0, <vscale x 8 x i64> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {536; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i64:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu539; CHECK-NEXT: vsext.vf2 v8, v16, v0.t540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 8 x i64> @llvm.riscv.vsext.mask.nxv8i64.nxv8i32(543 <vscale x 8 x i64> %1,544 <vscale x 8 x i32> %2,545 <vscale x 8 x i1> %0,546 iXLen %3, iXLen 1)547 548 ret <vscale x 8 x i64> %a549}550 551define <vscale x 1 x i32> @intrinsic_vsext_vf2_nxv1i32(<vscale x 1 x i16> %0, iXLen %1) nounwind {552; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma555; CHECK-NEXT: vsext.vf2 v9, v8556; CHECK-NEXT: vmv1r.v v8, v9557; CHECK-NEXT: ret558entry:559 %a = call <vscale x 1 x i32> @llvm.riscv.vsext.nxv1i32.nxv1i16(560 <vscale x 1 x i32> poison,561 <vscale x 1 x i16> %0,562 iXLen %1)563 564 ret <vscale x 1 x i32> %a565}566 567define <vscale x 1 x i32> @intrinsic_vsext_mask_vf2_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i16> %2, iXLen %3) nounwind {568; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i32:569; CHECK: # %bb.0: # %entry570; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu571; CHECK-NEXT: vsext.vf2 v8, v9, v0.t572; CHECK-NEXT: ret573entry:574 %a = call <vscale x 1 x i32> @llvm.riscv.vsext.mask.nxv1i32.nxv1i16(575 <vscale x 1 x i32> %1,576 <vscale x 1 x i16> %2,577 <vscale x 1 x i1> %0,578 iXLen %3, iXLen 1)579 580 ret <vscale x 1 x i32> %a581}582 583define <vscale x 2 x i32> @intrinsic_vsext_vf2_nxv2i32(<vscale x 2 x i16> %0, iXLen %1) nounwind {584; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i32:585; CHECK: # %bb.0: # %entry586; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma587; CHECK-NEXT: vsext.vf2 v9, v8588; CHECK-NEXT: vmv.v.v v8, v9589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 2 x i32> @llvm.riscv.vsext.nxv2i32.nxv2i16(592 <vscale x 2 x i32> poison,593 <vscale x 2 x i16> %0,594 iXLen %1)595 596 ret <vscale x 2 x i32> %a597}598 599define <vscale x 2 x i32> @intrinsic_vsext_mask_vf2_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i16> %2, iXLen %3) nounwind {600; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i32:601; CHECK: # %bb.0: # %entry602; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu603; CHECK-NEXT: vsext.vf2 v8, v9, v0.t604; CHECK-NEXT: ret605entry:606 %a = call <vscale x 2 x i32> @llvm.riscv.vsext.mask.nxv2i32.nxv2i16(607 <vscale x 2 x i32> %1,608 <vscale x 2 x i16> %2,609 <vscale x 2 x i1> %0,610 iXLen %3, iXLen 1)611 612 ret <vscale x 2 x i32> %a613}614 615define <vscale x 4 x i32> @intrinsic_vsext_vf2_nxv4i32(<vscale x 4 x i16> %0, iXLen %1) nounwind {616; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i32:617; CHECK: # %bb.0: # %entry618; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma619; CHECK-NEXT: vmv1r.v v10, v8620; CHECK-NEXT: vsext.vf2 v8, v10621; CHECK-NEXT: ret622entry:623 %a = call <vscale x 4 x i32> @llvm.riscv.vsext.nxv4i32.nxv4i16(624 <vscale x 4 x i32> poison,625 <vscale x 4 x i16> %0,626 iXLen %1)627 628 ret <vscale x 4 x i32> %a629}630 631define <vscale x 4 x i32> @intrinsic_vsext_mask_vf2_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i16> %2, iXLen %3) nounwind {632; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i32:633; CHECK: # %bb.0: # %entry634; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu635; CHECK-NEXT: vsext.vf2 v8, v10, v0.t636; CHECK-NEXT: ret637entry:638 %a = call <vscale x 4 x i32> @llvm.riscv.vsext.mask.nxv4i32.nxv4i16(639 <vscale x 4 x i32> %1,640 <vscale x 4 x i16> %2,641 <vscale x 4 x i1> %0,642 iXLen %3, iXLen 1)643 644 ret <vscale x 4 x i32> %a645}646 647define <vscale x 8 x i32> @intrinsic_vsext_vf2_nxv8i32(<vscale x 8 x i16> %0, iXLen %1) nounwind {648; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i32:649; CHECK: # %bb.0: # %entry650; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma651; CHECK-NEXT: vmv2r.v v12, v8652; CHECK-NEXT: vsext.vf2 v8, v12653; CHECK-NEXT: ret654entry:655 %a = call <vscale x 8 x i32> @llvm.riscv.vsext.nxv8i32.nxv8i16(656 <vscale x 8 x i32> poison,657 <vscale x 8 x i16> %0,658 iXLen %1)659 660 ret <vscale x 8 x i32> %a661}662 663define <vscale x 8 x i32> @intrinsic_vsext_mask_vf2_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i16> %2, iXLen %3) nounwind {664; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i32:665; CHECK: # %bb.0: # %entry666; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu667; CHECK-NEXT: vsext.vf2 v8, v12, v0.t668; CHECK-NEXT: ret669entry:670 %a = call <vscale x 8 x i32> @llvm.riscv.vsext.mask.nxv8i32.nxv8i16(671 <vscale x 8 x i32> %1,672 <vscale x 8 x i16> %2,673 <vscale x 8 x i1> %0,674 iXLen %3, iXLen 1)675 676 ret <vscale x 8 x i32> %a677}678 679define <vscale x 16 x i32> @intrinsic_vsext_vf2_nxv16i32(<vscale x 16 x i16> %0, iXLen %1) nounwind {680; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i32:681; CHECK: # %bb.0: # %entry682; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma683; CHECK-NEXT: vmv4r.v v16, v8684; CHECK-NEXT: vsext.vf2 v8, v16685; CHECK-NEXT: ret686entry:687 %a = call <vscale x 16 x i32> @llvm.riscv.vsext.nxv16i32.nxv16i16(688 <vscale x 16 x i32> poison,689 <vscale x 16 x i16> %0,690 iXLen %1)691 692 ret <vscale x 16 x i32> %a693}694 695define <vscale x 16 x i32> @intrinsic_vsext_mask_vf2_nxv16i32(<vscale x 16 x i1> %0, <vscale x 16 x i32> %1, <vscale x 16 x i16> %2, iXLen %3) nounwind {696; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i32:697; CHECK: # %bb.0: # %entry698; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu699; CHECK-NEXT: vsext.vf2 v8, v16, v0.t700; CHECK-NEXT: ret701entry:702 %a = call <vscale x 16 x i32> @llvm.riscv.vsext.mask.nxv16i32.nxv16i16(703 <vscale x 16 x i32> %1,704 <vscale x 16 x i16> %2,705 <vscale x 16 x i1> %0,706 iXLen %3, iXLen 1)707 708 ret <vscale x 16 x i32> %a709}710 711define <vscale x 1 x i16> @intrinsic_vsext_vf2_nxv1i16(<vscale x 1 x i8> %0, iXLen %1) nounwind {712; CHECK-LABEL: intrinsic_vsext_vf2_nxv1i16:713; CHECK: # %bb.0: # %entry714; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma715; CHECK-NEXT: vsext.vf2 v9, v8716; CHECK-NEXT: vmv1r.v v8, v9717; CHECK-NEXT: ret718entry:719 %a = call <vscale x 1 x i16> @llvm.riscv.vsext.nxv1i16.nxv1i8(720 <vscale x 1 x i16> poison,721 <vscale x 1 x i8> %0,722 iXLen %1)723 724 ret <vscale x 1 x i16> %a725}726 727define <vscale x 1 x i16> @intrinsic_vsext_mask_vf2_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {728; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv1i16:729; CHECK: # %bb.0: # %entry730; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu731; CHECK-NEXT: vsext.vf2 v8, v9, v0.t732; CHECK-NEXT: ret733entry:734 %a = call <vscale x 1 x i16> @llvm.riscv.vsext.mask.nxv1i16.nxv1i8(735 <vscale x 1 x i16> %1,736 <vscale x 1 x i8> %2,737 <vscale x 1 x i1> %0,738 iXLen %3, iXLen 1)739 740 ret <vscale x 1 x i16> %a741}742 743define <vscale x 2 x i16> @intrinsic_vsext_vf2_nxv2i16(<vscale x 2 x i8> %0, iXLen %1) nounwind {744; CHECK-LABEL: intrinsic_vsext_vf2_nxv2i16:745; CHECK: # %bb.0: # %entry746; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma747; CHECK-NEXT: vsext.vf2 v9, v8748; CHECK-NEXT: vmv1r.v v8, v9749; CHECK-NEXT: ret750entry:751 %a = call <vscale x 2 x i16> @llvm.riscv.vsext.nxv2i16.nxv2i8(752 <vscale x 2 x i16> poison,753 <vscale x 2 x i8> %0,754 iXLen %1)755 756 ret <vscale x 2 x i16> %a757}758 759define <vscale x 2 x i16> @intrinsic_vsext_mask_vf2_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i8> %2, iXLen %3) nounwind {760; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv2i16:761; CHECK: # %bb.0: # %entry762; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu763; CHECK-NEXT: vsext.vf2 v8, v9, v0.t764; CHECK-NEXT: ret765entry:766 %a = call <vscale x 2 x i16> @llvm.riscv.vsext.mask.nxv2i16.nxv2i8(767 <vscale x 2 x i16> %1,768 <vscale x 2 x i8> %2,769 <vscale x 2 x i1> %0,770 iXLen %3, iXLen 1)771 772 ret <vscale x 2 x i16> %a773}774 775define <vscale x 4 x i16> @intrinsic_vsext_vf2_nxv4i16(<vscale x 4 x i8> %0, iXLen %1) nounwind {776; CHECK-LABEL: intrinsic_vsext_vf2_nxv4i16:777; CHECK: # %bb.0: # %entry778; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma779; CHECK-NEXT: vsext.vf2 v9, v8780; CHECK-NEXT: vmv.v.v v8, v9781; CHECK-NEXT: ret782entry:783 %a = call <vscale x 4 x i16> @llvm.riscv.vsext.nxv4i16.nxv4i8(784 <vscale x 4 x i16> poison,785 <vscale x 4 x i8> %0,786 iXLen %1)787 788 ret <vscale x 4 x i16> %a789}790 791define <vscale x 4 x i16> @intrinsic_vsext_mask_vf2_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i8> %2, iXLen %3) nounwind {792; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv4i16:793; CHECK: # %bb.0: # %entry794; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu795; CHECK-NEXT: vsext.vf2 v8, v9, v0.t796; CHECK-NEXT: ret797entry:798 %a = call <vscale x 4 x i16> @llvm.riscv.vsext.mask.nxv4i16.nxv4i8(799 <vscale x 4 x i16> %1,800 <vscale x 4 x i8> %2,801 <vscale x 4 x i1> %0,802 iXLen %3, iXLen 1)803 804 ret <vscale x 4 x i16> %a805}806 807define <vscale x 8 x i16> @intrinsic_vsext_vf2_nxv8i16(<vscale x 8 x i8> %0, iXLen %1) nounwind {808; CHECK-LABEL: intrinsic_vsext_vf2_nxv8i16:809; CHECK: # %bb.0: # %entry810; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma811; CHECK-NEXT: vmv1r.v v10, v8812; CHECK-NEXT: vsext.vf2 v8, v10813; CHECK-NEXT: ret814entry:815 %a = call <vscale x 8 x i16> @llvm.riscv.vsext.nxv8i16.nxv8i8(816 <vscale x 8 x i16> poison,817 <vscale x 8 x i8> %0,818 iXLen %1)819 820 ret <vscale x 8 x i16> %a821}822 823define <vscale x 8 x i16> @intrinsic_vsext_mask_vf2_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i8> %2, iXLen %3) nounwind {824; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv8i16:825; CHECK: # %bb.0: # %entry826; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu827; CHECK-NEXT: vsext.vf2 v8, v10, v0.t828; CHECK-NEXT: ret829entry:830 %a = call <vscale x 8 x i16> @llvm.riscv.vsext.mask.nxv8i16.nxv8i8(831 <vscale x 8 x i16> %1,832 <vscale x 8 x i8> %2,833 <vscale x 8 x i1> %0,834 iXLen %3, iXLen 1)835 836 ret <vscale x 8 x i16> %a837}838 839define <vscale x 16 x i16> @intrinsic_vsext_vf2_nxv16i16(<vscale x 16 x i8> %0, iXLen %1) nounwind {840; CHECK-LABEL: intrinsic_vsext_vf2_nxv16i16:841; CHECK: # %bb.0: # %entry842; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma843; CHECK-NEXT: vmv2r.v v12, v8844; CHECK-NEXT: vsext.vf2 v8, v12845; CHECK-NEXT: ret846entry:847 %a = call <vscale x 16 x i16> @llvm.riscv.vsext.nxv16i16.nxv16i8(848 <vscale x 16 x i16> poison,849 <vscale x 16 x i8> %0,850 iXLen %1)851 852 ret <vscale x 16 x i16> %a853}854 855define <vscale x 16 x i16> @intrinsic_vsext_mask_vf2_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i8> %2, iXLen %3) nounwind {856; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv16i16:857; CHECK: # %bb.0: # %entry858; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu859; CHECK-NEXT: vsext.vf2 v8, v12, v0.t860; CHECK-NEXT: ret861entry:862 %a = call <vscale x 16 x i16> @llvm.riscv.vsext.mask.nxv16i16.nxv16i8(863 <vscale x 16 x i16> %1,864 <vscale x 16 x i8> %2,865 <vscale x 16 x i1> %0,866 iXLen %3, iXLen 1)867 868 ret <vscale x 16 x i16> %a869}870 871define <vscale x 32 x i16> @intrinsic_vsext_vf2_nxv32i16(<vscale x 32 x i8> %0, iXLen %1) nounwind {872; CHECK-LABEL: intrinsic_vsext_vf2_nxv32i16:873; CHECK: # %bb.0: # %entry874; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma875; CHECK-NEXT: vmv4r.v v16, v8876; CHECK-NEXT: vsext.vf2 v8, v16877; CHECK-NEXT: ret878entry:879 %a = call <vscale x 32 x i16> @llvm.riscv.vsext.nxv32i16.nxv32i8(880 <vscale x 32 x i16> poison,881 <vscale x 32 x i8> %0,882 iXLen %1)883 884 ret <vscale x 32 x i16> %a885}886 887define <vscale x 32 x i16> @intrinsic_vsext_mask_vf2_nxv32i16(<vscale x 32 x i1> %0, <vscale x 32 x i16> %1, <vscale x 32 x i8> %2, iXLen %3) nounwind {888; CHECK-LABEL: intrinsic_vsext_mask_vf2_nxv32i16:889; CHECK: # %bb.0: # %entry890; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu891; CHECK-NEXT: vsext.vf2 v8, v16, v0.t892; CHECK-NEXT: ret893entry:894 %a = call <vscale x 32 x i16> @llvm.riscv.vsext.mask.nxv32i16.nxv32i8(895 <vscale x 32 x i16> %1,896 <vscale x 32 x i8> %2,897 <vscale x 32 x i1> %0,898 iXLen %3, iXLen 1)899 900 ret <vscale x 32 x i16> %a901}902