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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvknha,+zvknhb \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvknha,+zvknhb \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK6; RUN: sed 's/iXLen/i32/g' %s | not llc -mtriple=riscv32 -mattr=+v,+zvknha 2>&1 \7; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s8; RUN: sed 's/iXLen/i64/g' %s | not llc -mtriple=riscv64 -mattr=+v,+zvknha 2>&1 \9; RUN: | FileCheck --check-prefixes=CHECK-ERROR %s10 11; CHECK-ERROR: LLVM ERROR: SEW=64 needs Zvknhb to be enabled.12 13define <vscale x 4 x i32> @intrinsic_vsha2ms_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, iXLen %3) nounwind {14; CHECK-LABEL: intrinsic_vsha2ms_vv_nxv4i32_nxv4i32:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma17; CHECK-NEXT: vsha2ms.vv v8, v10, v1218; CHECK-NEXT: ret19entry:20 %a = call <vscale x 4 x i32> @llvm.riscv.vsha2ms.nxv4i32.nxv4i32(21 <vscale x 4 x i32> %0,22 <vscale x 4 x i32> %1,23 <vscale x 4 x i32> %2,24 iXLen %3,25 iXLen 2)26 27 ret <vscale x 4 x i32> %a28}29 30define <vscale x 8 x i32> @intrinsic_vsha2ms_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, iXLen %3) nounwind {31; CHECK-LABEL: intrinsic_vsha2ms_vv_nxv8i32_nxv8i32:32; CHECK: # %bb.0: # %entry33; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma34; CHECK-NEXT: vsha2ms.vv v8, v12, v1635; CHECK-NEXT: ret36entry:37 %a = call <vscale x 8 x i32> @llvm.riscv.vsha2ms.nxv8i32.nxv8i32(38 <vscale x 8 x i32> %0,39 <vscale x 8 x i32> %1,40 <vscale x 8 x i32> %2,41 iXLen %3,42 iXLen 2)43 44 ret <vscale x 8 x i32> %a45}46 47define <vscale x 16 x i32> @intrinsic_vsha2ms_vv_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, iXLen %3) nounwind {48; CHECK-LABEL: intrinsic_vsha2ms_vv_nxv16i32_nxv16i32:49; CHECK: # %bb.0: # %entry50; CHECK-NEXT: vl8re32.v v24, (a0)51; CHECK-NEXT: vsetvli zero, a1, e32, m8, tu, ma52; CHECK-NEXT: vsha2ms.vv v8, v16, v2453; CHECK-NEXT: ret54entry:55 %a = call <vscale x 16 x i32> @llvm.riscv.vsha2ms.nxv16i32.nxv16i32(56 <vscale x 16 x i32> %0,57 <vscale x 16 x i32> %1,58 <vscale x 16 x i32> %2,59 iXLen %3,60 iXLen 2)61 62 ret <vscale x 16 x i32> %a63}64 65define <vscale x 4 x i64> @intrinsic_vsha2ms_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, iXLen %3) nounwind {66; CHECK-LABEL: intrinsic_vsha2ms_vv_nxv4i64_nxv4i64:67; CHECK: # %bb.0: # %entry68; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma69; CHECK-NEXT: vsha2ms.vv v8, v12, v1670; CHECK-NEXT: ret71entry:72 %a = call <vscale x 4 x i64> @llvm.riscv.vsha2ms.nxv4i64.nxv4i64(73 <vscale x 4 x i64> %0,74 <vscale x 4 x i64> %1,75 <vscale x 4 x i64> %2,76 iXLen %3,77 iXLen 2)78 79 ret <vscale x 4 x i64> %a80}81 82define <vscale x 8 x i64> @intrinsic_vsha2ms_vv_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, iXLen %3) nounwind {83; CHECK-LABEL: intrinsic_vsha2ms_vv_nxv8i64_nxv8i64:84; CHECK: # %bb.0: # %entry85; CHECK-NEXT: vl8re64.v v24, (a0)86; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma87; CHECK-NEXT: vsha2ms.vv v8, v16, v2488; CHECK-NEXT: ret89entry:90 %a = call <vscale x 8 x i64> @llvm.riscv.vsha2ms.nxv8i64.nxv8i64(91 <vscale x 8 x i64> %0,92 <vscale x 8 x i64> %1,93 <vscale x 8 x i64> %2,94 iXLen %3,95 iXLen 2)96 97 ret <vscale x 8 x i64> %a98}99