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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @vshl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {6; CHECK-LABEL: vshl_vx_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma9; CHECK-NEXT: vsll.vx v8, v8, a010; CHECK-NEXT: ret11 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 012 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer13 %vc = shl <vscale x 1 x i8> %va, %splat14 ret <vscale x 1 x i8> %vc15}16 17define <vscale x 1 x i8> @vshl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {18; CHECK-LABEL: vshl_vx_nxv1i8_0:19; CHECK: # %bb.0:20; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma21; CHECK-NEXT: vsll.vi v8, v8, 622; CHECK-NEXT: ret23 %vc = shl <vscale x 1 x i8> %va, splat (i8 6)24 ret <vscale x 1 x i8> %vc25}26 27define <vscale x 2 x i8> @vshl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {28; CHECK-LABEL: vshl_vx_nxv2i8:29; CHECK: # %bb.0:30; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma31; CHECK-NEXT: vsll.vx v8, v8, a032; CHECK-NEXT: ret33 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 034 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer35 %vc = shl <vscale x 2 x i8> %va, %splat36 ret <vscale x 2 x i8> %vc37}38 39define <vscale x 2 x i8> @vshl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {40; CHECK-LABEL: vshl_vx_nxv2i8_0:41; CHECK: # %bb.0:42; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma43; CHECK-NEXT: vsll.vi v8, v8, 644; CHECK-NEXT: ret45 %vc = shl <vscale x 2 x i8> %va, splat (i8 6)46 ret <vscale x 2 x i8> %vc47}48 49define <vscale x 4 x i8> @vshl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {50; CHECK-LABEL: vshl_vx_nxv4i8:51; CHECK: # %bb.0:52; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma53; CHECK-NEXT: vsll.vx v8, v8, a054; CHECK-NEXT: ret55 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 056 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer57 %vc = shl <vscale x 4 x i8> %va, %splat58 ret <vscale x 4 x i8> %vc59}60 61define <vscale x 4 x i8> @vshl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {62; CHECK-LABEL: vshl_vx_nxv4i8_0:63; CHECK: # %bb.0:64; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma65; CHECK-NEXT: vsll.vi v8, v8, 666; CHECK-NEXT: ret67 %vc = shl <vscale x 4 x i8> %va, splat (i8 6)68 ret <vscale x 4 x i8> %vc69}70 71define <vscale x 8 x i8> @vshl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {72; CHECK-LABEL: vshl_vx_nxv8i8:73; CHECK: # %bb.0:74; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma75; CHECK-NEXT: vsll.vx v8, v8, a076; CHECK-NEXT: ret77 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 078 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer79 %vc = shl <vscale x 8 x i8> %va, %splat80 ret <vscale x 8 x i8> %vc81}82 83define <vscale x 8 x i8> @vshl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {84; CHECK-LABEL: vshl_vx_nxv8i8_0:85; CHECK: # %bb.0:86; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma87; CHECK-NEXT: vsll.vi v8, v8, 688; CHECK-NEXT: ret89 %vc = shl <vscale x 8 x i8> %va, splat (i8 6)90 ret <vscale x 8 x i8> %vc91}92 93define <vscale x 16 x i8> @vshl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {94; CHECK-LABEL: vshl_vx_nxv16i8:95; CHECK: # %bb.0:96; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma97; CHECK-NEXT: vsll.vx v8, v8, a098; CHECK-NEXT: ret99 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0100 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer101 %vc = shl <vscale x 16 x i8> %va, %splat102 ret <vscale x 16 x i8> %vc103}104 105define <vscale x 16 x i8> @vshl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {106; CHECK-LABEL: vshl_vx_nxv16i8_0:107; CHECK: # %bb.0:108; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma109; CHECK-NEXT: vsll.vi v8, v8, 6110; CHECK-NEXT: ret111 %vc = shl <vscale x 16 x i8> %va, splat (i8 6)112 ret <vscale x 16 x i8> %vc113}114 115define <vscale x 32 x i8> @vshl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {116; CHECK-LABEL: vshl_vx_nxv32i8:117; CHECK: # %bb.0:118; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma119; CHECK-NEXT: vsll.vx v8, v8, a0120; CHECK-NEXT: ret121 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0122 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer123 %vc = shl <vscale x 32 x i8> %va, %splat124 ret <vscale x 32 x i8> %vc125}126 127define <vscale x 32 x i8> @vshl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {128; CHECK-LABEL: vshl_vx_nxv32i8_0:129; CHECK: # %bb.0:130; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma131; CHECK-NEXT: vsll.vi v8, v8, 6132; CHECK-NEXT: ret133 %vc = shl <vscale x 32 x i8> %va, splat (i8 6)134 ret <vscale x 32 x i8> %vc135}136 137define <vscale x 64 x i8> @vshl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {138; CHECK-LABEL: vshl_vx_nxv64i8:139; CHECK: # %bb.0:140; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma141; CHECK-NEXT: vsll.vx v8, v8, a0142; CHECK-NEXT: ret143 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0144 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer145 %vc = shl <vscale x 64 x i8> %va, %splat146 ret <vscale x 64 x i8> %vc147}148 149define <vscale x 64 x i8> @vshl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {150; CHECK-LABEL: vshl_vx_nxv64i8_0:151; CHECK: # %bb.0:152; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma153; CHECK-NEXT: vsll.vi v8, v8, 6154; CHECK-NEXT: ret155 %vc = shl <vscale x 64 x i8> %va, splat (i8 6)156 ret <vscale x 64 x i8> %vc157}158 159define <vscale x 1 x i16> @vshl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {160; CHECK-LABEL: vshl_vx_nxv1i16:161; CHECK: # %bb.0:162; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma163; CHECK-NEXT: vsll.vx v8, v8, a0164; CHECK-NEXT: ret165 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0166 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer167 %vc = shl <vscale x 1 x i16> %va, %splat168 ret <vscale x 1 x i16> %vc169}170 171define <vscale x 1 x i16> @vshl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {172; CHECK-LABEL: vshl_vx_nxv1i16_0:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma175; CHECK-NEXT: vsll.vi v8, v8, 6176; CHECK-NEXT: ret177 %vc = shl <vscale x 1 x i16> %va, splat (i16 6)178 ret <vscale x 1 x i16> %vc179}180 181define <vscale x 2 x i16> @vshl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {182; CHECK-LABEL: vshl_vx_nxv2i16:183; CHECK: # %bb.0:184; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma185; CHECK-NEXT: vsll.vx v8, v8, a0186; CHECK-NEXT: ret187 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0188 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer189 %vc = shl <vscale x 2 x i16> %va, %splat190 ret <vscale x 2 x i16> %vc191}192 193define <vscale x 2 x i16> @vshl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {194; CHECK-LABEL: vshl_vx_nxv2i16_0:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma197; CHECK-NEXT: vsll.vi v8, v8, 6198; CHECK-NEXT: ret199 %vc = shl <vscale x 2 x i16> %va, splat (i16 6)200 ret <vscale x 2 x i16> %vc201}202 203define <vscale x 4 x i16> @vshl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {204; CHECK-LABEL: vshl_vx_nxv4i16:205; CHECK: # %bb.0:206; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma207; CHECK-NEXT: vsll.vx v8, v8, a0208; CHECK-NEXT: ret209 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0210 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer211 %vc = shl <vscale x 4 x i16> %va, %splat212 ret <vscale x 4 x i16> %vc213}214 215define <vscale x 4 x i16> @vshl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {216; CHECK-LABEL: vshl_vx_nxv4i16_0:217; CHECK: # %bb.0:218; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma219; CHECK-NEXT: vsll.vi v8, v8, 6220; CHECK-NEXT: ret221 %vc = shl <vscale x 4 x i16> %va, splat (i16 6)222 ret <vscale x 4 x i16> %vc223}224 225define <vscale x 8 x i16> @vshl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {226; CHECK-LABEL: vshl_vx_nxv8i16:227; CHECK: # %bb.0:228; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma229; CHECK-NEXT: vsll.vx v8, v8, a0230; CHECK-NEXT: ret231 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0232 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer233 %vc = shl <vscale x 8 x i16> %va, %splat234 ret <vscale x 8 x i16> %vc235}236 237define <vscale x 8 x i16> @vshl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {238; CHECK-LABEL: vshl_vx_nxv8i16_0:239; CHECK: # %bb.0:240; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma241; CHECK-NEXT: vsll.vi v8, v8, 6242; CHECK-NEXT: ret243 %vc = shl <vscale x 8 x i16> %va, splat (i16 6)244 ret <vscale x 8 x i16> %vc245}246 247define <vscale x 16 x i16> @vshl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {248; CHECK-LABEL: vshl_vx_nxv16i16:249; CHECK: # %bb.0:250; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma251; CHECK-NEXT: vsll.vx v8, v8, a0252; CHECK-NEXT: ret253 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0254 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer255 %vc = shl <vscale x 16 x i16> %va, %splat256 ret <vscale x 16 x i16> %vc257}258 259define <vscale x 16 x i16> @vshl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {260; CHECK-LABEL: vshl_vx_nxv16i16_0:261; CHECK: # %bb.0:262; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma263; CHECK-NEXT: vsll.vi v8, v8, 6264; CHECK-NEXT: ret265 %vc = shl <vscale x 16 x i16> %va, splat (i16 6)266 ret <vscale x 16 x i16> %vc267}268 269define <vscale x 32 x i16> @vshl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {270; CHECK-LABEL: vshl_vx_nxv32i16:271; CHECK: # %bb.0:272; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma273; CHECK-NEXT: vsll.vx v8, v8, a0274; CHECK-NEXT: ret275 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0276 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer277 %vc = shl <vscale x 32 x i16> %va, %splat278 ret <vscale x 32 x i16> %vc279}280 281define <vscale x 32 x i16> @vshl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {282; CHECK-LABEL: vshl_vx_nxv32i16_0:283; CHECK: # %bb.0:284; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma285; CHECK-NEXT: vsll.vi v8, v8, 6286; CHECK-NEXT: ret287 %vc = shl <vscale x 32 x i16> %va, splat (i16 6)288 ret <vscale x 32 x i16> %vc289}290 291define <vscale x 1 x i32> @vshl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {292; CHECK-LABEL: vshl_vx_nxv1i32:293; CHECK: # %bb.0:294; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma295; CHECK-NEXT: vsll.vx v8, v8, a0296; CHECK-NEXT: ret297 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0298 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer299 %vc = shl <vscale x 1 x i32> %va, %splat300 ret <vscale x 1 x i32> %vc301}302 303define <vscale x 1 x i32> @vshl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {304; CHECK-LABEL: vshl_vx_nxv1i32_0:305; CHECK: # %bb.0:306; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma307; CHECK-NEXT: vsll.vi v8, v8, 31308; CHECK-NEXT: ret309 %vc = shl <vscale x 1 x i32> %va, splat (i32 31)310 ret <vscale x 1 x i32> %vc311}312 313define <vscale x 2 x i32> @vshl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {314; CHECK-LABEL: vshl_vx_nxv2i32:315; CHECK: # %bb.0:316; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma317; CHECK-NEXT: vsll.vx v8, v8, a0318; CHECK-NEXT: ret319 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0320 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer321 %vc = shl <vscale x 2 x i32> %va, %splat322 ret <vscale x 2 x i32> %vc323}324 325define <vscale x 2 x i32> @vshl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {326; CHECK-LABEL: vshl_vx_nxv2i32_0:327; CHECK: # %bb.0:328; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma329; CHECK-NEXT: vsll.vi v8, v8, 31330; CHECK-NEXT: ret331 %vc = shl <vscale x 2 x i32> %va, splat (i32 31)332 ret <vscale x 2 x i32> %vc333}334 335define <vscale x 4 x i32> @vshl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {336; CHECK-LABEL: vshl_vx_nxv4i32:337; CHECK: # %bb.0:338; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma339; CHECK-NEXT: vsll.vx v8, v8, a0340; CHECK-NEXT: ret341 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0342 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer343 %vc = shl <vscale x 4 x i32> %va, %splat344 ret <vscale x 4 x i32> %vc345}346 347define <vscale x 4 x i32> @vshl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {348; CHECK-LABEL: vshl_vx_nxv4i32_0:349; CHECK: # %bb.0:350; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma351; CHECK-NEXT: vsll.vi v8, v8, 31352; CHECK-NEXT: ret353 %vc = shl <vscale x 4 x i32> %va, splat (i32 31)354 ret <vscale x 4 x i32> %vc355}356 357define <vscale x 8 x i32> @vshl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {358; CHECK-LABEL: vshl_vx_nxv8i32:359; CHECK: # %bb.0:360; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma361; CHECK-NEXT: vsll.vx v8, v8, a0362; CHECK-NEXT: ret363 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0364 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer365 %vc = shl <vscale x 8 x i32> %va, %splat366 ret <vscale x 8 x i32> %vc367}368 369define <vscale x 8 x i32> @vshl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {370; CHECK-LABEL: vshl_vx_nxv8i32_0:371; CHECK: # %bb.0:372; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma373; CHECK-NEXT: vsll.vi v8, v8, 31374; CHECK-NEXT: ret375 %vc = shl <vscale x 8 x i32> %va, splat (i32 31)376 ret <vscale x 8 x i32> %vc377}378 379define <vscale x 16 x i32> @vshl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {380; CHECK-LABEL: vshl_vx_nxv16i32:381; CHECK: # %bb.0:382; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma383; CHECK-NEXT: vsll.vx v8, v8, a0384; CHECK-NEXT: ret385 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0386 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer387 %vc = shl <vscale x 16 x i32> %va, %splat388 ret <vscale x 16 x i32> %vc389}390 391define <vscale x 16 x i32> @vshl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {392; CHECK-LABEL: vshl_vx_nxv16i32_0:393; CHECK: # %bb.0:394; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma395; CHECK-NEXT: vsll.vi v8, v8, 31396; CHECK-NEXT: ret397 %vc = shl <vscale x 16 x i32> %va, splat (i32 31)398 ret <vscale x 16 x i32> %vc399}400 401define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {402; CHECK-LABEL: vshl_vx_nxv1i64:403; CHECK: # %bb.0:404; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma405; CHECK-NEXT: vsll.vx v8, v8, a0406; CHECK-NEXT: ret407 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0408 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer409 %vc = shl <vscale x 1 x i64> %va, %splat410 ret <vscale x 1 x i64> %vc411}412 413define <vscale x 1 x i64> @vshl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {414; CHECK-LABEL: vshl_vx_nxv1i64_0:415; CHECK: # %bb.0:416; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma417; CHECK-NEXT: vsll.vi v8, v8, 31418; CHECK-NEXT: ret419 %vc = shl <vscale x 1 x i64> %va, splat (i64 31)420 ret <vscale x 1 x i64> %vc421}422 423define <vscale x 1 x i64> @vshl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {424; CHECK-LABEL: vshl_vx_nxv1i64_1:425; CHECK: # %bb.0:426; CHECK-NEXT: li a0, 32427; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma428; CHECK-NEXT: vsll.vx v8, v8, a0429; CHECK-NEXT: ret430 %vc = shl <vscale x 1 x i64> %va, splat (i64 32)431 ret <vscale x 1 x i64> %vc432}433 434define <vscale x 1 x i64> @vshl_vx_nxv1i64_2(<vscale x 1 x i64> %va) {435; CHECK-LABEL: vshl_vx_nxv1i64_2:436; CHECK: # %bb.0:437; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma438; CHECK-NEXT: vadd.vv v8, v8, v8439; CHECK-NEXT: ret440 %vc = shl <vscale x 1 x i64> %va, splat (i64 1)441 ret <vscale x 1 x i64> %vc442}443 444define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {445; CHECK-LABEL: vshl_vx_nxv2i64:446; CHECK: # %bb.0:447; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma448; CHECK-NEXT: vsll.vx v8, v8, a0449; CHECK-NEXT: ret450 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0451 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer452 %vc = shl <vscale x 2 x i64> %va, %splat453 ret <vscale x 2 x i64> %vc454}455 456define <vscale x 2 x i64> @vshl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {457; CHECK-LABEL: vshl_vx_nxv2i64_0:458; CHECK: # %bb.0:459; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma460; CHECK-NEXT: vsll.vi v8, v8, 31461; CHECK-NEXT: ret462 %vc = shl <vscale x 2 x i64> %va, splat (i64 31)463 ret <vscale x 2 x i64> %vc464}465 466define <vscale x 2 x i64> @vshl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {467; CHECK-LABEL: vshl_vx_nxv2i64_1:468; CHECK: # %bb.0:469; CHECK-NEXT: li a0, 32470; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma471; CHECK-NEXT: vsll.vx v8, v8, a0472; CHECK-NEXT: ret473 %vc = shl <vscale x 2 x i64> %va, splat (i64 32)474 ret <vscale x 2 x i64> %vc475}476 477define <vscale x 2 x i64> @vshl_vx_nxv2i64_2(<vscale x 2 x i64> %va) {478; CHECK-LABEL: vshl_vx_nxv2i64_2:479; CHECK: # %bb.0:480; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma481; CHECK-NEXT: vadd.vv v8, v8, v8482; CHECK-NEXT: ret483 %vc = shl <vscale x 2 x i64> %va, splat (i64 1)484 ret <vscale x 2 x i64> %vc485}486 487define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {488; CHECK-LABEL: vshl_vx_nxv4i64:489; CHECK: # %bb.0:490; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma491; CHECK-NEXT: vsll.vx v8, v8, a0492; CHECK-NEXT: ret493 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0494 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer495 %vc = shl <vscale x 4 x i64> %va, %splat496 ret <vscale x 4 x i64> %vc497}498 499define <vscale x 4 x i64> @vshl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {500; CHECK-LABEL: vshl_vx_nxv4i64_0:501; CHECK: # %bb.0:502; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma503; CHECK-NEXT: vsll.vi v8, v8, 31504; CHECK-NEXT: ret505 %vc = shl <vscale x 4 x i64> %va, splat (i64 31)506 ret <vscale x 4 x i64> %vc507}508 509define <vscale x 4 x i64> @vshl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {510; CHECK-LABEL: vshl_vx_nxv4i64_1:511; CHECK: # %bb.0:512; CHECK-NEXT: li a0, 32513; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma514; CHECK-NEXT: vsll.vx v8, v8, a0515; CHECK-NEXT: ret516 %vc = shl <vscale x 4 x i64> %va, splat (i64 32)517 ret <vscale x 4 x i64> %vc518}519 520define <vscale x 4 x i64> @vshl_vx_nxv4i64_2(<vscale x 4 x i64> %va) {521; CHECK-LABEL: vshl_vx_nxv4i64_2:522; CHECK: # %bb.0:523; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma524; CHECK-NEXT: vadd.vv v8, v8, v8525; CHECK-NEXT: ret526 %vc = shl <vscale x 4 x i64> %va, splat (i64 1)527 ret <vscale x 4 x i64> %vc528}529 530define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {531; CHECK-LABEL: vshl_vx_nxv8i64:532; CHECK: # %bb.0:533; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma534; CHECK-NEXT: vsll.vx v8, v8, a0535; CHECK-NEXT: ret536 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0537 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer538 %vc = shl <vscale x 8 x i64> %va, %splat539 ret <vscale x 8 x i64> %vc540}541 542define <vscale x 8 x i64> @vshl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {543; CHECK-LABEL: vshl_vx_nxv8i64_0:544; CHECK: # %bb.0:545; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma546; CHECK-NEXT: vsll.vi v8, v8, 31547; CHECK-NEXT: ret548 %vc = shl <vscale x 8 x i64> %va, splat (i64 31)549 ret <vscale x 8 x i64> %vc550}551 552define <vscale x 8 x i64> @vshl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {553; CHECK-LABEL: vshl_vx_nxv8i64_1:554; CHECK: # %bb.0:555; CHECK-NEXT: li a0, 32556; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma557; CHECK-NEXT: vsll.vx v8, v8, a0558; CHECK-NEXT: ret559 %vc = shl <vscale x 8 x i64> %va, splat (i64 32)560 ret <vscale x 8 x i64> %vc561}562 563define <vscale x 8 x i64> @vshl_vx_nxv8i64_2(<vscale x 8 x i64> %va) {564; CHECK-LABEL: vshl_vx_nxv8i64_2:565; CHECK: # %bb.0:566; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma567; CHECK-NEXT: vadd.vv v8, v8, v8568; CHECK-NEXT: ret569 %vc = shl <vscale x 8 x i64> %va, splat (i64 1)570 ret <vscale x 8 x i64> %vc571}572 573define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {574; CHECK-LABEL: vshl_vv_mask_nxv4i32:575; CHECK: # %bb.0:576; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu577; CHECK-NEXT: vsll.vv v8, v8, v12, v0.t578; CHECK-NEXT: ret579 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer580 %vc = shl <vscale x 8 x i32> %va, %vs581 ret <vscale x 8 x i32> %vc582}583 584define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {585; CHECK-LABEL: vshl_vx_mask_nxv8i32:586; CHECK: # %bb.0:587; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu588; CHECK-NEXT: vsll.vx v8, v8, a0, v0.t589; CHECK-NEXT: ret590 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0591 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer592 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer593 %vc = shl <vscale x 8 x i32> %va, %vs594 ret <vscale x 8 x i32> %vc595}596 597define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {598; CHECK-LABEL: vshl_vi_mask_nxv8i32:599; CHECK: # %bb.0:600; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu601; CHECK-NEXT: vsll.vi v8, v8, 31, v0.t602; CHECK-NEXT: ret603 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 31), <vscale x 8 x i32> zeroinitializer604 %vc = shl <vscale x 8 x i32> %va, %vs605 ret <vscale x 8 x i32> %vc606}607