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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \4; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-128-655365 6; RUN: llc -mtriple=riscv32 -riscv-v-vector-bits-max=512 \7; RUN: -mattr=+v,+zvl512b -verify-machineinstrs \8; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-5129 10; RUN: llc -mtriple=riscv32 -riscv-v-vector-bits-max=64 \11; RUN: -mattr=+zve64x,+zvl64b -verify-machineinstrs \12; RUN: < %s | FileCheck %s --check-prefixes=CHECK,CHECK-6413 14define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl1(<vscale x 1 x i64> %0, i64 %1) nounwind {15; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl1:16; CHECK: # %bb.0: # %entry17; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma18; CHECK-NEXT: vslide1down.vx v8, v8, a019; CHECK-NEXT: vslide1down.vx v8, v8, a120; CHECK-NEXT: ret21entry:22 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(23 <vscale x 1 x i64> poison,24 <vscale x 1 x i64> %0,25 i64 %1,26 i32 1)27 28 ret <vscale x 1 x i64> %a29}30 31define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2(<vscale x 1 x i64> %0, i64 %1) nounwind {32; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2:33; CHECK-128-65536: # %bb.0: # %entry34; CHECK-128-65536-NEXT: vsetivli zero, 4, e32, m1, ta, ma35; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a036; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a137; CHECK-128-65536-NEXT: ret38;39; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2:40; CHECK-512: # %bb.0: # %entry41; CHECK-512-NEXT: vsetivli zero, 4, e32, m1, ta, ma42; CHECK-512-NEXT: vslide1down.vx v8, v8, a043; CHECK-512-NEXT: vslide1down.vx v8, v8, a144; CHECK-512-NEXT: ret45;46; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2:47; CHECK-64: # %bb.0: # %entry48; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma49; CHECK-64-NEXT: vslide1down.vx v8, v8, a050; CHECK-64-NEXT: vslide1down.vx v8, v8, a151; CHECK-64-NEXT: ret52entry:53 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(54 <vscale x 1 x i64> poison,55 <vscale x 1 x i64> %0,56 i64 %1,57 i32 2)58 59 ret <vscale x 1 x i64> %a60}61 62define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3(<vscale x 1 x i64> %0, i64 %1) nounwind {63; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:64; CHECK-128-65536: # %bb.0: # %entry65; CHECK-128-65536-NEXT: vsetivli a2, 3, e64, m1, ta, ma66; CHECK-128-65536-NEXT: slli a2, a2, 167; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma68; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a069; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a170; CHECK-128-65536-NEXT: ret71;72; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:73; CHECK-512: # %bb.0: # %entry74; CHECK-512-NEXT: vsetivli zero, 6, e32, m1, ta, ma75; CHECK-512-NEXT: vslide1down.vx v8, v8, a076; CHECK-512-NEXT: vslide1down.vx v8, v8, a177; CHECK-512-NEXT: ret78;79; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl3:80; CHECK-64: # %bb.0: # %entry81; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma82; CHECK-64-NEXT: vslide1down.vx v8, v8, a083; CHECK-64-NEXT: vslide1down.vx v8, v8, a184; CHECK-64-NEXT: ret85entry:86 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(87 <vscale x 1 x i64> poison,88 <vscale x 1 x i64> %0,89 i64 %1,90 i32 3)91 92 ret <vscale x 1 x i64> %a93}94 95define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8(<vscale x 1 x i64> %0, i64 %1) nounwind {96; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:97; CHECK-128-65536: # %bb.0: # %entry98; CHECK-128-65536-NEXT: vsetivli a2, 8, e64, m1, ta, ma99; CHECK-128-65536-NEXT: slli a2, a2, 1100; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma101; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0102; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1103; CHECK-128-65536-NEXT: ret104;105; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:106; CHECK-512: # %bb.0: # %entry107; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma108; CHECK-512-NEXT: vslide1down.vx v8, v8, a0109; CHECK-512-NEXT: vslide1down.vx v8, v8, a1110; CHECK-512-NEXT: ret111;112; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl8:113; CHECK-64: # %bb.0: # %entry114; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma115; CHECK-64-NEXT: vslide1down.vx v8, v8, a0116; CHECK-64-NEXT: vslide1down.vx v8, v8, a1117; CHECK-64-NEXT: ret118entry:119 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(120 <vscale x 1 x i64> poison,121 <vscale x 1 x i64> %0,122 i64 %1,123 i32 8)124 125 ret <vscale x 1 x i64> %a126}127 128define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9(<vscale x 1 x i64> %0, i64 %1) nounwind {129; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:130; CHECK-128-65536: # %bb.0: # %entry131; CHECK-128-65536-NEXT: vsetivli a2, 9, e64, m1, ta, ma132; CHECK-128-65536-NEXT: slli a2, a2, 1133; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma134; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0135; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1136; CHECK-128-65536-NEXT: ret137;138; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:139; CHECK-512: # %bb.0: # %entry140; CHECK-512-NEXT: vsetivli a2, 9, e64, m1, ta, ma141; CHECK-512-NEXT: slli a2, a2, 1142; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma143; CHECK-512-NEXT: vslide1down.vx v8, v8, a0144; CHECK-512-NEXT: vslide1down.vx v8, v8, a1145; CHECK-512-NEXT: ret146;147; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl9:148; CHECK-64: # %bb.0: # %entry149; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma150; CHECK-64-NEXT: vslide1down.vx v8, v8, a0151; CHECK-64-NEXT: vslide1down.vx v8, v8, a1152; CHECK-64-NEXT: ret153entry:154 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(155 <vscale x 1 x i64> poison,156 <vscale x 1 x i64> %0,157 i64 %1,158 i32 9)159 160 ret <vscale x 1 x i64> %a161}162 163define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15(<vscale x 1 x i64> %0, i64 %1) nounwind {164; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:165; CHECK-128-65536: # %bb.0: # %entry166; CHECK-128-65536-NEXT: vsetivli a2, 15, e64, m1, ta, ma167; CHECK-128-65536-NEXT: slli a2, a2, 1168; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma169; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0170; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1171; CHECK-128-65536-NEXT: ret172;173; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:174; CHECK-512: # %bb.0: # %entry175; CHECK-512-NEXT: vsetivli a2, 15, e64, m1, ta, ma176; CHECK-512-NEXT: slli a2, a2, 1177; CHECK-512-NEXT: vsetvli zero, a2, e32, m1, ta, ma178; CHECK-512-NEXT: vslide1down.vx v8, v8, a0179; CHECK-512-NEXT: vslide1down.vx v8, v8, a1180; CHECK-512-NEXT: ret181;182; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl15:183; CHECK-64: # %bb.0: # %entry184; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma185; CHECK-64-NEXT: vslide1down.vx v8, v8, a0186; CHECK-64-NEXT: vslide1down.vx v8, v8, a1187; CHECK-64-NEXT: ret188entry:189 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(190 <vscale x 1 x i64> poison,191 <vscale x 1 x i64> %0,192 i64 %1,193 i32 15)194 195 ret <vscale x 1 x i64> %a196}197 198define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16(<vscale x 1 x i64> %0, i64 %1) nounwind {199; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:200; CHECK-128-65536: # %bb.0: # %entry201; CHECK-128-65536-NEXT: vsetivli a2, 16, e64, m1, ta, ma202; CHECK-128-65536-NEXT: slli a2, a2, 1203; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma204; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0205; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1206; CHECK-128-65536-NEXT: ret207;208; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:209; CHECK-512: # %bb.0: # %entry210; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma211; CHECK-512-NEXT: vslide1down.vx v8, v8, a0212; CHECK-512-NEXT: vslide1down.vx v8, v8, a1213; CHECK-512-NEXT: ret214;215; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl16:216; CHECK-64: # %bb.0: # %entry217; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma218; CHECK-64-NEXT: vslide1down.vx v8, v8, a0219; CHECK-64-NEXT: vslide1down.vx v8, v8, a1220; CHECK-64-NEXT: ret221entry:222 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(223 <vscale x 1 x i64> poison,224 <vscale x 1 x i64> %0,225 i64 %1,226 i32 16)227 228 ret <vscale x 1 x i64> %a229}230 231define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047(<vscale x 1 x i64> %0, i64 %1) nounwind {232; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:233; CHECK-128-65536: # %bb.0: # %entry234; CHECK-128-65536-NEXT: li a2, 2047235; CHECK-128-65536-NEXT: vsetvli a2, a2, e64, m1, ta, ma236; CHECK-128-65536-NEXT: slli a2, a2, 1237; CHECK-128-65536-NEXT: vsetvli zero, a2, e32, m1, ta, ma238; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0239; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1240; CHECK-128-65536-NEXT: ret241;242; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:243; CHECK-512: # %bb.0: # %entry244; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma245; CHECK-512-NEXT: vslide1down.vx v8, v8, a0246; CHECK-512-NEXT: vslide1down.vx v8, v8, a1247; CHECK-512-NEXT: ret248;249; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2047:250; CHECK-64: # %bb.0: # %entry251; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma252; CHECK-64-NEXT: vslide1down.vx v8, v8, a0253; CHECK-64-NEXT: vslide1down.vx v8, v8, a1254; CHECK-64-NEXT: ret255entry:256 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(257 <vscale x 1 x i64> poison,258 <vscale x 1 x i64> %0,259 i64 %1,260 i32 2047)261 262 ret <vscale x 1 x i64> %a263}264 265define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048(<vscale x 1 x i64> %0, i64 %1) nounwind {266; CHECK-128-65536-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048:267; CHECK-128-65536: # %bb.0: # %entry268; CHECK-128-65536-NEXT: vsetvli a2, zero, e32, m1, ta, ma269; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a0270; CHECK-128-65536-NEXT: vslide1down.vx v8, v8, a1271; CHECK-128-65536-NEXT: ret272;273; CHECK-512-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048:274; CHECK-512: # %bb.0: # %entry275; CHECK-512-NEXT: vsetivli zero, 16, e32, m1, ta, ma276; CHECK-512-NEXT: vslide1down.vx v8, v8, a0277; CHECK-512-NEXT: vslide1down.vx v8, v8, a1278; CHECK-512-NEXT: ret279;280; CHECK-64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64_vl2048:281; CHECK-64: # %bb.0: # %entry282; CHECK-64-NEXT: vsetivli zero, 2, e32, m1, ta, ma283; CHECK-64-NEXT: vslide1down.vx v8, v8, a0284; CHECK-64-NEXT: vslide1down.vx v8, v8, a1285; CHECK-64-NEXT: ret286entry:287 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(288 <vscale x 1 x i64> poison,289 <vscale x 1 x i64> %0,290 i64 %1,291 i32 2048)292 293 ret <vscale x 1 x i64> %a294}295