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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vslide1down.vx v8, v8, a012; CHECK-NEXT: ret13entry:14 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(15 <vscale x 1 x i8> poison,16 <vscale x 1 x i8> %0,17 i8 %1,18 iXLen %2)19 20 ret <vscale x 1 x i8> %a21}22 23define <vscale x 1 x i8> @intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {24; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu27; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t28; CHECK-NEXT: ret29entry:30 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(31 <vscale x 1 x i8> %0,32 <vscale x 1 x i8> %1,33 i8 %2,34 <vscale x 1 x i1> %3,35 iXLen %4, iXLen 1)36 37 ret <vscale x 1 x i8> %a38}39 40define <vscale x 2 x i8> @intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma44; CHECK-NEXT: vslide1down.vx v8, v8, a045; CHECK-NEXT: ret46entry:47 %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(48 <vscale x 2 x i8> poison,49 <vscale x 2 x i8> %0,50 i8 %1,51 iXLen %2)52 53 ret <vscale x 2 x i8> %a54}55 56define <vscale x 2 x i8> @intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {57; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu60; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t61; CHECK-NEXT: ret62entry:63 %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(64 <vscale x 2 x i8> %0,65 <vscale x 2 x i8> %1,66 i8 %2,67 <vscale x 2 x i1> %3,68 iXLen %4, iXLen 1)69 70 ret <vscale x 2 x i8> %a71}72 73define <vscale x 4 x i8> @intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma77; CHECK-NEXT: vslide1down.vx v8, v8, a078; CHECK-NEXT: ret79entry:80 %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(81 <vscale x 4 x i8> poison,82 <vscale x 4 x i8> %0,83 i8 %1,84 iXLen %2)85 86 ret <vscale x 4 x i8> %a87}88 89define <vscale x 4 x i8> @intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {90; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu93; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t94; CHECK-NEXT: ret95entry:96 %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(97 <vscale x 4 x i8> %0,98 <vscale x 4 x i8> %1,99 i8 %2,100 <vscale x 4 x i1> %3,101 iXLen %4, iXLen 1)102 103 ret <vscale x 4 x i8> %a104}105 106define <vscale x 8 x i8> @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {107; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma110; CHECK-NEXT: vslide1down.vx v8, v8, a0111; CHECK-NEXT: ret112entry:113 %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(114 <vscale x 8 x i8> poison,115 <vscale x 8 x i8> %0,116 i8 %1,117 iXLen %2)118 119 ret <vscale x 8 x i8> %a120}121 122define <vscale x 8 x i8> @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {123; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu126; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t127; CHECK-NEXT: ret128entry:129 %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(130 <vscale x 8 x i8> %0,131 <vscale x 8 x i8> %1,132 i8 %2,133 <vscale x 8 x i1> %3,134 iXLen %4, iXLen 1)135 136 ret <vscale x 8 x i8> %a137}138 139define <vscale x 16 x i8> @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {140; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma143; CHECK-NEXT: vslide1down.vx v8, v8, a0144; CHECK-NEXT: ret145entry:146 %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(147 <vscale x 16 x i8> poison,148 <vscale x 16 x i8> %0,149 i8 %1,150 iXLen %2)151 152 ret <vscale x 16 x i8> %a153}154 155define <vscale x 16 x i8> @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {156; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu159; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t160; CHECK-NEXT: ret161entry:162 %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(163 <vscale x 16 x i8> %0,164 <vscale x 16 x i8> %1,165 i8 %2,166 <vscale x 16 x i1> %3,167 iXLen %4, iXLen 1)168 169 ret <vscale x 16 x i8> %a170}171 172define <vscale x 32 x i8> @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {173; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma176; CHECK-NEXT: vslide1down.vx v8, v8, a0177; CHECK-NEXT: ret178entry:179 %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(180 <vscale x 32 x i8> poison,181 <vscale x 32 x i8> %0,182 i8 %1,183 iXLen %2)184 185 ret <vscale x 32 x i8> %a186}187 188define <vscale x 32 x i8> @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {189; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu192; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t193; CHECK-NEXT: ret194entry:195 %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(196 <vscale x 32 x i8> %0,197 <vscale x 32 x i8> %1,198 i8 %2,199 <vscale x 32 x i1> %3,200 iXLen %4, iXLen 1)201 202 ret <vscale x 32 x i8> %a203}204 205define <vscale x 64 x i8> @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {206; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma209; CHECK-NEXT: vslide1down.vx v8, v8, a0210; CHECK-NEXT: ret211entry:212 %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(213 <vscale x 64 x i8> poison,214 <vscale x 64 x i8> %0,215 i8 %1,216 iXLen %2)217 218 ret <vscale x 64 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {222; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu225; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t226; CHECK-NEXT: ret227entry:228 %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(229 <vscale x 64 x i8> %0,230 <vscale x 64 x i8> %1,231 i8 %2,232 <vscale x 64 x i1> %3,233 iXLen %4, iXLen 1)234 235 ret <vscale x 64 x i8> %a236}237 238define <vscale x 1 x i16> @intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {239; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma242; CHECK-NEXT: vslide1down.vx v8, v8, a0243; CHECK-NEXT: ret244entry:245 %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(246 <vscale x 1 x i16> poison,247 <vscale x 1 x i16> %0,248 i16 %1,249 iXLen %2)250 251 ret <vscale x 1 x i16> %a252}253 254define <vscale x 1 x i16> @intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {255; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu258; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t259; CHECK-NEXT: ret260entry:261 %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(262 <vscale x 1 x i16> %0,263 <vscale x 1 x i16> %1,264 i16 %2,265 <vscale x 1 x i1> %3,266 iXLen %4, iXLen 1)267 268 ret <vscale x 1 x i16> %a269}270 271define <vscale x 2 x i16> @intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {272; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma275; CHECK-NEXT: vslide1down.vx v8, v8, a0276; CHECK-NEXT: ret277entry:278 %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(279 <vscale x 2 x i16> poison,280 <vscale x 2 x i16> %0,281 i16 %1,282 iXLen %2)283 284 ret <vscale x 2 x i16> %a285}286 287define <vscale x 2 x i16> @intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {288; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu291; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t292; CHECK-NEXT: ret293entry:294 %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(295 <vscale x 2 x i16> %0,296 <vscale x 2 x i16> %1,297 i16 %2,298 <vscale x 2 x i1> %3,299 iXLen %4, iXLen 1)300 301 ret <vscale x 2 x i16> %a302}303 304define <vscale x 4 x i16> @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {305; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma308; CHECK-NEXT: vslide1down.vx v8, v8, a0309; CHECK-NEXT: ret310entry:311 %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(312 <vscale x 4 x i16> poison,313 <vscale x 4 x i16> %0,314 i16 %1,315 iXLen %2)316 317 ret <vscale x 4 x i16> %a318}319 320define <vscale x 4 x i16> @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {321; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu324; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t325; CHECK-NEXT: ret326entry:327 %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(328 <vscale x 4 x i16> %0,329 <vscale x 4 x i16> %1,330 i16 %2,331 <vscale x 4 x i1> %3,332 iXLen %4, iXLen 1)333 334 ret <vscale x 4 x i16> %a335}336 337define <vscale x 8 x i16> @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {338; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma341; CHECK-NEXT: vslide1down.vx v8, v8, a0342; CHECK-NEXT: ret343entry:344 %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(345 <vscale x 8 x i16> poison,346 <vscale x 8 x i16> %0,347 i16 %1,348 iXLen %2)349 350 ret <vscale x 8 x i16> %a351}352 353define <vscale x 8 x i16> @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {354; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu357; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t358; CHECK-NEXT: ret359entry:360 %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(361 <vscale x 8 x i16> %0,362 <vscale x 8 x i16> %1,363 i16 %2,364 <vscale x 8 x i1> %3,365 iXLen %4, iXLen 1)366 367 ret <vscale x 8 x i16> %a368}369 370define <vscale x 16 x i16> @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {371; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma374; CHECK-NEXT: vslide1down.vx v8, v8, a0375; CHECK-NEXT: ret376entry:377 %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(378 <vscale x 16 x i16> poison,379 <vscale x 16 x i16> %0,380 i16 %1,381 iXLen %2)382 383 ret <vscale x 16 x i16> %a384}385 386define <vscale x 16 x i16> @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {387; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu390; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t391; CHECK-NEXT: ret392entry:393 %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(394 <vscale x 16 x i16> %0,395 <vscale x 16 x i16> %1,396 i16 %2,397 <vscale x 16 x i1> %3,398 iXLen %4, iXLen 1)399 400 ret <vscale x 16 x i16> %a401}402 403define <vscale x 32 x i16> @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {404; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma407; CHECK-NEXT: vslide1down.vx v8, v8, a0408; CHECK-NEXT: ret409entry:410 %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(411 <vscale x 32 x i16> poison,412 <vscale x 32 x i16> %0,413 i16 %1,414 iXLen %2)415 416 ret <vscale x 32 x i16> %a417}418 419define <vscale x 32 x i16> @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {420; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu423; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t424; CHECK-NEXT: ret425entry:426 %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(427 <vscale x 32 x i16> %0,428 <vscale x 32 x i16> %1,429 i16 %2,430 <vscale x 32 x i1> %3,431 iXLen %4, iXLen 1)432 433 ret <vscale x 32 x i16> %a434}435 436define <vscale x 1 x i32> @intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {437; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma440; CHECK-NEXT: vslide1down.vx v8, v8, a0441; CHECK-NEXT: ret442entry:443 %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(444 <vscale x 1 x i32> poison,445 <vscale x 1 x i32> %0,446 i32 %1,447 iXLen %2)448 449 ret <vscale x 1 x i32> %a450}451 452define <vscale x 1 x i32> @intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {453; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu456; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t457; CHECK-NEXT: ret458entry:459 %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(460 <vscale x 1 x i32> %0,461 <vscale x 1 x i32> %1,462 i32 %2,463 <vscale x 1 x i1> %3,464 iXLen %4, iXLen 1)465 466 ret <vscale x 1 x i32> %a467}468 469define <vscale x 2 x i32> @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {470; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma473; CHECK-NEXT: vslide1down.vx v8, v8, a0474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(477 <vscale x 2 x i32> poison,478 <vscale x 2 x i32> %0,479 i32 %1,480 iXLen %2)481 482 ret <vscale x 2 x i32> %a483}484 485define <vscale x 2 x i32> @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu489; CHECK-NEXT: vslide1down.vx v8, v9, a0, v0.t490; CHECK-NEXT: ret491entry:492 %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(493 <vscale x 2 x i32> %0,494 <vscale x 2 x i32> %1,495 i32 %2,496 <vscale x 2 x i1> %3,497 iXLen %4, iXLen 1)498 499 ret <vscale x 2 x i32> %a500}501 502define <vscale x 4 x i32> @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {503; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma506; CHECK-NEXT: vslide1down.vx v8, v8, a0507; CHECK-NEXT: ret508entry:509 %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(510 <vscale x 4 x i32> poison,511 <vscale x 4 x i32> %0,512 i32 %1,513 iXLen %2)514 515 ret <vscale x 4 x i32> %a516}517 518define <vscale x 4 x i32> @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {519; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu522; CHECK-NEXT: vslide1down.vx v8, v10, a0, v0.t523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(526 <vscale x 4 x i32> %0,527 <vscale x 4 x i32> %1,528 i32 %2,529 <vscale x 4 x i1> %3,530 iXLen %4, iXLen 1)531 532 ret <vscale x 4 x i32> %a533}534 535define <vscale x 8 x i32> @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {536; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma539; CHECK-NEXT: vslide1down.vx v8, v8, a0540; CHECK-NEXT: ret541entry:542 %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(543 <vscale x 8 x i32> poison,544 <vscale x 8 x i32> %0,545 i32 %1,546 iXLen %2)547 548 ret <vscale x 8 x i32> %a549}550 551define <vscale x 8 x i32> @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {552; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu555; CHECK-NEXT: vslide1down.vx v8, v12, a0, v0.t556; CHECK-NEXT: ret557entry:558 %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(559 <vscale x 8 x i32> %0,560 <vscale x 8 x i32> %1,561 i32 %2,562 <vscale x 8 x i1> %3,563 iXLen %4, iXLen 1)564 565 ret <vscale x 8 x i32> %a566}567 568define <vscale x 16 x i32> @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {569; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma572; CHECK-NEXT: vslide1down.vx v8, v8, a0573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(576 <vscale x 16 x i32> poison,577 <vscale x 16 x i32> %0,578 i32 %1,579 iXLen %2)580 581 ret <vscale x 16 x i32> %a582}583 584define <vscale x 16 x i32> @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {585; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu588; CHECK-NEXT: vslide1down.vx v8, v16, a0, v0.t589; CHECK-NEXT: ret590entry:591 %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(592 <vscale x 16 x i32> %0,593 <vscale x 16 x i32> %1,594 i32 %2,595 <vscale x 16 x i1> %3,596 iXLen %4, iXLen 1)597 598 ret <vscale x 16 x i32> %a599}600 601define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {602; RV32-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:603; RV32: # %bb.0: # %entry604; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma605; RV32-NEXT: slli a2, a2, 1606; RV32-NEXT: vsetvli zero, a2, e32, m1, ta, ma607; RV32-NEXT: vslide1down.vx v8, v8, a0608; RV32-NEXT: vslide1down.vx v8, v8, a1609; RV32-NEXT: ret610;611; RV64-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:612; RV64: # %bb.0: # %entry613; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma614; RV64-NEXT: vslide1down.vx v8, v8, a0615; RV64-NEXT: ret616entry:617 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(618 <vscale x 1 x i64> poison,619 <vscale x 1 x i64> %0,620 i64 %1,621 iXLen %2)622 623 ret <vscale x 1 x i64> %a624}625 626define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {627; RV32-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64:628; RV32: # %bb.0: # %entry629; RV32-NEXT: vsetvli a3, a2, e64, m1, ta, ma630; RV32-NEXT: slli a3, a3, 1631; RV32-NEXT: vsetvli zero, a3, e32, m1, ta, ma632; RV32-NEXT: vslide1down.vx v9, v9, a0633; RV32-NEXT: vslide1down.vx v9, v9, a1634; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma635; RV32-NEXT: vmerge.vvm v8, v8, v9, v0636; RV32-NEXT: ret637;638; RV64-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64:639; RV64: # %bb.0: # %entry640; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu641; RV64-NEXT: vslide1down.vx v8, v9, a0, v0.t642; RV64-NEXT: ret643entry:644 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(645 <vscale x 1 x i64> %0,646 <vscale x 1 x i64> %1,647 i64 %2,648 <vscale x 1 x i1> %3,649 iXLen %4, iXLen 1)650 651 ret <vscale x 1 x i64> %a652}653 654define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {655; RV32-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64:656; RV32: # %bb.0: # %entry657; RV32-NEXT: vsetvli a2, a2, e64, m2, ta, ma658; RV32-NEXT: slli a2, a2, 1659; RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma660; RV32-NEXT: vslide1down.vx v8, v8, a0661; RV32-NEXT: vslide1down.vx v8, v8, a1662; RV32-NEXT: ret663;664; RV64-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64:665; RV64: # %bb.0: # %entry666; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma667; RV64-NEXT: vslide1down.vx v8, v8, a0668; RV64-NEXT: ret669entry:670 %a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(671 <vscale x 2 x i64> poison,672 <vscale x 2 x i64> %0,673 i64 %1,674 iXLen %2)675 676 ret <vscale x 2 x i64> %a677}678 679define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {680; RV32-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64:681; RV32: # %bb.0: # %entry682; RV32-NEXT: vsetvli a3, a2, e64, m2, ta, ma683; RV32-NEXT: slli a3, a3, 1684; RV32-NEXT: vsetvli zero, a3, e32, m2, ta, ma685; RV32-NEXT: vslide1down.vx v10, v10, a0686; RV32-NEXT: vslide1down.vx v10, v10, a1687; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma688; RV32-NEXT: vmerge.vvm v8, v8, v10, v0689; RV32-NEXT: ret690;691; RV64-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64:692; RV64: # %bb.0: # %entry693; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu694; RV64-NEXT: vslide1down.vx v8, v10, a0, v0.t695; RV64-NEXT: ret696entry:697 %a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(698 <vscale x 2 x i64> %0,699 <vscale x 2 x i64> %1,700 i64 %2,701 <vscale x 2 x i1> %3,702 iXLen %4, iXLen 1)703 704 ret <vscale x 2 x i64> %a705}706 707define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {708; RV32-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64:709; RV32: # %bb.0: # %entry710; RV32-NEXT: vsetvli a2, a2, e64, m4, ta, ma711; RV32-NEXT: slli a2, a2, 1712; RV32-NEXT: vsetvli zero, a2, e32, m4, ta, ma713; RV32-NEXT: vslide1down.vx v8, v8, a0714; RV32-NEXT: vslide1down.vx v8, v8, a1715; RV32-NEXT: ret716;717; RV64-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64:718; RV64: # %bb.0: # %entry719; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma720; RV64-NEXT: vslide1down.vx v8, v8, a0721; RV64-NEXT: ret722entry:723 %a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(724 <vscale x 4 x i64> poison,725 <vscale x 4 x i64> %0,726 i64 %1,727 iXLen %2)728 729 ret <vscale x 4 x i64> %a730}731 732define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {733; RV32-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64:734; RV32: # %bb.0: # %entry735; RV32-NEXT: vsetvli a3, a2, e64, m4, ta, ma736; RV32-NEXT: slli a3, a3, 1737; RV32-NEXT: vsetvli zero, a3, e32, m4, ta, ma738; RV32-NEXT: vslide1down.vx v12, v12, a0739; RV32-NEXT: vslide1down.vx v12, v12, a1740; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma741; RV32-NEXT: vmerge.vvm v8, v8, v12, v0742; RV32-NEXT: ret743;744; RV64-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64:745; RV64: # %bb.0: # %entry746; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu747; RV64-NEXT: vslide1down.vx v8, v12, a0, v0.t748; RV64-NEXT: ret749entry:750 %a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(751 <vscale x 4 x i64> %0,752 <vscale x 4 x i64> %1,753 i64 %2,754 <vscale x 4 x i1> %3,755 iXLen %4, iXLen 1)756 757 ret <vscale x 4 x i64> %a758}759 760define <vscale x 8 x i64> @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {761; RV32-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64:762; RV32: # %bb.0: # %entry763; RV32-NEXT: vsetvli a2, a2, e64, m8, ta, ma764; RV32-NEXT: slli a2, a2, 1765; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma766; RV32-NEXT: vslide1down.vx v8, v8, a0767; RV32-NEXT: vslide1down.vx v8, v8, a1768; RV32-NEXT: ret769;770; RV64-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64:771; RV64: # %bb.0: # %entry772; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma773; RV64-NEXT: vslide1down.vx v8, v8, a0774; RV64-NEXT: ret775entry:776 %a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(777 <vscale x 8 x i64> poison,778 <vscale x 8 x i64> %0,779 i64 %1,780 iXLen %2)781 782 ret <vscale x 8 x i64> %a783}784 785define <vscale x 8 x i64> @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {786; RV32-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64:787; RV32: # %bb.0: # %entry788; RV32-NEXT: vsetvli a3, a2, e64, m8, ta, ma789; RV32-NEXT: slli a3, a3, 1790; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma791; RV32-NEXT: vslide1down.vx v16, v16, a0792; RV32-NEXT: vslide1down.vx v16, v16, a1793; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma794; RV32-NEXT: vmerge.vvm v8, v8, v16, v0795; RV32-NEXT: ret796;797; RV64-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64:798; RV64: # %bb.0: # %entry799; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu800; RV64-NEXT: vslide1down.vx v8, v16, a0, v0.t801; RV64-NEXT: ret802entry:803 %a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(804 <vscale x 8 x i64> %0,805 <vscale x 8 x i64> %1,806 i64 %2,807 <vscale x 8 x i1> %3,808 iXLen %4, iXLen 1)809 810 ret <vscale x 8 x i64> %a811}812