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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vslide1up.vx v9, v8, a012; CHECK-NEXT: vmv1r.v v8, v913; CHECK-NEXT: ret14entry:15 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(16 <vscale x 1 x i8> poison,17 <vscale x 1 x i8> %0,18 i8 %1,19 iXLen %2)20 21 ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8:26; CHECK: # %bb.0: # %entry27; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu28; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t29; CHECK-NEXT: ret30entry:31 %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(32 <vscale x 1 x i8> %0,33 <vscale x 1 x i8> %1,34 i8 %2,35 <vscale x 1 x i1> %3,36 iXLen %4, iXLen 1)37 38 ret <vscale x 1 x i8> %a39}40 41define <vscale x 2 x i8> @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8:43; CHECK: # %bb.0: # %entry44; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma45; CHECK-NEXT: vslide1up.vx v9, v8, a046; CHECK-NEXT: vmv1r.v v8, v947; CHECK-NEXT: ret48entry:49 %a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(50 <vscale x 2 x i8> poison,51 <vscale x 2 x i8> %0,52 i8 %1,53 iXLen %2)54 55 ret <vscale x 2 x i8> %a56}57 58define <vscale x 2 x i8> @intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {59; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8:60; CHECK: # %bb.0: # %entry61; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu62; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t63; CHECK-NEXT: ret64entry:65 %a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8(66 <vscale x 2 x i8> %0,67 <vscale x 2 x i8> %1,68 i8 %2,69 <vscale x 2 x i1> %3,70 iXLen %4, iXLen 1)71 72 ret <vscale x 2 x i8> %a73}74 75define <vscale x 4 x i8> @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {76; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8:77; CHECK: # %bb.0: # %entry78; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma79; CHECK-NEXT: vslide1up.vx v9, v8, a080; CHECK-NEXT: vmv1r.v v8, v981; CHECK-NEXT: ret82entry:83 %a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(84 <vscale x 4 x i8> poison,85 <vscale x 4 x i8> %0,86 i8 %1,87 iXLen %2)88 89 ret <vscale x 4 x i8> %a90}91 92define <vscale x 4 x i8> @intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8:94; CHECK: # %bb.0: # %entry95; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu96; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t97; CHECK-NEXT: ret98entry:99 %a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8(100 <vscale x 4 x i8> %0,101 <vscale x 4 x i8> %1,102 i8 %2,103 <vscale x 4 x i1> %3,104 iXLen %4, iXLen 1)105 106 ret <vscale x 4 x i8> %a107}108 109define <vscale x 8 x i8> @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8:111; CHECK: # %bb.0: # %entry112; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma113; CHECK-NEXT: vslide1up.vx v9, v8, a0114; CHECK-NEXT: vmv.v.v v8, v9115; CHECK-NEXT: ret116entry:117 %a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(118 <vscale x 8 x i8> poison,119 <vscale x 8 x i8> %0,120 i8 %1,121 iXLen %2)122 123 ret <vscale x 8 x i8> %a124}125 126define <vscale x 8 x i8> @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {127; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8:128; CHECK: # %bb.0: # %entry129; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu130; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t131; CHECK-NEXT: ret132entry:133 %a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8(134 <vscale x 8 x i8> %0,135 <vscale x 8 x i8> %1,136 i8 %2,137 <vscale x 8 x i1> %3,138 iXLen %4, iXLen 1)139 140 ret <vscale x 8 x i8> %a141}142 143define <vscale x 16 x i8> @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {144; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8:145; CHECK: # %bb.0: # %entry146; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma147; CHECK-NEXT: vslide1up.vx v10, v8, a0148; CHECK-NEXT: vmv.v.v v8, v10149; CHECK-NEXT: ret150entry:151 %a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(152 <vscale x 16 x i8> poison,153 <vscale x 16 x i8> %0,154 i8 %1,155 iXLen %2)156 157 ret <vscale x 16 x i8> %a158}159 160define <vscale x 16 x i8> @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8:162; CHECK: # %bb.0: # %entry163; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu164; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t165; CHECK-NEXT: ret166entry:167 %a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8(168 <vscale x 16 x i8> %0,169 <vscale x 16 x i8> %1,170 i8 %2,171 <vscale x 16 x i1> %3,172 iXLen %4, iXLen 1)173 174 ret <vscale x 16 x i8> %a175}176 177define <vscale x 32 x i8> @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8:179; CHECK: # %bb.0: # %entry180; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma181; CHECK-NEXT: vslide1up.vx v12, v8, a0182; CHECK-NEXT: vmv.v.v v8, v12183; CHECK-NEXT: ret184entry:185 %a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(186 <vscale x 32 x i8> poison,187 <vscale x 32 x i8> %0,188 i8 %1,189 iXLen %2)190 191 ret <vscale x 32 x i8> %a192}193 194define <vscale x 32 x i8> @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {195; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8:196; CHECK: # %bb.0: # %entry197; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu198; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t199; CHECK-NEXT: ret200entry:201 %a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8(202 <vscale x 32 x i8> %0,203 <vscale x 32 x i8> %1,204 i8 %2,205 <vscale x 32 x i1> %3,206 iXLen %4, iXLen 1)207 208 ret <vscale x 32 x i8> %a209}210 211define <vscale x 64 x i8> @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {212; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8:213; CHECK: # %bb.0: # %entry214; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma215; CHECK-NEXT: vslide1up.vx v16, v8, a0216; CHECK-NEXT: vmv.v.v v8, v16217; CHECK-NEXT: ret218entry:219 %a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8(220 <vscale x 64 x i8> poison,221 <vscale x 64 x i8> %0,222 i8 %1,223 iXLen %2)224 225 ret <vscale x 64 x i8> %a226}227 228define <vscale x 64 x i8> @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8:230; CHECK: # %bb.0: # %entry231; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu232; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t233; CHECK-NEXT: ret234entry:235 %a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8(236 <vscale x 64 x i8> %0,237 <vscale x 64 x i8> %1,238 i8 %2,239 <vscale x 64 x i1> %3,240 iXLen %4, iXLen 1)241 242 ret <vscale x 64 x i8> %a243}244 245define <vscale x 1 x i16> @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16:247; CHECK: # %bb.0: # %entry248; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma249; CHECK-NEXT: vslide1up.vx v9, v8, a0250; CHECK-NEXT: vmv1r.v v8, v9251; CHECK-NEXT: ret252entry:253 %a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(254 <vscale x 1 x i16> poison,255 <vscale x 1 x i16> %0,256 i16 %1,257 iXLen %2)258 259 ret <vscale x 1 x i16> %a260}261 262define <vscale x 1 x i16> @intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {263; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16:264; CHECK: # %bb.0: # %entry265; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu266; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t267; CHECK-NEXT: ret268entry:269 %a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16(270 <vscale x 1 x i16> %0,271 <vscale x 1 x i16> %1,272 i16 %2,273 <vscale x 1 x i1> %3,274 iXLen %4, iXLen 1)275 276 ret <vscale x 1 x i16> %a277}278 279define <vscale x 2 x i16> @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {280; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16:281; CHECK: # %bb.0: # %entry282; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma283; CHECK-NEXT: vslide1up.vx v9, v8, a0284; CHECK-NEXT: vmv1r.v v8, v9285; CHECK-NEXT: ret286entry:287 %a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(288 <vscale x 2 x i16> poison,289 <vscale x 2 x i16> %0,290 i16 %1,291 iXLen %2)292 293 ret <vscale x 2 x i16> %a294}295 296define <vscale x 2 x i16> @intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16:298; CHECK: # %bb.0: # %entry299; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu300; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t301; CHECK-NEXT: ret302entry:303 %a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16(304 <vscale x 2 x i16> %0,305 <vscale x 2 x i16> %1,306 i16 %2,307 <vscale x 2 x i1> %3,308 iXLen %4, iXLen 1)309 310 ret <vscale x 2 x i16> %a311}312 313define <vscale x 4 x i16> @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16:315; CHECK: # %bb.0: # %entry316; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma317; CHECK-NEXT: vslide1up.vx v9, v8, a0318; CHECK-NEXT: vmv.v.v v8, v9319; CHECK-NEXT: ret320entry:321 %a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(322 <vscale x 4 x i16> poison,323 <vscale x 4 x i16> %0,324 i16 %1,325 iXLen %2)326 327 ret <vscale x 4 x i16> %a328}329 330define <vscale x 4 x i16> @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {331; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16:332; CHECK: # %bb.0: # %entry333; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu334; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t335; CHECK-NEXT: ret336entry:337 %a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16(338 <vscale x 4 x i16> %0,339 <vscale x 4 x i16> %1,340 i16 %2,341 <vscale x 4 x i1> %3,342 iXLen %4, iXLen 1)343 344 ret <vscale x 4 x i16> %a345}346 347define <vscale x 8 x i16> @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {348; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16:349; CHECK: # %bb.0: # %entry350; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma351; CHECK-NEXT: vslide1up.vx v10, v8, a0352; CHECK-NEXT: vmv.v.v v8, v10353; CHECK-NEXT: ret354entry:355 %a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(356 <vscale x 8 x i16> poison,357 <vscale x 8 x i16> %0,358 i16 %1,359 iXLen %2)360 361 ret <vscale x 8 x i16> %a362}363 364define <vscale x 8 x i16> @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {365; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16:366; CHECK: # %bb.0: # %entry367; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu368; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t369; CHECK-NEXT: ret370entry:371 %a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16(372 <vscale x 8 x i16> %0,373 <vscale x 8 x i16> %1,374 i16 %2,375 <vscale x 8 x i1> %3,376 iXLen %4, iXLen 1)377 378 ret <vscale x 8 x i16> %a379}380 381define <vscale x 16 x i16> @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {382; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16:383; CHECK: # %bb.0: # %entry384; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma385; CHECK-NEXT: vslide1up.vx v12, v8, a0386; CHECK-NEXT: vmv.v.v v8, v12387; CHECK-NEXT: ret388entry:389 %a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(390 <vscale x 16 x i16> poison,391 <vscale x 16 x i16> %0,392 i16 %1,393 iXLen %2)394 395 ret <vscale x 16 x i16> %a396}397 398define <vscale x 16 x i16> @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {399; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16:400; CHECK: # %bb.0: # %entry401; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu402; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16(406 <vscale x 16 x i16> %0,407 <vscale x 16 x i16> %1,408 i16 %2,409 <vscale x 16 x i1> %3,410 iXLen %4, iXLen 1)411 412 ret <vscale x 16 x i16> %a413}414 415define <vscale x 32 x i16> @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {416; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16:417; CHECK: # %bb.0: # %entry418; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma419; CHECK-NEXT: vslide1up.vx v16, v8, a0420; CHECK-NEXT: vmv.v.v v8, v16421; CHECK-NEXT: ret422entry:423 %a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16(424 <vscale x 32 x i16> poison,425 <vscale x 32 x i16> %0,426 i16 %1,427 iXLen %2)428 429 ret <vscale x 32 x i16> %a430}431 432define <vscale x 32 x i16> @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {433; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu436; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t437; CHECK-NEXT: ret438entry:439 %a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16(440 <vscale x 32 x i16> %0,441 <vscale x 32 x i16> %1,442 i16 %2,443 <vscale x 32 x i1> %3,444 iXLen %4, iXLen 1)445 446 ret <vscale x 32 x i16> %a447}448 449define <vscale x 1 x i32> @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {450; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma453; CHECK-NEXT: vslide1up.vx v9, v8, a0454; CHECK-NEXT: vmv1r.v v8, v9455; CHECK-NEXT: ret456entry:457 %a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(458 <vscale x 1 x i32> poison,459 <vscale x 1 x i32> %0,460 i32 %1,461 iXLen %2)462 463 ret <vscale x 1 x i32> %a464}465 466define <vscale x 1 x i32> @intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {467; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32:468; CHECK: # %bb.0: # %entry469; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu470; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t471; CHECK-NEXT: ret472entry:473 %a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32(474 <vscale x 1 x i32> %0,475 <vscale x 1 x i32> %1,476 i32 %2,477 <vscale x 1 x i1> %3,478 iXLen %4, iXLen 1)479 480 ret <vscale x 1 x i32> %a481}482 483define <vscale x 2 x i32> @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {484; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32:485; CHECK: # %bb.0: # %entry486; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma487; CHECK-NEXT: vslide1up.vx v9, v8, a0488; CHECK-NEXT: vmv.v.v v8, v9489; CHECK-NEXT: ret490entry:491 %a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(492 <vscale x 2 x i32> poison,493 <vscale x 2 x i32> %0,494 i32 %1,495 iXLen %2)496 497 ret <vscale x 2 x i32> %a498}499 500define <vscale x 2 x i32> @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {501; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32:502; CHECK: # %bb.0: # %entry503; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu504; CHECK-NEXT: vslide1up.vx v8, v9, a0, v0.t505; CHECK-NEXT: ret506entry:507 %a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32(508 <vscale x 2 x i32> %0,509 <vscale x 2 x i32> %1,510 i32 %2,511 <vscale x 2 x i1> %3,512 iXLen %4, iXLen 1)513 514 ret <vscale x 2 x i32> %a515}516 517define <vscale x 4 x i32> @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {518; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32:519; CHECK: # %bb.0: # %entry520; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma521; CHECK-NEXT: vslide1up.vx v10, v8, a0522; CHECK-NEXT: vmv.v.v v8, v10523; CHECK-NEXT: ret524entry:525 %a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(526 <vscale x 4 x i32> poison,527 <vscale x 4 x i32> %0,528 i32 %1,529 iXLen %2)530 531 ret <vscale x 4 x i32> %a532}533 534define <vscale x 4 x i32> @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {535; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32:536; CHECK: # %bb.0: # %entry537; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu538; CHECK-NEXT: vslide1up.vx v8, v10, a0, v0.t539; CHECK-NEXT: ret540entry:541 %a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32(542 <vscale x 4 x i32> %0,543 <vscale x 4 x i32> %1,544 i32 %2,545 <vscale x 4 x i1> %3,546 iXLen %4, iXLen 1)547 548 ret <vscale x 4 x i32> %a549}550 551define <vscale x 8 x i32> @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {552; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma555; CHECK-NEXT: vslide1up.vx v12, v8, a0556; CHECK-NEXT: vmv.v.v v8, v12557; CHECK-NEXT: ret558entry:559 %a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(560 <vscale x 8 x i32> poison,561 <vscale x 8 x i32> %0,562 i32 %1,563 iXLen %2)564 565 ret <vscale x 8 x i32> %a566}567 568define <vscale x 8 x i32> @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu572; CHECK-NEXT: vslide1up.vx v8, v12, a0, v0.t573; CHECK-NEXT: ret574entry:575 %a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32(576 <vscale x 8 x i32> %0,577 <vscale x 8 x i32> %1,578 i32 %2,579 <vscale x 8 x i1> %3,580 iXLen %4, iXLen 1)581 582 ret <vscale x 8 x i32> %a583}584 585define <vscale x 16 x i32> @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {586; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32:587; CHECK: # %bb.0: # %entry588; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma589; CHECK-NEXT: vslide1up.vx v16, v8, a0590; CHECK-NEXT: vmv.v.v v8, v16591; CHECK-NEXT: ret592entry:593 %a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32(594 <vscale x 16 x i32> poison,595 <vscale x 16 x i32> %0,596 i32 %1,597 iXLen %2)598 599 ret <vscale x 16 x i32> %a600}601 602define <vscale x 16 x i32> @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {603; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32:604; CHECK: # %bb.0: # %entry605; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu606; CHECK-NEXT: vslide1up.vx v8, v16, a0, v0.t607; CHECK-NEXT: ret608entry:609 %a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32(610 <vscale x 16 x i32> %0,611 <vscale x 16 x i32> %1,612 i32 %2,613 <vscale x 16 x i1> %3,614 iXLen %4, iXLen 1)615 616 ret <vscale x 16 x i32> %a617}618 619define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {620; RV32-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:621; RV32: # %bb.0: # %entry622; RV32-NEXT: vsetvli a2, a2, e64, m1, ta, ma623; RV32-NEXT: slli a2, a2, 1624; RV32-NEXT: vsetvli zero, a2, e32, m1, ta, ma625; RV32-NEXT: vslide1up.vx v9, v8, a1626; RV32-NEXT: vslide1up.vx v8, v9, a0627; RV32-NEXT: ret628;629; RV64-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:630; RV64: # %bb.0: # %entry631; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma632; RV64-NEXT: vslide1up.vx v9, v8, a0633; RV64-NEXT: vmv.v.v v8, v9634; RV64-NEXT: ret635entry:636 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(637 <vscale x 1 x i64> poison,638 <vscale x 1 x i64> %0,639 i64 %1,640 iXLen %2)641 642 ret <vscale x 1 x i64> %a643}644 645define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {646; RV32-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64:647; RV32: # %bb.0: # %entry648; RV32-NEXT: vsetvli a3, a2, e64, m1, ta, ma649; RV32-NEXT: slli a3, a3, 1650; RV32-NEXT: vsetvli zero, a3, e32, m1, ta, ma651; RV32-NEXT: vslide1up.vx v10, v9, a1652; RV32-NEXT: vslide1up.vx v9, v10, a0653; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma654; RV32-NEXT: vmerge.vvm v8, v8, v9, v0655; RV32-NEXT: ret656;657; RV64-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64:658; RV64: # %bb.0: # %entry659; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu660; RV64-NEXT: vslide1up.vx v8, v9, a0, v0.t661; RV64-NEXT: ret662entry:663 %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(664 <vscale x 1 x i64> %0,665 <vscale x 1 x i64> %1,666 i64 %2,667 <vscale x 1 x i1> %3,668 iXLen %4, iXLen 1)669 670 ret <vscale x 1 x i64> %a671}672 673define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {674; RV32-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:675; RV32: # %bb.0: # %entry676; RV32-NEXT: vsetvli a2, a2, e64, m2, ta, ma677; RV32-NEXT: slli a2, a2, 1678; RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma679; RV32-NEXT: vslide1up.vx v10, v8, a1680; RV32-NEXT: vslide1up.vx v8, v10, a0681; RV32-NEXT: ret682;683; RV64-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:684; RV64: # %bb.0: # %entry685; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma686; RV64-NEXT: vslide1up.vx v10, v8, a0687; RV64-NEXT: vmv.v.v v8, v10688; RV64-NEXT: ret689entry:690 %a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(691 <vscale x 2 x i64> poison,692 <vscale x 2 x i64> %0,693 i64 %1,694 iXLen %2)695 696 ret <vscale x 2 x i64> %a697}698 699define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {700; RV32-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64:701; RV32: # %bb.0: # %entry702; RV32-NEXT: vsetvli a3, a2, e64, m2, ta, ma703; RV32-NEXT: slli a3, a3, 1704; RV32-NEXT: vsetvli zero, a3, e32, m2, ta, ma705; RV32-NEXT: vslide1up.vx v12, v10, a1706; RV32-NEXT: vslide1up.vx v10, v12, a0707; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma708; RV32-NEXT: vmerge.vvm v8, v8, v10, v0709; RV32-NEXT: ret710;711; RV64-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64:712; RV64: # %bb.0: # %entry713; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu714; RV64-NEXT: vslide1up.vx v8, v10, a0, v0.t715; RV64-NEXT: ret716entry:717 %a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(718 <vscale x 2 x i64> %0,719 <vscale x 2 x i64> %1,720 i64 %2,721 <vscale x 2 x i1> %3,722 iXLen %4, iXLen 1)723 724 ret <vscale x 2 x i64> %a725}726 727define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {728; RV32-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:729; RV32: # %bb.0: # %entry730; RV32-NEXT: vsetvli a2, a2, e64, m4, ta, ma731; RV32-NEXT: slli a2, a2, 1732; RV32-NEXT: vsetvli zero, a2, e32, m4, ta, ma733; RV32-NEXT: vslide1up.vx v12, v8, a1734; RV32-NEXT: vslide1up.vx v8, v12, a0735; RV32-NEXT: ret736;737; RV64-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:738; RV64: # %bb.0: # %entry739; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma740; RV64-NEXT: vslide1up.vx v12, v8, a0741; RV64-NEXT: vmv.v.v v8, v12742; RV64-NEXT: ret743entry:744 %a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(745 <vscale x 4 x i64> poison,746 <vscale x 4 x i64> %0,747 i64 %1,748 iXLen %2)749 750 ret <vscale x 4 x i64> %a751}752 753define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {754; RV32-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64:755; RV32: # %bb.0: # %entry756; RV32-NEXT: vsetvli a3, a2, e64, m4, ta, ma757; RV32-NEXT: slli a3, a3, 1758; RV32-NEXT: vsetvli zero, a3, e32, m4, ta, ma759; RV32-NEXT: vslide1up.vx v16, v12, a1760; RV32-NEXT: vslide1up.vx v12, v16, a0761; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma762; RV32-NEXT: vmerge.vvm v8, v8, v12, v0763; RV32-NEXT: ret764;765; RV64-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64:766; RV64: # %bb.0: # %entry767; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu768; RV64-NEXT: vslide1up.vx v8, v12, a0, v0.t769; RV64-NEXT: ret770entry:771 %a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(772 <vscale x 4 x i64> %0,773 <vscale x 4 x i64> %1,774 i64 %2,775 <vscale x 4 x i1> %3,776 iXLen %4, iXLen 1)777 778 ret <vscale x 4 x i64> %a779}780 781define <vscale x 8 x i64> @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {782; RV32-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64:783; RV32: # %bb.0: # %entry784; RV32-NEXT: vsetvli a2, a2, e64, m8, ta, ma785; RV32-NEXT: slli a2, a2, 1786; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma787; RV32-NEXT: vslide1up.vx v16, v8, a1788; RV32-NEXT: vslide1up.vx v8, v16, a0789; RV32-NEXT: ret790;791; RV64-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64:792; RV64: # %bb.0: # %entry793; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma794; RV64-NEXT: vslide1up.vx v16, v8, a0795; RV64-NEXT: vmv.v.v v8, v16796; RV64-NEXT: ret797entry:798 %a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(799 <vscale x 8 x i64> poison,800 <vscale x 8 x i64> %0,801 i64 %1,802 iXLen %2)803 804 ret <vscale x 8 x i64> %a805}806 807define <vscale x 8 x i64> @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {808; RV32-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64:809; RV32: # %bb.0: # %entry810; RV32-NEXT: vsetvli a3, a2, e64, m8, ta, ma811; RV32-NEXT: slli a3, a3, 1812; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma813; RV32-NEXT: vslide1up.vx v24, v16, a1814; RV32-NEXT: vslide1up.vx v16, v24, a0815; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma816; RV32-NEXT: vmerge.vvm v8, v8, v16, v0817; RV32-NEXT: ret818;819; RV64-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64:820; RV64: # %bb.0: # %entry821; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu822; RV64-NEXT: vslide1up.vx v8, v16, a0, v0.t823; RV64-NEXT: ret824entry:825 %a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(826 <vscale x 8 x i64> %0,827 <vscale x 8 x i64> %1,828 i64 %2,829 <vscale x 8 x i1> %3,830 iXLen %4, iXLen 1)831 832 ret <vscale x 8 x i64> %a833}834