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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+d,+zvfhmin,+zvfbfmin \3; RUN:   -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+d,+zvfhmin,+zvfbfmin \5; RUN:   -verify-machineinstrs | FileCheck %s6 7define <vscale x 1 x i8> @intrinsic_vslidedown_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, iXLen %3) nounwind {8; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i8_nxv1i8:9; CHECK:       # %bb.0: # %entry10; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT:    vslidedown.vx v8, v9, a012; CHECK-NEXT:    ret13entry:14  %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(15    <vscale x 1 x i8> %0,16    <vscale x 1 x i8> %1,17    iXLen %2,18    iXLen %3,19    iXLen 1)20 21  ret <vscale x 1 x i8> %a22}23 24define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {25; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i8_nxv1i8:26; CHECK:       # %bb.0: # %entry27; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, tu, mu28; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t29; CHECK-NEXT:    ret30entry:31  %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(32    <vscale x 1 x i8> %0,33    <vscale x 1 x i8> %1,34    iXLen %2,35    <vscale x 1 x i1> %3,36    iXLen %4, iXLen 0)37 38  ret <vscale x 1 x i8> %a39}40 41define <vscale x 1 x i8> @intrinsic_vslidedown_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {42; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i8_nxv1i8:43; CHECK:       # %bb.0: # %entry44; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma45; CHECK-NEXT:    vslidedown.vi v8, v9, 946; CHECK-NEXT:    ret47entry:48  %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.nxv1i8(49    <vscale x 1 x i8> %0,50    <vscale x 1 x i8> %1,51    iXLen 9,52    iXLen %2,53    iXLen 1)54 55  ret <vscale x 1 x i8> %a56}57 58define <vscale x 1 x i8> @intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {59; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i8_nxv1i8:60; CHECK:       # %bb.0: # %entry61; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu62; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t63; CHECK-NEXT:    ret64entry:65  %a = call <vscale x 1 x i8> @llvm.riscv.vslidedown.mask.nxv1i8(66    <vscale x 1 x i8> %0,67    <vscale x 1 x i8> %1,68    iXLen 9,69    <vscale x 1 x i1> %2,70    iXLen %3, iXLen 0)71 72  ret <vscale x 1 x i8> %a73}74 75define <vscale x 2 x i8> @intrinsic_vslidedown_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2, iXLen %3) nounwind {76; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i8_nxv2i8:77; CHECK:       # %bb.0: # %entry78; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, ma79; CHECK-NEXT:    vslidedown.vx v8, v9, a080; CHECK-NEXT:    ret81entry:82  %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(83    <vscale x 2 x i8> %0,84    <vscale x 2 x i8> %1,85    iXLen %2,86    iXLen %3,87    iXLen 1)88 89  ret <vscale x 2 x i8> %a90}91 92define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {93; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i8_nxv2i8:94; CHECK:       # %bb.0: # %entry95; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, tu, mu96; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t97; CHECK-NEXT:    ret98entry:99  %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(100    <vscale x 2 x i8> %0,101    <vscale x 2 x i8> %1,102    iXLen %2,103    <vscale x 2 x i1> %3,104    iXLen %4, iXLen 0)105 106  ret <vscale x 2 x i8> %a107}108 109define <vscale x 2 x i8> @intrinsic_vslidedown_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {110; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i8_nxv2i8:111; CHECK:       # %bb.0: # %entry112; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, ta, ma113; CHECK-NEXT:    vslidedown.vi v8, v9, 9114; CHECK-NEXT:    ret115entry:116  %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.nxv2i8(117    <vscale x 2 x i8> %0,118    <vscale x 2 x i8> %1,119    iXLen 9,120    iXLen %2,121    iXLen 1)122 123  ret <vscale x 2 x i8> %a124}125 126define <vscale x 2 x i8> @intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {127; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i8_nxv2i8:128; CHECK:       # %bb.0: # %entry129; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, mu130; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t131; CHECK-NEXT:    ret132entry:133  %a = call <vscale x 2 x i8> @llvm.riscv.vslidedown.mask.nxv2i8(134    <vscale x 2 x i8> %0,135    <vscale x 2 x i8> %1,136    iXLen 9,137    <vscale x 2 x i1> %2,138    iXLen %3, iXLen 0)139 140  ret <vscale x 2 x i8> %a141}142 143define <vscale x 4 x i8> @intrinsic_vslidedown_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2, iXLen %3) nounwind {144; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i8_nxv4i8:145; CHECK:       # %bb.0: # %entry146; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, ta, ma147; CHECK-NEXT:    vslidedown.vx v8, v9, a0148; CHECK-NEXT:    ret149entry:150  %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(151    <vscale x 4 x i8> %0,152    <vscale x 4 x i8> %1,153    iXLen %2,154    iXLen %3,155    iXLen 1)156 157  ret <vscale x 4 x i8> %a158}159 160define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {161; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i8_nxv4i8:162; CHECK:       # %bb.0: # %entry163; CHECK-NEXT:    vsetvli zero, a1, e8, mf2, tu, mu164; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t165; CHECK-NEXT:    ret166entry:167  %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(168    <vscale x 4 x i8> %0,169    <vscale x 4 x i8> %1,170    iXLen %2,171    <vscale x 4 x i1> %3,172    iXLen %4, iXLen 0)173 174  ret <vscale x 4 x i8> %a175}176 177define <vscale x 4 x i8> @intrinsic_vslidedown_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {178; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i8_nxv4i8:179; CHECK:       # %bb.0: # %entry180; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, ta, ma181; CHECK-NEXT:    vslidedown.vi v8, v9, 9182; CHECK-NEXT:    ret183entry:184  %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.nxv4i8(185    <vscale x 4 x i8> %0,186    <vscale x 4 x i8> %1,187    iXLen 9,188    iXLen %2,189    iXLen 1)190 191  ret <vscale x 4 x i8> %a192}193 194define <vscale x 4 x i8> @intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {195; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i8_nxv4i8:196; CHECK:       # %bb.0: # %entry197; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, mu198; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t199; CHECK-NEXT:    ret200entry:201  %a = call <vscale x 4 x i8> @llvm.riscv.vslidedown.mask.nxv4i8(202    <vscale x 4 x i8> %0,203    <vscale x 4 x i8> %1,204    iXLen 9,205    <vscale x 4 x i1> %2,206    iXLen %3, iXLen 0)207 208  ret <vscale x 4 x i8> %a209}210 211define <vscale x 8 x i8> @intrinsic_vslidedown_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2, iXLen %3) nounwind {212; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i8_nxv8i8:213; CHECK:       # %bb.0: # %entry214; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma215; CHECK-NEXT:    vslidedown.vx v8, v9, a0216; CHECK-NEXT:    ret217entry:218  %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(219    <vscale x 8 x i8> %0,220    <vscale x 8 x i8> %1,221    iXLen %2,222    iXLen %3,223    iXLen 1)224 225  ret <vscale x 8 x i8> %a226}227 228define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {229; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i8_nxv8i8:230; CHECK:       # %bb.0: # %entry231; CHECK-NEXT:    vsetvli zero, a1, e8, m1, tu, mu232; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t233; CHECK-NEXT:    ret234entry:235  %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(236    <vscale x 8 x i8> %0,237    <vscale x 8 x i8> %1,238    iXLen %2,239    <vscale x 8 x i1> %3,240    iXLen %4, iXLen 0)241 242  ret <vscale x 8 x i8> %a243}244 245define <vscale x 8 x i8> @intrinsic_vslidedown_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {246; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i8_nxv8i8:247; CHECK:       # %bb.0: # %entry248; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma249; CHECK-NEXT:    vslidedown.vi v8, v9, 9250; CHECK-NEXT:    ret251entry:252  %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.nxv8i8(253    <vscale x 8 x i8> %0,254    <vscale x 8 x i8> %1,255    iXLen 9,256    iXLen %2,257    iXLen 1)258 259  ret <vscale x 8 x i8> %a260}261 262define <vscale x 8 x i8> @intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {263; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i8_nxv8i8:264; CHECK:       # %bb.0: # %entry265; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, mu266; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t267; CHECK-NEXT:    ret268entry:269  %a = call <vscale x 8 x i8> @llvm.riscv.vslidedown.mask.nxv8i8(270    <vscale x 8 x i8> %0,271    <vscale x 8 x i8> %1,272    iXLen 9,273    <vscale x 8 x i1> %2,274    iXLen %3, iXLen 0)275 276  ret <vscale x 8 x i8> %a277}278 279define <vscale x 16 x i8> @intrinsic_vslidedown_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2, iXLen %3) nounwind {280; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i8_nxv16i8:281; CHECK:       # %bb.0: # %entry282; CHECK-NEXT:    vsetvli zero, a1, e8, m2, ta, ma283; CHECK-NEXT:    vslidedown.vx v8, v10, a0284; CHECK-NEXT:    ret285entry:286  %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(287    <vscale x 16 x i8> %0,288    <vscale x 16 x i8> %1,289    iXLen %2,290    iXLen %3,291    iXLen 1)292 293  ret <vscale x 16 x i8> %a294}295 296define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {297; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i8_nxv16i8:298; CHECK:       # %bb.0: # %entry299; CHECK-NEXT:    vsetvli zero, a1, e8, m2, tu, mu300; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t301; CHECK-NEXT:    ret302entry:303  %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(304    <vscale x 16 x i8> %0,305    <vscale x 16 x i8> %1,306    iXLen %2,307    <vscale x 16 x i1> %3,308    iXLen %4, iXLen 0)309 310  ret <vscale x 16 x i8> %a311}312 313define <vscale x 16 x i8> @intrinsic_vslidedown_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {314; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i8_nxv16i8:315; CHECK:       # %bb.0: # %entry316; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma317; CHECK-NEXT:    vslidedown.vi v8, v10, 9318; CHECK-NEXT:    ret319entry:320  %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.nxv16i8(321    <vscale x 16 x i8> %0,322    <vscale x 16 x i8> %1,323    iXLen 9,324    iXLen %2,325    iXLen 1)326 327  ret <vscale x 16 x i8> %a328}329 330define <vscale x 16 x i8> @intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {331; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i8_nxv16i8:332; CHECK:       # %bb.0: # %entry333; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, mu334; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t335; CHECK-NEXT:    ret336entry:337  %a = call <vscale x 16 x i8> @llvm.riscv.vslidedown.mask.nxv16i8(338    <vscale x 16 x i8> %0,339    <vscale x 16 x i8> %1,340    iXLen 9,341    <vscale x 16 x i1> %2,342    iXLen %3, iXLen 0)343 344  ret <vscale x 16 x i8> %a345}346 347define <vscale x 32 x i8> @intrinsic_vslidedown_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2, iXLen %3) nounwind {348; CHECK-LABEL: intrinsic_vslidedown_vx_nxv32i8_nxv32i8:349; CHECK:       # %bb.0: # %entry350; CHECK-NEXT:    vsetvli zero, a1, e8, m4, ta, ma351; CHECK-NEXT:    vslidedown.vx v8, v12, a0352; CHECK-NEXT:    ret353entry:354  %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(355    <vscale x 32 x i8> %0,356    <vscale x 32 x i8> %1,357    iXLen %2,358    iXLen %3,359    iXLen 1)360 361  ret <vscale x 32 x i8> %a362}363 364define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {365; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv32i8_nxv32i8:366; CHECK:       # %bb.0: # %entry367; CHECK-NEXT:    vsetvli zero, a1, e8, m4, tu, mu368; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t369; CHECK-NEXT:    ret370entry:371  %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(372    <vscale x 32 x i8> %0,373    <vscale x 32 x i8> %1,374    iXLen %2,375    <vscale x 32 x i1> %3,376    iXLen %4, iXLen 0)377 378  ret <vscale x 32 x i8> %a379}380 381define <vscale x 32 x i8> @intrinsic_vslidedown_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {382; CHECK-LABEL: intrinsic_vslidedown_vi_nxv32i8_nxv32i8:383; CHECK:       # %bb.0: # %entry384; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma385; CHECK-NEXT:    vslidedown.vi v8, v12, 9386; CHECK-NEXT:    ret387entry:388  %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.nxv32i8(389    <vscale x 32 x i8> %0,390    <vscale x 32 x i8> %1,391    iXLen 9,392    iXLen %2,393    iXLen 1)394 395  ret <vscale x 32 x i8> %a396}397 398define <vscale x 32 x i8> @intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {399; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv32i8_nxv32i8:400; CHECK:       # %bb.0: # %entry401; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, mu402; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t403; CHECK-NEXT:    ret404entry:405  %a = call <vscale x 32 x i8> @llvm.riscv.vslidedown.mask.nxv32i8(406    <vscale x 32 x i8> %0,407    <vscale x 32 x i8> %1,408    iXLen 9,409    <vscale x 32 x i1> %2,410    iXLen %3, iXLen 0)411 412  ret <vscale x 32 x i8> %a413}414 415define <vscale x 1 x i16> @intrinsic_vslidedown_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2, iXLen %3) nounwind {416; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i16_nxv1i16:417; CHECK:       # %bb.0: # %entry418; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma419; CHECK-NEXT:    vslidedown.vx v8, v9, a0420; CHECK-NEXT:    ret421entry:422  %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(423    <vscale x 1 x i16> %0,424    <vscale x 1 x i16> %1,425    iXLen %2,426    iXLen %3,427    iXLen 1)428 429  ret <vscale x 1 x i16> %a430}431 432define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {433; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i16_nxv1i16:434; CHECK:       # %bb.0: # %entry435; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, mu436; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t437; CHECK-NEXT:    ret438entry:439  %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(440    <vscale x 1 x i16> %0,441    <vscale x 1 x i16> %1,442    iXLen %2,443    <vscale x 1 x i1> %3,444    iXLen %4, iXLen 0)445 446  ret <vscale x 1 x i16> %a447}448 449define <vscale x 1 x i16> @intrinsic_vslidedown_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {450; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i16_nxv1i16:451; CHECK:       # %bb.0: # %entry452; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma453; CHECK-NEXT:    vslidedown.vi v8, v9, 9454; CHECK-NEXT:    ret455entry:456  %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.nxv1i16(457    <vscale x 1 x i16> %0,458    <vscale x 1 x i16> %1,459    iXLen 9,460    iXLen %2,461    iXLen 1)462 463  ret <vscale x 1 x i16> %a464}465 466define <vscale x 1 x i16> @intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {467; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i16_nxv1i16:468; CHECK:       # %bb.0: # %entry469; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu470; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t471; CHECK-NEXT:    ret472entry:473  %a = call <vscale x 1 x i16> @llvm.riscv.vslidedown.mask.nxv1i16(474    <vscale x 1 x i16> %0,475    <vscale x 1 x i16> %1,476    iXLen 9,477    <vscale x 1 x i1> %2,478    iXLen %3, iXLen 0)479 480  ret <vscale x 1 x i16> %a481}482 483define <vscale x 2 x i16> @intrinsic_vslidedown_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2, iXLen %3) nounwind {484; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i16_nxv2i16:485; CHECK:       # %bb.0: # %entry486; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma487; CHECK-NEXT:    vslidedown.vx v8, v9, a0488; CHECK-NEXT:    ret489entry:490  %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(491    <vscale x 2 x i16> %0,492    <vscale x 2 x i16> %1,493    iXLen %2,494    iXLen %3,495    iXLen 1)496 497  ret <vscale x 2 x i16> %a498}499 500define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {501; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i16_nxv2i16:502; CHECK:       # %bb.0: # %entry503; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, mu504; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t505; CHECK-NEXT:    ret506entry:507  %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(508    <vscale x 2 x i16> %0,509    <vscale x 2 x i16> %1,510    iXLen %2,511    <vscale x 2 x i1> %3,512    iXLen %4, iXLen 0)513 514  ret <vscale x 2 x i16> %a515}516 517define <vscale x 2 x i16> @intrinsic_vslidedown_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {518; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i16_nxv2i16:519; CHECK:       # %bb.0: # %entry520; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma521; CHECK-NEXT:    vslidedown.vi v8, v9, 9522; CHECK-NEXT:    ret523entry:524  %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.nxv2i16(525    <vscale x 2 x i16> %0,526    <vscale x 2 x i16> %1,527    iXLen 9,528    iXLen %2,529    iXLen 1)530 531  ret <vscale x 2 x i16> %a532}533 534define <vscale x 2 x i16> @intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {535; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i16_nxv2i16:536; CHECK:       # %bb.0: # %entry537; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu538; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t539; CHECK-NEXT:    ret540entry:541  %a = call <vscale x 2 x i16> @llvm.riscv.vslidedown.mask.nxv2i16(542    <vscale x 2 x i16> %0,543    <vscale x 2 x i16> %1,544    iXLen 9,545    <vscale x 2 x i1> %2,546    iXLen %3, iXLen 0)547 548  ret <vscale x 2 x i16> %a549}550 551define <vscale x 4 x i16> @intrinsic_vslidedown_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2, iXLen %3) nounwind {552; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i16_nxv4i16:553; CHECK:       # %bb.0: # %entry554; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma555; CHECK-NEXT:    vslidedown.vx v8, v9, a0556; CHECK-NEXT:    ret557entry:558  %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(559    <vscale x 4 x i16> %0,560    <vscale x 4 x i16> %1,561    iXLen %2,562    iXLen %3,563    iXLen 1)564 565  ret <vscale x 4 x i16> %a566}567 568define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {569; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i16_nxv4i16:570; CHECK:       # %bb.0: # %entry571; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu572; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t573; CHECK-NEXT:    ret574entry:575  %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(576    <vscale x 4 x i16> %0,577    <vscale x 4 x i16> %1,578    iXLen %2,579    <vscale x 4 x i1> %3,580    iXLen %4, iXLen 0)581 582  ret <vscale x 4 x i16> %a583}584 585define <vscale x 4 x i16> @intrinsic_vslidedown_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {586; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i16_nxv4i16:587; CHECK:       # %bb.0: # %entry588; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma589; CHECK-NEXT:    vslidedown.vi v8, v9, 9590; CHECK-NEXT:    ret591entry:592  %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.nxv4i16(593    <vscale x 4 x i16> %0,594    <vscale x 4 x i16> %1,595    iXLen 9,596    iXLen %2,597    iXLen 1)598 599  ret <vscale x 4 x i16> %a600}601 602define <vscale x 4 x i16> @intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {603; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i16_nxv4i16:604; CHECK:       # %bb.0: # %entry605; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu606; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t607; CHECK-NEXT:    ret608entry:609  %a = call <vscale x 4 x i16> @llvm.riscv.vslidedown.mask.nxv4i16(610    <vscale x 4 x i16> %0,611    <vscale x 4 x i16> %1,612    iXLen 9,613    <vscale x 4 x i1> %2,614    iXLen %3, iXLen 0)615 616  ret <vscale x 4 x i16> %a617}618 619define <vscale x 8 x i16> @intrinsic_vslidedown_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2, iXLen %3) nounwind {620; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i16_nxv8i16:621; CHECK:       # %bb.0: # %entry622; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma623; CHECK-NEXT:    vslidedown.vx v8, v10, a0624; CHECK-NEXT:    ret625entry:626  %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(627    <vscale x 8 x i16> %0,628    <vscale x 8 x i16> %1,629    iXLen %2,630    iXLen %3,631    iXLen 1)632 633  ret <vscale x 8 x i16> %a634}635 636define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {637; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i16_nxv8i16:638; CHECK:       # %bb.0: # %entry639; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, mu640; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t641; CHECK-NEXT:    ret642entry:643  %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(644    <vscale x 8 x i16> %0,645    <vscale x 8 x i16> %1,646    iXLen %2,647    <vscale x 8 x i1> %3,648    iXLen %4, iXLen 0)649 650  ret <vscale x 8 x i16> %a651}652 653define <vscale x 8 x i16> @intrinsic_vslidedown_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {654; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i16_nxv8i16:655; CHECK:       # %bb.0: # %entry656; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma657; CHECK-NEXT:    vslidedown.vi v8, v10, 9658; CHECK-NEXT:    ret659entry:660  %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.nxv8i16(661    <vscale x 8 x i16> %0,662    <vscale x 8 x i16> %1,663    iXLen 9,664    iXLen %2,665    iXLen 1)666 667  ret <vscale x 8 x i16> %a668}669 670define <vscale x 8 x i16> @intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {671; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i16_nxv8i16:672; CHECK:       # %bb.0: # %entry673; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu674; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t675; CHECK-NEXT:    ret676entry:677  %a = call <vscale x 8 x i16> @llvm.riscv.vslidedown.mask.nxv8i16(678    <vscale x 8 x i16> %0,679    <vscale x 8 x i16> %1,680    iXLen 9,681    <vscale x 8 x i1> %2,682    iXLen %3, iXLen 0)683 684  ret <vscale x 8 x i16> %a685}686 687define <vscale x 16 x i16> @intrinsic_vslidedown_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2, iXLen %3) nounwind {688; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16i16_nxv16i16:689; CHECK:       # %bb.0: # %entry690; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma691; CHECK-NEXT:    vslidedown.vx v8, v12, a0692; CHECK-NEXT:    ret693entry:694  %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(695    <vscale x 16 x i16> %0,696    <vscale x 16 x i16> %1,697    iXLen %2,698    iXLen %3,699    iXLen 1)700 701  ret <vscale x 16 x i16> %a702}703 704define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {705; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16i16_nxv16i16:706; CHECK:       # %bb.0: # %entry707; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, mu708; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t709; CHECK-NEXT:    ret710entry:711  %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(712    <vscale x 16 x i16> %0,713    <vscale x 16 x i16> %1,714    iXLen %2,715    <vscale x 16 x i1> %3,716    iXLen %4, iXLen 0)717 718  ret <vscale x 16 x i16> %a719}720 721define <vscale x 16 x i16> @intrinsic_vslidedown_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {722; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16i16_nxv16i16:723; CHECK:       # %bb.0: # %entry724; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma725; CHECK-NEXT:    vslidedown.vi v8, v12, 9726; CHECK-NEXT:    ret727entry:728  %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.nxv16i16(729    <vscale x 16 x i16> %0,730    <vscale x 16 x i16> %1,731    iXLen 9,732    iXLen %2,733    iXLen 1)734 735  ret <vscale x 16 x i16> %a736}737 738define <vscale x 16 x i16> @intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {739; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16i16_nxv16i16:740; CHECK:       # %bb.0: # %entry741; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu742; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t743; CHECK-NEXT:    ret744entry:745  %a = call <vscale x 16 x i16> @llvm.riscv.vslidedown.mask.nxv16i16(746    <vscale x 16 x i16> %0,747    <vscale x 16 x i16> %1,748    iXLen 9,749    <vscale x 16 x i1> %2,750    iXLen %3, iXLen 0)751 752  ret <vscale x 16 x i16> %a753}754 755define <vscale x 1 x i32> @intrinsic_vslidedown_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2, iXLen %3) nounwind {756; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i32_nxv1i32:757; CHECK:       # %bb.0: # %entry758; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma759; CHECK-NEXT:    vslidedown.vx v8, v9, a0760; CHECK-NEXT:    ret761entry:762  %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(763    <vscale x 1 x i32> %0,764    <vscale x 1 x i32> %1,765    iXLen %2,766    iXLen %3,767    iXLen 1)768 769  ret <vscale x 1 x i32> %a770}771 772define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {773; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i32_nxv1i32:774; CHECK:       # %bb.0: # %entry775; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu776; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t777; CHECK-NEXT:    ret778entry:779  %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(780    <vscale x 1 x i32> %0,781    <vscale x 1 x i32> %1,782    iXLen %2,783    <vscale x 1 x i1> %3,784    iXLen %4, iXLen 0)785 786  ret <vscale x 1 x i32> %a787}788 789define <vscale x 1 x i32> @intrinsic_vslidedown_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {790; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i32_nxv1i32:791; CHECK:       # %bb.0: # %entry792; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma793; CHECK-NEXT:    vslidedown.vi v8, v9, 9794; CHECK-NEXT:    ret795entry:796  %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.nxv1i32(797    <vscale x 1 x i32> %0,798    <vscale x 1 x i32> %1,799    iXLen 9,800    iXLen %2,801    iXLen 1)802 803  ret <vscale x 1 x i32> %a804}805 806define <vscale x 1 x i32> @intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {807; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i32_nxv1i32:808; CHECK:       # %bb.0: # %entry809; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu810; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t811; CHECK-NEXT:    ret812entry:813  %a = call <vscale x 1 x i32> @llvm.riscv.vslidedown.mask.nxv1i32(814    <vscale x 1 x i32> %0,815    <vscale x 1 x i32> %1,816    iXLen 9,817    <vscale x 1 x i1> %2,818    iXLen %3, iXLen 0)819 820  ret <vscale x 1 x i32> %a821}822 823define <vscale x 2 x i32> @intrinsic_vslidedown_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2, iXLen %3) nounwind {824; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i32_nxv2i32:825; CHECK:       # %bb.0: # %entry826; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma827; CHECK-NEXT:    vslidedown.vx v8, v9, a0828; CHECK-NEXT:    ret829entry:830  %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(831    <vscale x 2 x i32> %0,832    <vscale x 2 x i32> %1,833    iXLen %2,834    iXLen %3,835    iXLen 1)836 837  ret <vscale x 2 x i32> %a838}839 840define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {841; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i32_nxv2i32:842; CHECK:       # %bb.0: # %entry843; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu844; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t845; CHECK-NEXT:    ret846entry:847  %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(848    <vscale x 2 x i32> %0,849    <vscale x 2 x i32> %1,850    iXLen %2,851    <vscale x 2 x i1> %3,852    iXLen %4, iXLen 0)853 854  ret <vscale x 2 x i32> %a855}856 857define <vscale x 2 x i32> @intrinsic_vslidedown_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {858; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i32_nxv2i32:859; CHECK:       # %bb.0: # %entry860; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma861; CHECK-NEXT:    vslidedown.vi v8, v9, 9862; CHECK-NEXT:    ret863entry:864  %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.nxv2i32(865    <vscale x 2 x i32> %0,866    <vscale x 2 x i32> %1,867    iXLen 9,868    iXLen %2,869    iXLen 1)870 871  ret <vscale x 2 x i32> %a872}873 874define <vscale x 2 x i32> @intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {875; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i32_nxv2i32:876; CHECK:       # %bb.0: # %entry877; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu878; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t879; CHECK-NEXT:    ret880entry:881  %a = call <vscale x 2 x i32> @llvm.riscv.vslidedown.mask.nxv2i32(882    <vscale x 2 x i32> %0,883    <vscale x 2 x i32> %1,884    iXLen 9,885    <vscale x 2 x i1> %2,886    iXLen %3, iXLen 0)887 888  ret <vscale x 2 x i32> %a889}890 891define <vscale x 4 x i32> @intrinsic_vslidedown_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, iXLen %3) nounwind {892; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i32_nxv4i32:893; CHECK:       # %bb.0: # %entry894; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma895; CHECK-NEXT:    vslidedown.vx v8, v10, a0896; CHECK-NEXT:    ret897entry:898  %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(899    <vscale x 4 x i32> %0,900    <vscale x 4 x i32> %1,901    iXLen %2,902    iXLen %3,903    iXLen 1)904 905  ret <vscale x 4 x i32> %a906}907 908define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {909; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i32_nxv4i32:910; CHECK:       # %bb.0: # %entry911; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu912; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t913; CHECK-NEXT:    ret914entry:915  %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(916    <vscale x 4 x i32> %0,917    <vscale x 4 x i32> %1,918    iXLen %2,919    <vscale x 4 x i1> %3,920    iXLen %4, iXLen 0)921 922  ret <vscale x 4 x i32> %a923}924 925define <vscale x 4 x i32> @intrinsic_vslidedown_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {926; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i32_nxv4i32:927; CHECK:       # %bb.0: # %entry928; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma929; CHECK-NEXT:    vslidedown.vi v8, v10, 9930; CHECK-NEXT:    ret931entry:932  %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.nxv4i32(933    <vscale x 4 x i32> %0,934    <vscale x 4 x i32> %1,935    iXLen 9,936    iXLen %2,937    iXLen 1)938 939  ret <vscale x 4 x i32> %a940}941 942define <vscale x 4 x i32> @intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {943; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i32_nxv4i32:944; CHECK:       # %bb.0: # %entry945; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu946; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t947; CHECK-NEXT:    ret948entry:949  %a = call <vscale x 4 x i32> @llvm.riscv.vslidedown.mask.nxv4i32(950    <vscale x 4 x i32> %0,951    <vscale x 4 x i32> %1,952    iXLen 9,953    <vscale x 4 x i1> %2,954    iXLen %3, iXLen 0)955 956  ret <vscale x 4 x i32> %a957}958 959define <vscale x 8 x i32> @intrinsic_vslidedown_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2, iXLen %3) nounwind {960; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8i32_nxv8i32:961; CHECK:       # %bb.0: # %entry962; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma963; CHECK-NEXT:    vslidedown.vx v8, v12, a0964; CHECK-NEXT:    ret965entry:966  %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(967    <vscale x 8 x i32> %0,968    <vscale x 8 x i32> %1,969    iXLen %2,970    iXLen %3,971    iXLen 1)972 973  ret <vscale x 8 x i32> %a974}975 976define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {977; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8i32_nxv8i32:978; CHECK:       # %bb.0: # %entry979; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu980; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t981; CHECK-NEXT:    ret982entry:983  %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(984    <vscale x 8 x i32> %0,985    <vscale x 8 x i32> %1,986    iXLen %2,987    <vscale x 8 x i1> %3,988    iXLen %4, iXLen 0)989 990  ret <vscale x 8 x i32> %a991}992 993define <vscale x 8 x i32> @intrinsic_vslidedown_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {994; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8i32_nxv8i32:995; CHECK:       # %bb.0: # %entry996; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma997; CHECK-NEXT:    vslidedown.vi v8, v12, 9998; CHECK-NEXT:    ret999entry:1000  %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.nxv8i32(1001    <vscale x 8 x i32> %0,1002    <vscale x 8 x i32> %1,1003    iXLen 9,1004    iXLen %2,1005    iXLen 1)1006 1007  ret <vscale x 8 x i32> %a1008}1009 1010define <vscale x 8 x i32> @intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1011; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8i32_nxv8i32:1012; CHECK:       # %bb.0: # %entry1013; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu1014; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t1015; CHECK-NEXT:    ret1016entry:1017  %a = call <vscale x 8 x i32> @llvm.riscv.vslidedown.mask.nxv8i32(1018    <vscale x 8 x i32> %0,1019    <vscale x 8 x i32> %1,1020    iXLen 9,1021    <vscale x 8 x i1> %2,1022    iXLen %3, iXLen 0)1023 1024  ret <vscale x 8 x i32> %a1025}1026 1027define <vscale x 1 x i64> @intrinsic_vslidedown_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2, iXLen %3) nounwind {1028; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1i64_nxv1i64:1029; CHECK:       # %bb.0: # %entry1030; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1031; CHECK-NEXT:    vslidedown.vx v8, v9, a01032; CHECK-NEXT:    ret1033entry:1034  %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(1035    <vscale x 1 x i64> %0,1036    <vscale x 1 x i64> %1,1037    iXLen %2,1038    iXLen %3,1039    iXLen 1)1040 1041  ret <vscale x 1 x i64> %a1042}1043 1044define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1045; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1i64_nxv1i64:1046; CHECK:       # %bb.0: # %entry1047; CHECK-NEXT:    vsetvli zero, a1, e64, m1, tu, mu1048; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1049; CHECK-NEXT:    ret1050entry:1051  %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(1052    <vscale x 1 x i64> %0,1053    <vscale x 1 x i64> %1,1054    iXLen %2,1055    <vscale x 1 x i1> %3,1056    iXLen %4, iXLen 0)1057 1058  ret <vscale x 1 x i64> %a1059}1060 1061define <vscale x 1 x i64> @intrinsic_vslidedown_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {1062; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1i64_nxv1i64:1063; CHECK:       # %bb.0: # %entry1064; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1065; CHECK-NEXT:    vslidedown.vi v8, v9, 91066; CHECK-NEXT:    ret1067entry:1068  %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.nxv1i64(1069    <vscale x 1 x i64> %0,1070    <vscale x 1 x i64> %1,1071    iXLen 9,1072    iXLen %2,1073    iXLen 1)1074 1075  ret <vscale x 1 x i64> %a1076}1077 1078define <vscale x 1 x i64> @intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1079; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1i64_nxv1i64:1080; CHECK:       # %bb.0: # %entry1081; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu1082; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1083; CHECK-NEXT:    ret1084entry:1085  %a = call <vscale x 1 x i64> @llvm.riscv.vslidedown.mask.nxv1i64(1086    <vscale x 1 x i64> %0,1087    <vscale x 1 x i64> %1,1088    iXLen 9,1089    <vscale x 1 x i1> %2,1090    iXLen %3, iXLen 0)1091 1092  ret <vscale x 1 x i64> %a1093}1094 1095define <vscale x 2 x i64> @intrinsic_vslidedown_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2, iXLen %3) nounwind {1096; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2i64_nxv2i64:1097; CHECK:       # %bb.0: # %entry1098; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1099; CHECK-NEXT:    vslidedown.vx v8, v10, a01100; CHECK-NEXT:    ret1101entry:1102  %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(1103    <vscale x 2 x i64> %0,1104    <vscale x 2 x i64> %1,1105    iXLen %2,1106    iXLen %3,1107    iXLen 1)1108 1109  ret <vscale x 2 x i64> %a1110}1111 1112define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1113; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2i64_nxv2i64:1114; CHECK:       # %bb.0: # %entry1115; CHECK-NEXT:    vsetvli zero, a1, e64, m2, tu, mu1116; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t1117; CHECK-NEXT:    ret1118entry:1119  %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(1120    <vscale x 2 x i64> %0,1121    <vscale x 2 x i64> %1,1122    iXLen %2,1123    <vscale x 2 x i1> %3,1124    iXLen %4, iXLen 0)1125 1126  ret <vscale x 2 x i64> %a1127}1128 1129define <vscale x 2 x i64> @intrinsic_vslidedown_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {1130; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2i64_nxv2i64:1131; CHECK:       # %bb.0: # %entry1132; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1133; CHECK-NEXT:    vslidedown.vi v8, v10, 91134; CHECK-NEXT:    ret1135entry:1136  %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.nxv2i64(1137    <vscale x 2 x i64> %0,1138    <vscale x 2 x i64> %1,1139    iXLen 9,1140    iXLen %2,1141    iXLen 1)1142 1143  ret <vscale x 2 x i64> %a1144}1145 1146define <vscale x 2 x i64> @intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1147; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2i64_nxv2i64:1148; CHECK:       # %bb.0: # %entry1149; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, mu1150; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t1151; CHECK-NEXT:    ret1152entry:1153  %a = call <vscale x 2 x i64> @llvm.riscv.vslidedown.mask.nxv2i64(1154    <vscale x 2 x i64> %0,1155    <vscale x 2 x i64> %1,1156    iXLen 9,1157    <vscale x 2 x i1> %2,1158    iXLen %3, iXLen 0)1159 1160  ret <vscale x 2 x i64> %a1161}1162 1163define <vscale x 4 x i64> @intrinsic_vslidedown_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2, iXLen %3) nounwind {1164; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4i64_nxv4i64:1165; CHECK:       # %bb.0: # %entry1166; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1167; CHECK-NEXT:    vslidedown.vx v8, v12, a01168; CHECK-NEXT:    ret1169entry:1170  %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(1171    <vscale x 4 x i64> %0,1172    <vscale x 4 x i64> %1,1173    iXLen %2,1174    iXLen %3,1175    iXLen 1)1176 1177  ret <vscale x 4 x i64> %a1178}1179 1180define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1181; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4i64_nxv4i64:1182; CHECK:       # %bb.0: # %entry1183; CHECK-NEXT:    vsetvli zero, a1, e64, m4, tu, mu1184; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t1185; CHECK-NEXT:    ret1186entry:1187  %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(1188    <vscale x 4 x i64> %0,1189    <vscale x 4 x i64> %1,1190    iXLen %2,1191    <vscale x 4 x i1> %3,1192    iXLen %4, iXLen 0)1193 1194  ret <vscale x 4 x i64> %a1195}1196 1197define <vscale x 4 x i64> @intrinsic_vslidedown_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {1198; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4i64_nxv4i64:1199; CHECK:       # %bb.0: # %entry1200; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma1201; CHECK-NEXT:    vslidedown.vi v8, v12, 91202; CHECK-NEXT:    ret1203entry:1204  %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.nxv4i64(1205    <vscale x 4 x i64> %0,1206    <vscale x 4 x i64> %1,1207    iXLen 9,1208    iXLen %2,1209    iXLen 1)1210 1211  ret <vscale x 4 x i64> %a1212}1213 1214define <vscale x 4 x i64> @intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1215; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4i64_nxv4i64:1216; CHECK:       # %bb.0: # %entry1217; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu1218; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t1219; CHECK-NEXT:    ret1220entry:1221  %a = call <vscale x 4 x i64> @llvm.riscv.vslidedown.mask.nxv4i64(1222    <vscale x 4 x i64> %0,1223    <vscale x 4 x i64> %1,1224    iXLen 9,1225    <vscale x 4 x i1> %2,1226    iXLen %3, iXLen 0)1227 1228  ret <vscale x 4 x i64> %a1229}1230 1231define <vscale x 1 x half> @intrinsic_vslidedown_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2, iXLen %3) nounwind {1232; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f16_nxv1f16:1233; CHECK:       # %bb.0: # %entry1234; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma1235; CHECK-NEXT:    vslidedown.vx v8, v9, a01236; CHECK-NEXT:    ret1237entry:1238  %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(1239    <vscale x 1 x half> %0,1240    <vscale x 1 x half> %1,1241    iXLen %2,1242    iXLen %3,1243    iXLen 1)1244 1245  ret <vscale x 1 x half> %a1246}1247 1248define <vscale x 1 x half> @intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1249; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f16_nxv1f16:1250; CHECK:       # %bb.0: # %entry1251; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, mu1252; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1253; CHECK-NEXT:    ret1254entry:1255  %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(1256    <vscale x 1 x half> %0,1257    <vscale x 1 x half> %1,1258    iXLen %2,1259    <vscale x 1 x i1> %3,1260    iXLen %4, iXLen 0)1261 1262  ret <vscale x 1 x half> %a1263}1264 1265define <vscale x 1 x half> @intrinsic_vslidedown_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {1266; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f16_nxv1f16:1267; CHECK:       # %bb.0: # %entry1268; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma1269; CHECK-NEXT:    vslidedown.vi v8, v9, 91270; CHECK-NEXT:    ret1271entry:1272  %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.nxv1f16(1273    <vscale x 1 x half> %0,1274    <vscale x 1 x half> %1,1275    iXLen 9,1276    iXLen %2,1277    iXLen 1)1278 1279  ret <vscale x 1 x half> %a1280}1281 1282define <vscale x 1 x half> @intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1283; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f16_nxv1f16:1284; CHECK:       # %bb.0: # %entry1285; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu1286; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1287; CHECK-NEXT:    ret1288entry:1289  %a = call <vscale x 1 x half> @llvm.riscv.vslidedown.mask.nxv1f16(1290    <vscale x 1 x half> %0,1291    <vscale x 1 x half> %1,1292    iXLen 9,1293    <vscale x 1 x i1> %2,1294    iXLen %3, iXLen 0)1295 1296  ret <vscale x 1 x half> %a1297}1298 1299define <vscale x 2 x half> @intrinsic_vslidedown_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2, iXLen %3) nounwind {1300; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f16_nxv2f16:1301; CHECK:       # %bb.0: # %entry1302; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma1303; CHECK-NEXT:    vslidedown.vx v8, v9, a01304; CHECK-NEXT:    ret1305entry:1306  %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(1307    <vscale x 2 x half> %0,1308    <vscale x 2 x half> %1,1309    iXLen %2,1310    iXLen %3,1311    iXLen 1)1312 1313  ret <vscale x 2 x half> %a1314}1315 1316define <vscale x 2 x half> @intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1317; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f16_nxv2f16:1318; CHECK:       # %bb.0: # %entry1319; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, mu1320; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1321; CHECK-NEXT:    ret1322entry:1323  %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(1324    <vscale x 2 x half> %0,1325    <vscale x 2 x half> %1,1326    iXLen %2,1327    <vscale x 2 x i1> %3,1328    iXLen %4, iXLen 0)1329 1330  ret <vscale x 2 x half> %a1331}1332 1333define <vscale x 2 x half> @intrinsic_vslidedown_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, iXLen %2) nounwind {1334; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f16_nxv2f16:1335; CHECK:       # %bb.0: # %entry1336; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma1337; CHECK-NEXT:    vslidedown.vi v8, v9, 91338; CHECK-NEXT:    ret1339entry:1340  %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.nxv2f16(1341    <vscale x 2 x half> %0,1342    <vscale x 2 x half> %1,1343    iXLen 9,1344    iXLen %2,1345    iXLen 1)1346 1347  ret <vscale x 2 x half> %a1348}1349 1350define <vscale x 2 x half> @intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1351; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f16_nxv2f16:1352; CHECK:       # %bb.0: # %entry1353; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu1354; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1355; CHECK-NEXT:    ret1356entry:1357  %a = call <vscale x 2 x half> @llvm.riscv.vslidedown.mask.nxv2f16(1358    <vscale x 2 x half> %0,1359    <vscale x 2 x half> %1,1360    iXLen 9,1361    <vscale x 2 x i1> %2,1362    iXLen %3, iXLen 0)1363 1364  ret <vscale x 2 x half> %a1365}1366 1367define <vscale x 4 x half> @intrinsic_vslidedown_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2, iXLen %3) nounwind {1368; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f16_nxv4f16:1369; CHECK:       # %bb.0: # %entry1370; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma1371; CHECK-NEXT:    vslidedown.vx v8, v9, a01372; CHECK-NEXT:    ret1373entry:1374  %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(1375    <vscale x 4 x half> %0,1376    <vscale x 4 x half> %1,1377    iXLen %2,1378    iXLen %3,1379    iXLen 1)1380 1381  ret <vscale x 4 x half> %a1382}1383 1384define <vscale x 4 x half> @intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1385; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f16_nxv4f16:1386; CHECK:       # %bb.0: # %entry1387; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu1388; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1389; CHECK-NEXT:    ret1390entry:1391  %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(1392    <vscale x 4 x half> %0,1393    <vscale x 4 x half> %1,1394    iXLen %2,1395    <vscale x 4 x i1> %3,1396    iXLen %4, iXLen 0)1397 1398  ret <vscale x 4 x half> %a1399}1400 1401define <vscale x 4 x half> @intrinsic_vslidedown_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, iXLen %2) nounwind {1402; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f16_nxv4f16:1403; CHECK:       # %bb.0: # %entry1404; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma1405; CHECK-NEXT:    vslidedown.vi v8, v9, 91406; CHECK-NEXT:    ret1407entry:1408  %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.nxv4f16(1409    <vscale x 4 x half> %0,1410    <vscale x 4 x half> %1,1411    iXLen 9,1412    iXLen %2,1413    iXLen 1)1414 1415  ret <vscale x 4 x half> %a1416}1417 1418define <vscale x 4 x half> @intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1419; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f16_nxv4f16:1420; CHECK:       # %bb.0: # %entry1421; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu1422; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1423; CHECK-NEXT:    ret1424entry:1425  %a = call <vscale x 4 x half> @llvm.riscv.vslidedown.mask.nxv4f16(1426    <vscale x 4 x half> %0,1427    <vscale x 4 x half> %1,1428    iXLen 9,1429    <vscale x 4 x i1> %2,1430    iXLen %3, iXLen 0)1431 1432  ret <vscale x 4 x half> %a1433}1434 1435define <vscale x 8 x half> @intrinsic_vslidedown_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2, iXLen %3) nounwind {1436; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f16_nxv8f16:1437; CHECK:       # %bb.0: # %entry1438; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma1439; CHECK-NEXT:    vslidedown.vx v8, v10, a01440; CHECK-NEXT:    ret1441entry:1442  %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(1443    <vscale x 8 x half> %0,1444    <vscale x 8 x half> %1,1445    iXLen %2,1446    iXLen %3,1447    iXLen 1)1448 1449  ret <vscale x 8 x half> %a1450}1451 1452define <vscale x 8 x half> @intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1453; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f16_nxv8f16:1454; CHECK:       # %bb.0: # %entry1455; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, mu1456; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t1457; CHECK-NEXT:    ret1458entry:1459  %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(1460    <vscale x 8 x half> %0,1461    <vscale x 8 x half> %1,1462    iXLen %2,1463    <vscale x 8 x i1> %3,1464    iXLen %4, iXLen 0)1465 1466  ret <vscale x 8 x half> %a1467}1468 1469define <vscale x 8 x half> @intrinsic_vslidedown_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, iXLen %2) nounwind {1470; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f16_nxv8f16:1471; CHECK:       # %bb.0: # %entry1472; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma1473; CHECK-NEXT:    vslidedown.vi v8, v10, 91474; CHECK-NEXT:    ret1475entry:1476  %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.nxv8f16(1477    <vscale x 8 x half> %0,1478    <vscale x 8 x half> %1,1479    iXLen 9,1480    iXLen %2,1481    iXLen 1)1482 1483  ret <vscale x 8 x half> %a1484}1485 1486define <vscale x 8 x half> @intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1487; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f16_nxv8f16:1488; CHECK:       # %bb.0: # %entry1489; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu1490; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t1491; CHECK-NEXT:    ret1492entry:1493  %a = call <vscale x 8 x half> @llvm.riscv.vslidedown.mask.nxv8f16(1494    <vscale x 8 x half> %0,1495    <vscale x 8 x half> %1,1496    iXLen 9,1497    <vscale x 8 x i1> %2,1498    iXLen %3, iXLen 0)1499 1500  ret <vscale x 8 x half> %a1501}1502 1503define <vscale x 16 x half> @intrinsic_vslidedown_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2, iXLen %3) nounwind {1504; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16f16_nxv16f16:1505; CHECK:       # %bb.0: # %entry1506; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma1507; CHECK-NEXT:    vslidedown.vx v8, v12, a01508; CHECK-NEXT:    ret1509entry:1510  %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(1511    <vscale x 16 x half> %0,1512    <vscale x 16 x half> %1,1513    iXLen %2,1514    iXLen %3,1515    iXLen 1)1516 1517  ret <vscale x 16 x half> %a1518}1519 1520define <vscale x 16 x half> @intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1521; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16f16_nxv16f16:1522; CHECK:       # %bb.0: # %entry1523; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, mu1524; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t1525; CHECK-NEXT:    ret1526entry:1527  %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(1528    <vscale x 16 x half> %0,1529    <vscale x 16 x half> %1,1530    iXLen %2,1531    <vscale x 16 x i1> %3,1532    iXLen %4, iXLen 0)1533 1534  ret <vscale x 16 x half> %a1535}1536 1537define <vscale x 16 x half> @intrinsic_vslidedown_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, iXLen %2) nounwind {1538; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16f16_nxv16f16:1539; CHECK:       # %bb.0: # %entry1540; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma1541; CHECK-NEXT:    vslidedown.vi v8, v12, 91542; CHECK-NEXT:    ret1543entry:1544  %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.nxv16f16(1545    <vscale x 16 x half> %0,1546    <vscale x 16 x half> %1,1547    iXLen 9,1548    iXLen %2,1549    iXLen 1)1550 1551  ret <vscale x 16 x half> %a1552}1553 1554define <vscale x 16 x half> @intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {1555; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16f16_nxv16f16:1556; CHECK:       # %bb.0: # %entry1557; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu1558; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t1559; CHECK-NEXT:    ret1560entry:1561  %a = call <vscale x 16 x half> @llvm.riscv.vslidedown.mask.nxv16f16(1562    <vscale x 16 x half> %0,1563    <vscale x 16 x half> %1,1564    iXLen 9,1565    <vscale x 16 x i1> %2,1566    iXLen %3, iXLen 0)1567 1568  ret <vscale x 16 x half> %a1569}1570 1571define <vscale x 1 x float> @intrinsic_vslidedown_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2, iXLen %3) nounwind {1572; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f32_nxv1f32:1573; CHECK:       # %bb.0: # %entry1574; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, ta, ma1575; CHECK-NEXT:    vslidedown.vx v8, v9, a01576; CHECK-NEXT:    ret1577entry:1578  %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(1579    <vscale x 1 x float> %0,1580    <vscale x 1 x float> %1,1581    iXLen %2,1582    iXLen %3,1583    iXLen 1)1584 1585  ret <vscale x 1 x float> %a1586}1587 1588define <vscale x 1 x float> @intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1589; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f32_nxv1f32:1590; CHECK:       # %bb.0: # %entry1591; CHECK-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu1592; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1593; CHECK-NEXT:    ret1594entry:1595  %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(1596    <vscale x 1 x float> %0,1597    <vscale x 1 x float> %1,1598    iXLen %2,1599    <vscale x 1 x i1> %3,1600    iXLen %4, iXLen 0)1601 1602  ret <vscale x 1 x float> %a1603}1604 1605define <vscale x 1 x float> @intrinsic_vslidedown_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, iXLen %2) nounwind {1606; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f32_nxv1f32:1607; CHECK:       # %bb.0: # %entry1608; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, ta, ma1609; CHECK-NEXT:    vslidedown.vi v8, v9, 91610; CHECK-NEXT:    ret1611entry:1612  %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.nxv1f32(1613    <vscale x 1 x float> %0,1614    <vscale x 1 x float> %1,1615    iXLen 9,1616    iXLen %2,1617    iXLen 1)1618 1619  ret <vscale x 1 x float> %a1620}1621 1622define <vscale x 1 x float> @intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1623; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f32_nxv1f32:1624; CHECK:       # %bb.0: # %entry1625; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu1626; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1627; CHECK-NEXT:    ret1628entry:1629  %a = call <vscale x 1 x float> @llvm.riscv.vslidedown.mask.nxv1f32(1630    <vscale x 1 x float> %0,1631    <vscale x 1 x float> %1,1632    iXLen 9,1633    <vscale x 1 x i1> %2,1634    iXLen %3, iXLen 0)1635 1636  ret <vscale x 1 x float> %a1637}1638 1639define <vscale x 2 x float> @intrinsic_vslidedown_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2, iXLen %3) nounwind {1640; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f32_nxv2f32:1641; CHECK:       # %bb.0: # %entry1642; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma1643; CHECK-NEXT:    vslidedown.vx v8, v9, a01644; CHECK-NEXT:    ret1645entry:1646  %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(1647    <vscale x 2 x float> %0,1648    <vscale x 2 x float> %1,1649    iXLen %2,1650    iXLen %3,1651    iXLen 1)1652 1653  ret <vscale x 2 x float> %a1654}1655 1656define <vscale x 2 x float> @intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1657; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f32_nxv2f32:1658; CHECK:       # %bb.0: # %entry1659; CHECK-NEXT:    vsetvli zero, a1, e32, m1, tu, mu1660; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1661; CHECK-NEXT:    ret1662entry:1663  %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(1664    <vscale x 2 x float> %0,1665    <vscale x 2 x float> %1,1666    iXLen %2,1667    <vscale x 2 x i1> %3,1668    iXLen %4, iXLen 0)1669 1670  ret <vscale x 2 x float> %a1671}1672 1673define <vscale x 2 x float> @intrinsic_vslidedown_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, iXLen %2) nounwind {1674; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f32_nxv2f32:1675; CHECK:       # %bb.0: # %entry1676; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma1677; CHECK-NEXT:    vslidedown.vi v8, v9, 91678; CHECK-NEXT:    ret1679entry:1680  %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.nxv2f32(1681    <vscale x 2 x float> %0,1682    <vscale x 2 x float> %1,1683    iXLen 9,1684    iXLen %2,1685    iXLen 1)1686 1687  ret <vscale x 2 x float> %a1688}1689 1690define <vscale x 2 x float> @intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1691; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f32_nxv2f32:1692; CHECK:       # %bb.0: # %entry1693; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu1694; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1695; CHECK-NEXT:    ret1696entry:1697  %a = call <vscale x 2 x float> @llvm.riscv.vslidedown.mask.nxv2f32(1698    <vscale x 2 x float> %0,1699    <vscale x 2 x float> %1,1700    iXLen 9,1701    <vscale x 2 x i1> %2,1702    iXLen %3, iXLen 0)1703 1704  ret <vscale x 2 x float> %a1705}1706 1707define <vscale x 4 x float> @intrinsic_vslidedown_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2, iXLen %3) nounwind {1708; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f32_nxv4f32:1709; CHECK:       # %bb.0: # %entry1710; CHECK-NEXT:    vsetvli zero, a1, e32, m2, ta, ma1711; CHECK-NEXT:    vslidedown.vx v8, v10, a01712; CHECK-NEXT:    ret1713entry:1714  %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(1715    <vscale x 4 x float> %0,1716    <vscale x 4 x float> %1,1717    iXLen %2,1718    iXLen %3,1719    iXLen 1)1720 1721  ret <vscale x 4 x float> %a1722}1723 1724define <vscale x 4 x float> @intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1725; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f32_nxv4f32:1726; CHECK:       # %bb.0: # %entry1727; CHECK-NEXT:    vsetvli zero, a1, e32, m2, tu, mu1728; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t1729; CHECK-NEXT:    ret1730entry:1731  %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(1732    <vscale x 4 x float> %0,1733    <vscale x 4 x float> %1,1734    iXLen %2,1735    <vscale x 4 x i1> %3,1736    iXLen %4, iXLen 0)1737 1738  ret <vscale x 4 x float> %a1739}1740 1741define <vscale x 4 x float> @intrinsic_vslidedown_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, iXLen %2) nounwind {1742; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f32_nxv4f32:1743; CHECK:       # %bb.0: # %entry1744; CHECK-NEXT:    vsetvli zero, a0, e32, m2, ta, ma1745; CHECK-NEXT:    vslidedown.vi v8, v10, 91746; CHECK-NEXT:    ret1747entry:1748  %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.nxv4f32(1749    <vscale x 4 x float> %0,1750    <vscale x 4 x float> %1,1751    iXLen 9,1752    iXLen %2,1753    iXLen 1)1754 1755  ret <vscale x 4 x float> %a1756}1757 1758define <vscale x 4 x float> @intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {1759; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f32_nxv4f32:1760; CHECK:       # %bb.0: # %entry1761; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu1762; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t1763; CHECK-NEXT:    ret1764entry:1765  %a = call <vscale x 4 x float> @llvm.riscv.vslidedown.mask.nxv4f32(1766    <vscale x 4 x float> %0,1767    <vscale x 4 x float> %1,1768    iXLen 9,1769    <vscale x 4 x i1> %2,1770    iXLen %3, iXLen 0)1771 1772  ret <vscale x 4 x float> %a1773}1774 1775define <vscale x 8 x float> @intrinsic_vslidedown_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2, iXLen %3) nounwind {1776; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8f32_nxv8f32:1777; CHECK:       # %bb.0: # %entry1778; CHECK-NEXT:    vsetvli zero, a1, e32, m4, ta, ma1779; CHECK-NEXT:    vslidedown.vx v8, v12, a01780; CHECK-NEXT:    ret1781entry:1782  %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(1783    <vscale x 8 x float> %0,1784    <vscale x 8 x float> %1,1785    iXLen %2,1786    iXLen %3,1787    iXLen 1)1788 1789  ret <vscale x 8 x float> %a1790}1791 1792define <vscale x 8 x float> @intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1793; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8f32_nxv8f32:1794; CHECK:       # %bb.0: # %entry1795; CHECK-NEXT:    vsetvli zero, a1, e32, m4, tu, mu1796; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t1797; CHECK-NEXT:    ret1798entry:1799  %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(1800    <vscale x 8 x float> %0,1801    <vscale x 8 x float> %1,1802    iXLen %2,1803    <vscale x 8 x i1> %3,1804    iXLen %4, iXLen 0)1805 1806  ret <vscale x 8 x float> %a1807}1808 1809define <vscale x 8 x float> @intrinsic_vslidedown_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, iXLen %2) nounwind {1810; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8f32_nxv8f32:1811; CHECK:       # %bb.0: # %entry1812; CHECK-NEXT:    vsetvli zero, a0, e32, m4, ta, ma1813; CHECK-NEXT:    vslidedown.vi v8, v12, 91814; CHECK-NEXT:    ret1815entry:1816  %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.nxv8f32(1817    <vscale x 8 x float> %0,1818    <vscale x 8 x float> %1,1819    iXLen 9,1820    iXLen %2,1821    iXLen 1)1822 1823  ret <vscale x 8 x float> %a1824}1825 1826define <vscale x 8 x float> @intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {1827; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8f32_nxv8f32:1828; CHECK:       # %bb.0: # %entry1829; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu1830; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t1831; CHECK-NEXT:    ret1832entry:1833  %a = call <vscale x 8 x float> @llvm.riscv.vslidedown.mask.nxv8f32(1834    <vscale x 8 x float> %0,1835    <vscale x 8 x float> %1,1836    iXLen 9,1837    <vscale x 8 x i1> %2,1838    iXLen %3, iXLen 0)1839 1840  ret <vscale x 8 x float> %a1841}1842 1843define <vscale x 1 x double> @intrinsic_vslidedown_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2, iXLen %3) nounwind {1844; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1f64_nxv1f64:1845; CHECK:       # %bb.0: # %entry1846; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma1847; CHECK-NEXT:    vslidedown.vx v8, v9, a01848; CHECK-NEXT:    ret1849entry:1850  %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(1851    <vscale x 1 x double> %0,1852    <vscale x 1 x double> %1,1853    iXLen %2,1854    iXLen %3,1855    iXLen 1)1856 1857  ret <vscale x 1 x double> %a1858}1859 1860define <vscale x 1 x double> @intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1861; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1f64_nxv1f64:1862; CHECK:       # %bb.0: # %entry1863; CHECK-NEXT:    vsetvli zero, a1, e64, m1, tu, mu1864; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t1865; CHECK-NEXT:    ret1866entry:1867  %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(1868    <vscale x 1 x double> %0,1869    <vscale x 1 x double> %1,1870    iXLen %2,1871    <vscale x 1 x i1> %3,1872    iXLen %4, iXLen 0)1873 1874  ret <vscale x 1 x double> %a1875}1876 1877define <vscale x 1 x double> @intrinsic_vslidedown_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, iXLen %2) nounwind {1878; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1f64_nxv1f64:1879; CHECK:       # %bb.0: # %entry1880; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma1881; CHECK-NEXT:    vslidedown.vi v8, v9, 91882; CHECK-NEXT:    ret1883entry:1884  %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.nxv1f64(1885    <vscale x 1 x double> %0,1886    <vscale x 1 x double> %1,1887    iXLen 9,1888    iXLen %2,1889    iXLen 1)1890 1891  ret <vscale x 1 x double> %a1892}1893 1894define <vscale x 1 x double> @intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {1895; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1f64_nxv1f64:1896; CHECK:       # %bb.0: # %entry1897; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu1898; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t1899; CHECK-NEXT:    ret1900entry:1901  %a = call <vscale x 1 x double> @llvm.riscv.vslidedown.mask.nxv1f64(1902    <vscale x 1 x double> %0,1903    <vscale x 1 x double> %1,1904    iXLen 9,1905    <vscale x 1 x i1> %2,1906    iXLen %3, iXLen 0)1907 1908  ret <vscale x 1 x double> %a1909}1910 1911define <vscale x 2 x double> @intrinsic_vslidedown_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2, iXLen %3) nounwind {1912; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2f64_nxv2f64:1913; CHECK:       # %bb.0: # %entry1914; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma1915; CHECK-NEXT:    vslidedown.vx v8, v10, a01916; CHECK-NEXT:    ret1917entry:1918  %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(1919    <vscale x 2 x double> %0,1920    <vscale x 2 x double> %1,1921    iXLen %2,1922    iXLen %3,1923    iXLen 1)1924 1925  ret <vscale x 2 x double> %a1926}1927 1928define <vscale x 2 x double> @intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1929; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2f64_nxv2f64:1930; CHECK:       # %bb.0: # %entry1931; CHECK-NEXT:    vsetvli zero, a1, e64, m2, tu, mu1932; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t1933; CHECK-NEXT:    ret1934entry:1935  %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(1936    <vscale x 2 x double> %0,1937    <vscale x 2 x double> %1,1938    iXLen %2,1939    <vscale x 2 x i1> %3,1940    iXLen %4, iXLen 0)1941 1942  ret <vscale x 2 x double> %a1943}1944 1945define <vscale x 2 x double> @intrinsic_vslidedown_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, iXLen %2) nounwind {1946; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2f64_nxv2f64:1947; CHECK:       # %bb.0: # %entry1948; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma1949; CHECK-NEXT:    vslidedown.vi v8, v10, 91950; CHECK-NEXT:    ret1951entry:1952  %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.nxv2f64(1953    <vscale x 2 x double> %0,1954    <vscale x 2 x double> %1,1955    iXLen 9,1956    iXLen %2,1957    iXLen 1)1958 1959  ret <vscale x 2 x double> %a1960}1961 1962define <vscale x 2 x double> @intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {1963; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2f64_nxv2f64:1964; CHECK:       # %bb.0: # %entry1965; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, mu1966; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t1967; CHECK-NEXT:    ret1968entry:1969  %a = call <vscale x 2 x double> @llvm.riscv.vslidedown.mask.nxv2f64(1970    <vscale x 2 x double> %0,1971    <vscale x 2 x double> %1,1972    iXLen 9,1973    <vscale x 2 x i1> %2,1974    iXLen %3, iXLen 0)1975 1976  ret <vscale x 2 x double> %a1977}1978 1979define <vscale x 4 x double> @intrinsic_vslidedown_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2, iXLen %3) nounwind {1980; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4f64_nxv4f64:1981; CHECK:       # %bb.0: # %entry1982; CHECK-NEXT:    vsetvli zero, a1, e64, m4, ta, ma1983; CHECK-NEXT:    vslidedown.vx v8, v12, a01984; CHECK-NEXT:    ret1985entry:1986  %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(1987    <vscale x 4 x double> %0,1988    <vscale x 4 x double> %1,1989    iXLen %2,1990    iXLen %3,1991    iXLen 1)1992 1993  ret <vscale x 4 x double> %a1994}1995 1996define <vscale x 4 x double> @intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1997; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4f64_nxv4f64:1998; CHECK:       # %bb.0: # %entry1999; CHECK-NEXT:    vsetvli zero, a1, e64, m4, tu, mu2000; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t2001; CHECK-NEXT:    ret2002entry:2003  %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(2004    <vscale x 4 x double> %0,2005    <vscale x 4 x double> %1,2006    iXLen %2,2007    <vscale x 4 x i1> %3,2008    iXLen %4, iXLen 0)2009 2010  ret <vscale x 4 x double> %a2011}2012 2013define <vscale x 4 x double> @intrinsic_vslidedown_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, iXLen %2) nounwind {2014; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4f64_nxv4f64:2015; CHECK:       # %bb.0: # %entry2016; CHECK-NEXT:    vsetvli zero, a0, e64, m4, ta, ma2017; CHECK-NEXT:    vslidedown.vi v8, v12, 92018; CHECK-NEXT:    ret2019entry:2020  %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.nxv4f64(2021    <vscale x 4 x double> %0,2022    <vscale x 4 x double> %1,2023    iXLen 9,2024    iXLen %2,2025    iXLen 1)2026 2027  ret <vscale x 4 x double> %a2028}2029 2030define <vscale x 4 x double> @intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2031; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4f64_nxv4f64:2032; CHECK:       # %bb.0: # %entry2033; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu2034; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t2035; CHECK-NEXT:    ret2036entry:2037  %a = call <vscale x 4 x double> @llvm.riscv.vslidedown.mask.nxv4f64(2038    <vscale x 4 x double> %0,2039    <vscale x 4 x double> %1,2040    iXLen 9,2041    <vscale x 4 x i1> %2,2042    iXLen %3, iXLen 0)2043 2044  ret <vscale x 4 x double> %a2045}2046 2047define <vscale x 1 x bfloat> @intrinsic_vslidedown_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, iXLen %3) nounwind {2048; CHECK-LABEL: intrinsic_vslidedown_vx_nxv1bf16_nxv1bf16:2049; CHECK:       # %bb.0: # %entry2050; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, ta, ma2051; CHECK-NEXT:    vslidedown.vx v8, v9, a02052; CHECK-NEXT:    ret2053entry:2054  %a = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16(2055    <vscale x 1 x bfloat> %0,2056    <vscale x 1 x bfloat> %1,2057    iXLen %2,2058    iXLen %3,2059    iXLen 1)2060 2061  ret <vscale x 1 x bfloat> %a2062}2063 2064define <vscale x 1 x bfloat> @intrinsic_vslidedown_mask_vx_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {2065; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv1bf16_nxv1bf16:2066; CHECK:       # %bb.0: # %entry2067; CHECK-NEXT:    vsetvli zero, a1, e16, mf4, tu, mu2068; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t2069; CHECK-NEXT:    ret2070entry:2071  %a = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16(2072    <vscale x 1 x bfloat> %0,2073    <vscale x 1 x bfloat> %1,2074    iXLen %2,2075    <vscale x 1 x i1> %3,2076    iXLen %4, iXLen 0)2077 2078  ret <vscale x 1 x bfloat> %a2079}2080 2081define <vscale x 1 x bfloat> @intrinsic_vslidedown_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, iXLen %2) nounwind {2082; CHECK-LABEL: intrinsic_vslidedown_vi_nxv1bf16_nxv1bf16:2083; CHECK:       # %bb.0: # %entry2084; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma2085; CHECK-NEXT:    vslidedown.vi v8, v9, 92086; CHECK-NEXT:    ret2087entry:2088  %a = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.nxv1bf16(2089    <vscale x 1 x bfloat> %0,2090    <vscale x 1 x bfloat> %1,2091    iXLen 9,2092    iXLen %2,2093    iXLen 1)2094 2095  ret <vscale x 1 x bfloat> %a2096}2097 2098define <vscale x 1 x bfloat> @intrinsic_vslidedown_mask_vi_nxv1bf16_nxv1bf16(<vscale x 1 x bfloat> %0, <vscale x 1 x bfloat> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {2099; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv1bf16_nxv1bf16:2100; CHECK:       # %bb.0: # %entry2101; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu2102; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t2103; CHECK-NEXT:    ret2104entry:2105  %a = call <vscale x 1 x bfloat> @llvm.riscv.vslidedown.mask.nxv1bf16(2106    <vscale x 1 x bfloat> %0,2107    <vscale x 1 x bfloat> %1,2108    iXLen 9,2109    <vscale x 1 x i1> %2,2110    iXLen %3, iXLen 0)2111 2112  ret <vscale x 1 x bfloat> %a2113}2114 2115define <vscale x 2 x bfloat> @intrinsic_vslidedown_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2, iXLen %3) nounwind {2116; CHECK-LABEL: intrinsic_vslidedown_vx_nxv2bf16_nxv2bf16:2117; CHECK:       # %bb.0: # %entry2118; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, ta, ma2119; CHECK-NEXT:    vslidedown.vx v8, v9, a02120; CHECK-NEXT:    ret2121entry:2122  %a = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16(2123    <vscale x 2 x bfloat> %0,2124    <vscale x 2 x bfloat> %1,2125    iXLen %2,2126    iXLen %3,2127    iXLen 1)2128 2129  ret <vscale x 2 x bfloat> %a2130}2131 2132define <vscale x 2 x bfloat> @intrinsic_vslidedown_mask_vx_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {2133; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv2bf16_nxv2bf16:2134; CHECK:       # %bb.0: # %entry2135; CHECK-NEXT:    vsetvli zero, a1, e16, mf2, tu, mu2136; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t2137; CHECK-NEXT:    ret2138entry:2139  %a = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16(2140    <vscale x 2 x bfloat> %0,2141    <vscale x 2 x bfloat> %1,2142    iXLen %2,2143    <vscale x 2 x i1> %3,2144    iXLen %4, iXLen 0)2145 2146  ret <vscale x 2 x bfloat> %a2147}2148 2149define <vscale x 2 x bfloat> @intrinsic_vslidedown_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, iXLen %2) nounwind {2150; CHECK-LABEL: intrinsic_vslidedown_vi_nxv2bf16_nxv2bf16:2151; CHECK:       # %bb.0: # %entry2152; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma2153; CHECK-NEXT:    vslidedown.vi v8, v9, 92154; CHECK-NEXT:    ret2155entry:2156  %a = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.nxv2bf16(2157    <vscale x 2 x bfloat> %0,2158    <vscale x 2 x bfloat> %1,2159    iXLen 9,2160    iXLen %2,2161    iXLen 1)2162 2163  ret <vscale x 2 x bfloat> %a2164}2165 2166define <vscale x 2 x bfloat> @intrinsic_vslidedown_mask_vi_nxv2bf16_nxv2bf16(<vscale x 2 x bfloat> %0, <vscale x 2 x bfloat> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {2167; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv2bf16_nxv2bf16:2168; CHECK:       # %bb.0: # %entry2169; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu2170; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t2171; CHECK-NEXT:    ret2172entry:2173  %a = call <vscale x 2 x bfloat> @llvm.riscv.vslidedown.mask.nxv2bf16(2174    <vscale x 2 x bfloat> %0,2175    <vscale x 2 x bfloat> %1,2176    iXLen 9,2177    <vscale x 2 x i1> %2,2178    iXLen %3, iXLen 0)2179 2180  ret <vscale x 2 x bfloat> %a2181}2182 2183define <vscale x 4 x bfloat> @intrinsic_vslidedown_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2, iXLen %3) nounwind {2184; CHECK-LABEL: intrinsic_vslidedown_vx_nxv4bf16_nxv4bf16:2185; CHECK:       # %bb.0: # %entry2186; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma2187; CHECK-NEXT:    vslidedown.vx v8, v9, a02188; CHECK-NEXT:    ret2189entry:2190  %a = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16(2191    <vscale x 4 x bfloat> %0,2192    <vscale x 4 x bfloat> %1,2193    iXLen %2,2194    iXLen %3,2195    iXLen 1)2196 2197  ret <vscale x 4 x bfloat> %a2198}2199 2200define <vscale x 4 x bfloat> @intrinsic_vslidedown_mask_vx_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {2201; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv4bf16_nxv4bf16:2202; CHECK:       # %bb.0: # %entry2203; CHECK-NEXT:    vsetvli zero, a1, e16, m1, tu, mu2204; CHECK-NEXT:    vslidedown.vx v8, v9, a0, v0.t2205; CHECK-NEXT:    ret2206entry:2207  %a = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16(2208    <vscale x 4 x bfloat> %0,2209    <vscale x 4 x bfloat> %1,2210    iXLen %2,2211    <vscale x 4 x i1> %3,2212    iXLen %4, iXLen 0)2213 2214  ret <vscale x 4 x bfloat> %a2215}2216 2217define <vscale x 4 x bfloat> @intrinsic_vslidedown_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, iXLen %2) nounwind {2218; CHECK-LABEL: intrinsic_vslidedown_vi_nxv4bf16_nxv4bf16:2219; CHECK:       # %bb.0: # %entry2220; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma2221; CHECK-NEXT:    vslidedown.vi v8, v9, 92222; CHECK-NEXT:    ret2223entry:2224  %a = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.nxv4bf16(2225    <vscale x 4 x bfloat> %0,2226    <vscale x 4 x bfloat> %1,2227    iXLen 9,2228    iXLen %2,2229    iXLen 1)2230 2231  ret <vscale x 4 x bfloat> %a2232}2233 2234define <vscale x 4 x bfloat> @intrinsic_vslidedown_mask_vi_nxv4bf16_nxv4bf16(<vscale x 4 x bfloat> %0, <vscale x 4 x bfloat> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {2235; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv4bf16_nxv4bf16:2236; CHECK:       # %bb.0: # %entry2237; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu2238; CHECK-NEXT:    vslidedown.vi v8, v9, 9, v0.t2239; CHECK-NEXT:    ret2240entry:2241  %a = call <vscale x 4 x bfloat> @llvm.riscv.vslidedown.mask.nxv4bf16(2242    <vscale x 4 x bfloat> %0,2243    <vscale x 4 x bfloat> %1,2244    iXLen 9,2245    <vscale x 4 x i1> %2,2246    iXLen %3, iXLen 0)2247 2248  ret <vscale x 4 x bfloat> %a2249}2250 2251define <vscale x 8 x bfloat> @intrinsic_vslidedown_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2, iXLen %3) nounwind {2252; CHECK-LABEL: intrinsic_vslidedown_vx_nxv8bf16_nxv8bf16:2253; CHECK:       # %bb.0: # %entry2254; CHECK-NEXT:    vsetvli zero, a1, e16, m2, ta, ma2255; CHECK-NEXT:    vslidedown.vx v8, v10, a02256; CHECK-NEXT:    ret2257entry:2258  %a = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16(2259    <vscale x 8 x bfloat> %0,2260    <vscale x 8 x bfloat> %1,2261    iXLen %2,2262    iXLen %3,2263    iXLen 1)2264 2265  ret <vscale x 8 x bfloat> %a2266}2267 2268define <vscale x 8 x bfloat> @intrinsic_vslidedown_mask_vx_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {2269; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv8bf16_nxv8bf16:2270; CHECK:       # %bb.0: # %entry2271; CHECK-NEXT:    vsetvli zero, a1, e16, m2, tu, mu2272; CHECK-NEXT:    vslidedown.vx v8, v10, a0, v0.t2273; CHECK-NEXT:    ret2274entry:2275  %a = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.mask.nxv8bf16(2276    <vscale x 8 x bfloat> %0,2277    <vscale x 8 x bfloat> %1,2278    iXLen %2,2279    <vscale x 8 x i1> %3,2280    iXLen %4, iXLen 0)2281 2282  ret <vscale x 8 x bfloat> %a2283}2284 2285define <vscale x 8 x bfloat> @intrinsic_vslidedown_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, iXLen %2) nounwind {2286; CHECK-LABEL: intrinsic_vslidedown_vi_nxv8bf16_nxv8bf16:2287; CHECK:       # %bb.0: # %entry2288; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma2289; CHECK-NEXT:    vslidedown.vi v8, v10, 92290; CHECK-NEXT:    ret2291entry:2292  %a = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.nxv8bf16(2293    <vscale x 8 x bfloat> %0,2294    <vscale x 8 x bfloat> %1,2295    iXLen 9,2296    iXLen %2,2297    iXLen 1)2298 2299  ret <vscale x 8 x bfloat> %a2300}2301 2302define <vscale x 8 x bfloat> @intrinsic_vslidedown_mask_vi_nxv8bf16_nxv8bf16(<vscale x 8 x bfloat> %0, <vscale x 8 x bfloat> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {2303; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv8bf16_nxv8bf16:2304; CHECK:       # %bb.0: # %entry2305; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu2306; CHECK-NEXT:    vslidedown.vi v8, v10, 9, v0.t2307; CHECK-NEXT:    ret2308entry:2309  %a = call <vscale x 8 x bfloat> @llvm.riscv.vslidedown.mask.nxv8bf16(2310    <vscale x 8 x bfloat> %0,2311    <vscale x 8 x bfloat> %1,2312    iXLen 9,2313    <vscale x 8 x i1> %2,2314    iXLen %3, iXLen 0)2315 2316  ret <vscale x 8 x bfloat> %a2317}2318 2319define <vscale x 16 x bfloat> @intrinsic_vslidedown_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2, iXLen %3) nounwind {2320; CHECK-LABEL: intrinsic_vslidedown_vx_nxv16bf16_nxv16bf16:2321; CHECK:       # %bb.0: # %entry2322; CHECK-NEXT:    vsetvli zero, a1, e16, m4, ta, ma2323; CHECK-NEXT:    vslidedown.vx v8, v12, a02324; CHECK-NEXT:    ret2325entry:2326  %a = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16(2327    <vscale x 16 x bfloat> %0,2328    <vscale x 16 x bfloat> %1,2329    iXLen %2,2330    iXLen %3,2331    iXLen 1)2332 2333  ret <vscale x 16 x bfloat> %a2334}2335 2336define <vscale x 16 x bfloat> @intrinsic_vslidedown_mask_vx_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {2337; CHECK-LABEL: intrinsic_vslidedown_mask_vx_nxv16bf16_nxv16bf16:2338; CHECK:       # %bb.0: # %entry2339; CHECK-NEXT:    vsetvli zero, a1, e16, m4, tu, mu2340; CHECK-NEXT:    vslidedown.vx v8, v12, a0, v0.t2341; CHECK-NEXT:    ret2342entry:2343  %a = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.mask.nxv16bf16(2344    <vscale x 16 x bfloat> %0,2345    <vscale x 16 x bfloat> %1,2346    iXLen %2,2347    <vscale x 16 x i1> %3,2348    iXLen %4, iXLen 0)2349 2350  ret <vscale x 16 x bfloat> %a2351}2352 2353define <vscale x 16 x bfloat> @intrinsic_vslidedown_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, iXLen %2) nounwind {2354; CHECK-LABEL: intrinsic_vslidedown_vi_nxv16bf16_nxv16bf16:2355; CHECK:       # %bb.0: # %entry2356; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma2357; CHECK-NEXT:    vslidedown.vi v8, v12, 92358; CHECK-NEXT:    ret2359entry:2360  %a = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.nxv16bf16(2361    <vscale x 16 x bfloat> %0,2362    <vscale x 16 x bfloat> %1,2363    iXLen 9,2364    iXLen %2,2365    iXLen 1)2366 2367  ret <vscale x 16 x bfloat> %a2368}2369 2370define <vscale x 16 x bfloat> @intrinsic_vslidedown_mask_vi_nxv16bf16_nxv16bf16(<vscale x 16 x bfloat> %0, <vscale x 16 x bfloat> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {2371; CHECK-LABEL: intrinsic_vslidedown_mask_vi_nxv16bf16_nxv16bf16:2372; CHECK:       # %bb.0: # %entry2373; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu2374; CHECK-NEXT:    vslidedown.vi v8, v12, 9, v0.t2375; CHECK-NEXT:    ret2376entry:2377  %a = call <vscale x 16 x bfloat> @llvm.riscv.vslidedown.mask.nxv16bf16(2378    <vscale x 16 x bfloat> %0,2379    <vscale x 16 x bfloat> %1,2380    iXLen 9,2381    <vscale x 16 x i1> %2,2382    iXLen %3, iXLen 0)2383 2384  ret <vscale x 16 x bfloat> %a2385}2386