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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s6 7define void @intrinsic_vsm_v_nxv1i1(<vscale x 1 x i1> %0, ptr %1, iXLen %2) nounwind {8; CHECK-LABEL: intrinsic_vsm_v_nxv1i1:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vsm.v v0, (a0)12; CHECK-NEXT: ret13entry:14 call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %0, ptr %1, iXLen %2)15 ret void16}17 18define void @intrinsic_vsm_v_nxv2i1(<vscale x 2 x i1> %0, ptr %1, iXLen %2) nounwind {19; CHECK-LABEL: intrinsic_vsm_v_nxv2i1:20; CHECK: # %bb.0: # %entry21; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma22; CHECK-NEXT: vsm.v v0, (a0)23; CHECK-NEXT: ret24entry:25 call void @llvm.riscv.vsm.nxv2i1(<vscale x 2 x i1> %0, ptr %1, iXLen %2)26 ret void27}28 29define void @intrinsic_vsm_v_nxv4i1(<vscale x 4 x i1> %0, ptr %1, iXLen %2) nounwind {30; CHECK-LABEL: intrinsic_vsm_v_nxv4i1:31; CHECK: # %bb.0: # %entry32; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma33; CHECK-NEXT: vsm.v v0, (a0)34; CHECK-NEXT: ret35entry:36 call void @llvm.riscv.vsm.nxv4i1(<vscale x 4 x i1> %0, ptr %1, iXLen %2)37 ret void38}39 40define void @intrinsic_vsm_v_nxv8i1(<vscale x 8 x i1> %0, ptr %1, iXLen %2) nounwind {41; CHECK-LABEL: intrinsic_vsm_v_nxv8i1:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma44; CHECK-NEXT: vsm.v v0, (a0)45; CHECK-NEXT: ret46entry:47 call void @llvm.riscv.vsm.nxv8i1(<vscale x 8 x i1> %0, ptr %1, iXLen %2)48 ret void49}50 51define void @intrinsic_vsm_v_nxv16i1(<vscale x 16 x i1> %0, ptr %1, iXLen %2) nounwind {52; CHECK-LABEL: intrinsic_vsm_v_nxv16i1:53; CHECK: # %bb.0: # %entry54; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma55; CHECK-NEXT: vsm.v v0, (a0)56; CHECK-NEXT: ret57entry:58 call void @llvm.riscv.vsm.nxv16i1(<vscale x 16 x i1> %0, ptr %1, iXLen %2)59 ret void60}61 62define void @intrinsic_vsm_v_nxv32i1(<vscale x 32 x i1> %0, ptr %1, iXLen %2) nounwind {63; CHECK-LABEL: intrinsic_vsm_v_nxv32i1:64; CHECK: # %bb.0: # %entry65; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma66; CHECK-NEXT: vsm.v v0, (a0)67; CHECK-NEXT: ret68entry:69 call void @llvm.riscv.vsm.nxv32i1(<vscale x 32 x i1> %0, ptr %1, iXLen %2)70 ret void71}72 73define void @intrinsic_vsm_v_nxv64i1(<vscale x 64 x i1> %0, ptr %1, iXLen %2) nounwind {74; CHECK-LABEL: intrinsic_vsm_v_nxv64i1:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma77; CHECK-NEXT: vsm.v v0, (a0)78; CHECK-NEXT: ret79entry:80 call void @llvm.riscv.vsm.nxv64i1(<vscale x 64 x i1> %0, ptr %1, iXLen %2)81 ret void82}83 84; Make sure we can use the vsetvli from the producing instruction.85define void @test_vsetvli_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, ptr %2, iXLen %3) nounwind {86; CHECK-LABEL: test_vsetvli_i16:87; CHECK: # %bb.0: # %entry88; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma89; CHECK-NEXT: vmseq.vv v8, v8, v990; CHECK-NEXT: vsm.v v8, (a0)91; CHECK-NEXT: ret92entry:93 %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(94 <vscale x 1 x i16> %0,95 <vscale x 1 x i16> %1,96 iXLen %3)97 call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, ptr %2, iXLen %3)98 ret void99}100 101define void @test_vsetvli_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, ptr %2, iXLen %3) nounwind {102; CHECK-LABEL: test_vsetvli_i32:103; CHECK: # %bb.0: # %entry104; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma105; CHECK-NEXT: vmseq.vv v8, v8, v9106; CHECK-NEXT: vsm.v v8, (a0)107; CHECK-NEXT: ret108entry:109 %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(110 <vscale x 1 x i32> %0,111 <vscale x 1 x i32> %1,112 iXLen %3)113 call void @llvm.riscv.vsm.nxv1i1(<vscale x 1 x i1> %a, ptr %2, iXLen %3)114 ret void115}116