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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV324; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV646; RUN: sed 's/iXLen/i64/g' %s | not --crash llc -mtriple=riscv64 \7; RUN: -mattr=+zve64d 2>&1 | FileCheck %s --check-prefixes=ZVE64D8 9; ZVE64D: LLVM ERROR: Cannot select: intrinsic %llvm.riscv.vsmul10 11define <vscale x 1 x i8> @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {12; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8:13; CHECK: # %bb.0: # %entry14; CHECK-NEXT: csrwi vxrm, 015; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma16; CHECK-NEXT: vsmul.vv v8, v8, v917; CHECK-NEXT: ret18entry:19 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.nxv1i8(20 <vscale x 1 x i8> poison,21 <vscale x 1 x i8> %0,22 <vscale x 1 x i8> %1,23 iXLen 0, iXLen %2)24 25 ret <vscale x 1 x i8> %a26}27 28define <vscale x 1 x i8> @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {29; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8:30; CHECK: # %bb.0: # %entry31; CHECK-NEXT: csrwi vxrm, 032; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu33; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t34; CHECK-NEXT: ret35entry:36 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8(37 <vscale x 1 x i8> %0,38 <vscale x 1 x i8> %1,39 <vscale x 1 x i8> %2,40 <vscale x 1 x i1> %3,41 iXLen 0, iXLen %4, iXLen 1)42 43 ret <vscale x 1 x i8> %a44}45 46define <vscale x 2 x i8> @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {47; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8:48; CHECK: # %bb.0: # %entry49; CHECK-NEXT: csrwi vxrm, 050; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma51; CHECK-NEXT: vsmul.vv v8, v8, v952; CHECK-NEXT: ret53entry:54 %a = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.nxv2i8(55 <vscale x 2 x i8> poison,56 <vscale x 2 x i8> %0,57 <vscale x 2 x i8> %1,58 iXLen 0, iXLen %2)59 60 ret <vscale x 2 x i8> %a61}62 63define <vscale x 2 x i8> @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {64; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8:65; CHECK: # %bb.0: # %entry66; CHECK-NEXT: csrwi vxrm, 067; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu68; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t69; CHECK-NEXT: ret70entry:71 %a = call <vscale x 2 x i8> @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8(72 <vscale x 2 x i8> %0,73 <vscale x 2 x i8> %1,74 <vscale x 2 x i8> %2,75 <vscale x 2 x i1> %3,76 iXLen 0, iXLen %4, iXLen 1)77 78 ret <vscale x 2 x i8> %a79}80 81define <vscale x 4 x i8> @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {82; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8:83; CHECK: # %bb.0: # %entry84; CHECK-NEXT: csrwi vxrm, 085; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma86; CHECK-NEXT: vsmul.vv v8, v8, v987; CHECK-NEXT: ret88entry:89 %a = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.nxv4i8(90 <vscale x 4 x i8> poison,91 <vscale x 4 x i8> %0,92 <vscale x 4 x i8> %1,93 iXLen 0, iXLen %2)94 95 ret <vscale x 4 x i8> %a96}97 98define <vscale x 4 x i8> @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {99; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8:100; CHECK: # %bb.0: # %entry101; CHECK-NEXT: csrwi vxrm, 0102; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu103; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t104; CHECK-NEXT: ret105entry:106 %a = call <vscale x 4 x i8> @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8(107 <vscale x 4 x i8> %0,108 <vscale x 4 x i8> %1,109 <vscale x 4 x i8> %2,110 <vscale x 4 x i1> %3,111 iXLen 0, iXLen %4, iXLen 1)112 113 ret <vscale x 4 x i8> %a114}115 116define <vscale x 8 x i8> @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {117; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8:118; CHECK: # %bb.0: # %entry119; CHECK-NEXT: csrwi vxrm, 0120; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma121; CHECK-NEXT: vsmul.vv v8, v8, v9122; CHECK-NEXT: ret123entry:124 %a = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.nxv8i8(125 <vscale x 8 x i8> poison,126 <vscale x 8 x i8> %0,127 <vscale x 8 x i8> %1,128 iXLen 0, iXLen %2)129 130 ret <vscale x 8 x i8> %a131}132 133define <vscale x 8 x i8> @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {134; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8:135; CHECK: # %bb.0: # %entry136; CHECK-NEXT: csrwi vxrm, 0137; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu138; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t139; CHECK-NEXT: ret140entry:141 %a = call <vscale x 8 x i8> @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8(142 <vscale x 8 x i8> %0,143 <vscale x 8 x i8> %1,144 <vscale x 8 x i8> %2,145 <vscale x 8 x i1> %3,146 iXLen 0, iXLen %4, iXLen 1)147 148 ret <vscale x 8 x i8> %a149}150 151define <vscale x 16 x i8> @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {152; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8:153; CHECK: # %bb.0: # %entry154; CHECK-NEXT: csrwi vxrm, 0155; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma156; CHECK-NEXT: vsmul.vv v8, v8, v10157; CHECK-NEXT: ret158entry:159 %a = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.nxv16i8(160 <vscale x 16 x i8> poison,161 <vscale x 16 x i8> %0,162 <vscale x 16 x i8> %1,163 iXLen 0, iXLen %2)164 165 ret <vscale x 16 x i8> %a166}167 168define <vscale x 16 x i8> @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {169; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8:170; CHECK: # %bb.0: # %entry171; CHECK-NEXT: csrwi vxrm, 0172; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu173; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t174; CHECK-NEXT: ret175entry:176 %a = call <vscale x 16 x i8> @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8(177 <vscale x 16 x i8> %0,178 <vscale x 16 x i8> %1,179 <vscale x 16 x i8> %2,180 <vscale x 16 x i1> %3,181 iXLen 0, iXLen %4, iXLen 1)182 183 ret <vscale x 16 x i8> %a184}185 186define <vscale x 32 x i8> @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, iXLen %2) nounwind {187; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8:188; CHECK: # %bb.0: # %entry189; CHECK-NEXT: csrwi vxrm, 0190; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma191; CHECK-NEXT: vsmul.vv v8, v8, v12192; CHECK-NEXT: ret193entry:194 %a = call <vscale x 32 x i8> @llvm.riscv.vsmul.nxv32i8.nxv32i8(195 <vscale x 32 x i8> poison,196 <vscale x 32 x i8> %0,197 <vscale x 32 x i8> %1,198 iXLen 0, iXLen %2)199 200 ret <vscale x 32 x i8> %a201}202 203define <vscale x 32 x i8> @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {204; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8:205; CHECK: # %bb.0: # %entry206; CHECK-NEXT: csrwi vxrm, 0207; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu208; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t209; CHECK-NEXT: ret210entry:211 %a = call <vscale x 32 x i8> @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8(212 <vscale x 32 x i8> %0,213 <vscale x 32 x i8> %1,214 <vscale x 32 x i8> %2,215 <vscale x 32 x i1> %3,216 iXLen 0, iXLen %4, iXLen 1)217 218 ret <vscale x 32 x i8> %a219}220 221define <vscale x 64 x i8> @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, iXLen %2) nounwind {222; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: csrwi vxrm, 0225; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma226; CHECK-NEXT: vsmul.vv v8, v8, v16227; CHECK-NEXT: ret228entry:229 %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.nxv64i8.nxv64i8(230 <vscale x 64 x i8> poison,231 <vscale x 64 x i8> %0,232 <vscale x 64 x i8> %1,233 iXLen 0, iXLen %2)234 235 ret <vscale x 64 x i8> %a236}237 238define <vscale x 64 x i8> @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {239; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vl8r.v v24, (a0)242; CHECK-NEXT: csrwi vxrm, 0243; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu244; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t245; CHECK-NEXT: ret246entry:247 %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.nxv64i8(248 <vscale x 64 x i8> %0,249 <vscale x 64 x i8> %1,250 <vscale x 64 x i8> %2,251 <vscale x 64 x i1> %3,252 iXLen 0, iXLen %4, iXLen 1)253 254 ret <vscale x 64 x i8> %a255}256 257define <vscale x 1 x i16> @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, iXLen %2) nounwind {258; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16:259; CHECK: # %bb.0: # %entry260; CHECK-NEXT: csrwi vxrm, 0261; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma262; CHECK-NEXT: vsmul.vv v8, v8, v9263; CHECK-NEXT: ret264entry:265 %a = call <vscale x 1 x i16> @llvm.riscv.vsmul.nxv1i16.nxv1i16(266 <vscale x 1 x i16> poison,267 <vscale x 1 x i16> %0,268 <vscale x 1 x i16> %1,269 iXLen 0, iXLen %2)270 271 ret <vscale x 1 x i16> %a272}273 274define <vscale x 1 x i16> @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {275; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16:276; CHECK: # %bb.0: # %entry277; CHECK-NEXT: csrwi vxrm, 0278; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu279; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t280; CHECK-NEXT: ret281entry:282 %a = call <vscale x 1 x i16> @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16(283 <vscale x 1 x i16> %0,284 <vscale x 1 x i16> %1,285 <vscale x 1 x i16> %2,286 <vscale x 1 x i1> %3,287 iXLen 0, iXLen %4, iXLen 1)288 289 ret <vscale x 1 x i16> %a290}291 292define <vscale x 2 x i16> @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, iXLen %2) nounwind {293; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16:294; CHECK: # %bb.0: # %entry295; CHECK-NEXT: csrwi vxrm, 0296; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma297; CHECK-NEXT: vsmul.vv v8, v8, v9298; CHECK-NEXT: ret299entry:300 %a = call <vscale x 2 x i16> @llvm.riscv.vsmul.nxv2i16.nxv2i16(301 <vscale x 2 x i16> poison,302 <vscale x 2 x i16> %0,303 <vscale x 2 x i16> %1,304 iXLen 0, iXLen %2)305 306 ret <vscale x 2 x i16> %a307}308 309define <vscale x 2 x i16> @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {310; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16:311; CHECK: # %bb.0: # %entry312; CHECK-NEXT: csrwi vxrm, 0313; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu314; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t315; CHECK-NEXT: ret316entry:317 %a = call <vscale x 2 x i16> @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16(318 <vscale x 2 x i16> %0,319 <vscale x 2 x i16> %1,320 <vscale x 2 x i16> %2,321 <vscale x 2 x i1> %3,322 iXLen 0, iXLen %4, iXLen 1)323 324 ret <vscale x 2 x i16> %a325}326 327define <vscale x 4 x i16> @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, iXLen %2) nounwind {328; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16:329; CHECK: # %bb.0: # %entry330; CHECK-NEXT: csrwi vxrm, 0331; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma332; CHECK-NEXT: vsmul.vv v8, v8, v9333; CHECK-NEXT: ret334entry:335 %a = call <vscale x 4 x i16> @llvm.riscv.vsmul.nxv4i16.nxv4i16(336 <vscale x 4 x i16> poison,337 <vscale x 4 x i16> %0,338 <vscale x 4 x i16> %1,339 iXLen 0, iXLen %2)340 341 ret <vscale x 4 x i16> %a342}343 344define <vscale x 4 x i16> @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {345; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16:346; CHECK: # %bb.0: # %entry347; CHECK-NEXT: csrwi vxrm, 0348; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu349; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t350; CHECK-NEXT: ret351entry:352 %a = call <vscale x 4 x i16> @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16(353 <vscale x 4 x i16> %0,354 <vscale x 4 x i16> %1,355 <vscale x 4 x i16> %2,356 <vscale x 4 x i1> %3,357 iXLen 0, iXLen %4, iXLen 1)358 359 ret <vscale x 4 x i16> %a360}361 362define <vscale x 8 x i16> @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, iXLen %2) nounwind {363; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16:364; CHECK: # %bb.0: # %entry365; CHECK-NEXT: csrwi vxrm, 0366; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma367; CHECK-NEXT: vsmul.vv v8, v8, v10368; CHECK-NEXT: ret369entry:370 %a = call <vscale x 8 x i16> @llvm.riscv.vsmul.nxv8i16.nxv8i16(371 <vscale x 8 x i16> poison,372 <vscale x 8 x i16> %0,373 <vscale x 8 x i16> %1,374 iXLen 0, iXLen %2)375 376 ret <vscale x 8 x i16> %a377}378 379define <vscale x 8 x i16> @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {380; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16:381; CHECK: # %bb.0: # %entry382; CHECK-NEXT: csrwi vxrm, 0383; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu384; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t385; CHECK-NEXT: ret386entry:387 %a = call <vscale x 8 x i16> @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16(388 <vscale x 8 x i16> %0,389 <vscale x 8 x i16> %1,390 <vscale x 8 x i16> %2,391 <vscale x 8 x i1> %3,392 iXLen 0, iXLen %4, iXLen 1)393 394 ret <vscale x 8 x i16> %a395}396 397define <vscale x 16 x i16> @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, iXLen %2) nounwind {398; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16:399; CHECK: # %bb.0: # %entry400; CHECK-NEXT: csrwi vxrm, 0401; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma402; CHECK-NEXT: vsmul.vv v8, v8, v12403; CHECK-NEXT: ret404entry:405 %a = call <vscale x 16 x i16> @llvm.riscv.vsmul.nxv16i16.nxv16i16(406 <vscale x 16 x i16> poison,407 <vscale x 16 x i16> %0,408 <vscale x 16 x i16> %1,409 iXLen 0, iXLen %2)410 411 ret <vscale x 16 x i16> %a412}413 414define <vscale x 16 x i16> @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {415; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16:416; CHECK: # %bb.0: # %entry417; CHECK-NEXT: csrwi vxrm, 0418; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu419; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t420; CHECK-NEXT: ret421entry:422 %a = call <vscale x 16 x i16> @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16(423 <vscale x 16 x i16> %0,424 <vscale x 16 x i16> %1,425 <vscale x 16 x i16> %2,426 <vscale x 16 x i1> %3,427 iXLen 0, iXLen %4, iXLen 1)428 429 ret <vscale x 16 x i16> %a430}431 432define <vscale x 32 x i16> @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, iXLen %2) nounwind {433; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16:434; CHECK: # %bb.0: # %entry435; CHECK-NEXT: csrwi vxrm, 0436; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma437; CHECK-NEXT: vsmul.vv v8, v8, v16438; CHECK-NEXT: ret439entry:440 %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.nxv32i16.nxv32i16(441 <vscale x 32 x i16> poison,442 <vscale x 32 x i16> %0,443 <vscale x 32 x i16> %1,444 iXLen 0, iXLen %2)445 446 ret <vscale x 32 x i16> %a447}448 449define <vscale x 32 x i16> @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {450; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16:451; CHECK: # %bb.0: # %entry452; CHECK-NEXT: vl8re16.v v24, (a0)453; CHECK-NEXT: csrwi vxrm, 0454; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu455; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t456; CHECK-NEXT: ret457entry:458 %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.nxv32i16(459 <vscale x 32 x i16> %0,460 <vscale x 32 x i16> %1,461 <vscale x 32 x i16> %2,462 <vscale x 32 x i1> %3,463 iXLen 0, iXLen %4, iXLen 1)464 465 ret <vscale x 32 x i16> %a466}467 468define <vscale x 1 x i32> @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, iXLen %2) nounwind {469; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32:470; CHECK: # %bb.0: # %entry471; CHECK-NEXT: csrwi vxrm, 0472; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma473; CHECK-NEXT: vsmul.vv v8, v8, v9474; CHECK-NEXT: ret475entry:476 %a = call <vscale x 1 x i32> @llvm.riscv.vsmul.nxv1i32.nxv1i32(477 <vscale x 1 x i32> poison,478 <vscale x 1 x i32> %0,479 <vscale x 1 x i32> %1,480 iXLen 0, iXLen %2)481 482 ret <vscale x 1 x i32> %a483}484 485define <vscale x 1 x i32> @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {486; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: csrwi vxrm, 0489; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu490; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t491; CHECK-NEXT: ret492entry:493 %a = call <vscale x 1 x i32> @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32(494 <vscale x 1 x i32> %0,495 <vscale x 1 x i32> %1,496 <vscale x 1 x i32> %2,497 <vscale x 1 x i1> %3,498 iXLen 0, iXLen %4, iXLen 1)499 500 ret <vscale x 1 x i32> %a501}502 503define <vscale x 2 x i32> @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, iXLen %2) nounwind {504; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32:505; CHECK: # %bb.0: # %entry506; CHECK-NEXT: csrwi vxrm, 0507; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma508; CHECK-NEXT: vsmul.vv v8, v8, v9509; CHECK-NEXT: ret510entry:511 %a = call <vscale x 2 x i32> @llvm.riscv.vsmul.nxv2i32.nxv2i32(512 <vscale x 2 x i32> poison,513 <vscale x 2 x i32> %0,514 <vscale x 2 x i32> %1,515 iXLen 0, iXLen %2)516 517 ret <vscale x 2 x i32> %a518}519 520define <vscale x 2 x i32> @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {521; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32:522; CHECK: # %bb.0: # %entry523; CHECK-NEXT: csrwi vxrm, 0524; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu525; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t526; CHECK-NEXT: ret527entry:528 %a = call <vscale x 2 x i32> @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32(529 <vscale x 2 x i32> %0,530 <vscale x 2 x i32> %1,531 <vscale x 2 x i32> %2,532 <vscale x 2 x i1> %3,533 iXLen 0, iXLen %4, iXLen 1)534 535 ret <vscale x 2 x i32> %a536}537 538define <vscale x 4 x i32> @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, iXLen %2) nounwind {539; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32:540; CHECK: # %bb.0: # %entry541; CHECK-NEXT: csrwi vxrm, 0542; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma543; CHECK-NEXT: vsmul.vv v8, v8, v10544; CHECK-NEXT: ret545entry:546 %a = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.nxv4i32(547 <vscale x 4 x i32> poison,548 <vscale x 4 x i32> %0,549 <vscale x 4 x i32> %1,550 iXLen 0, iXLen %2)551 552 ret <vscale x 4 x i32> %a553}554 555define <vscale x 4 x i32> @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {556; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32:557; CHECK: # %bb.0: # %entry558; CHECK-NEXT: csrwi vxrm, 0559; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu560; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t561; CHECK-NEXT: ret562entry:563 %a = call <vscale x 4 x i32> @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32(564 <vscale x 4 x i32> %0,565 <vscale x 4 x i32> %1,566 <vscale x 4 x i32> %2,567 <vscale x 4 x i1> %3,568 iXLen 0, iXLen %4, iXLen 1)569 570 ret <vscale x 4 x i32> %a571}572 573define <vscale x 8 x i32> @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, iXLen %2) nounwind {574; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32:575; CHECK: # %bb.0: # %entry576; CHECK-NEXT: csrwi vxrm, 0577; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma578; CHECK-NEXT: vsmul.vv v8, v8, v12579; CHECK-NEXT: ret580entry:581 %a = call <vscale x 8 x i32> @llvm.riscv.vsmul.nxv8i32.nxv8i32(582 <vscale x 8 x i32> poison,583 <vscale x 8 x i32> %0,584 <vscale x 8 x i32> %1,585 iXLen 0, iXLen %2)586 587 ret <vscale x 8 x i32> %a588}589 590define <vscale x 8 x i32> @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {591; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32:592; CHECK: # %bb.0: # %entry593; CHECK-NEXT: csrwi vxrm, 0594; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu595; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t596; CHECK-NEXT: ret597entry:598 %a = call <vscale x 8 x i32> @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32(599 <vscale x 8 x i32> %0,600 <vscale x 8 x i32> %1,601 <vscale x 8 x i32> %2,602 <vscale x 8 x i1> %3,603 iXLen 0, iXLen %4, iXLen 1)604 605 ret <vscale x 8 x i32> %a606}607 608define <vscale x 16 x i32> @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, iXLen %2) nounwind {609; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32:610; CHECK: # %bb.0: # %entry611; CHECK-NEXT: csrwi vxrm, 0612; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma613; CHECK-NEXT: vsmul.vv v8, v8, v16614; CHECK-NEXT: ret615entry:616 %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.nxv16i32.nxv16i32(617 <vscale x 16 x i32> poison,618 <vscale x 16 x i32> %0,619 <vscale x 16 x i32> %1,620 iXLen 0, iXLen %2)621 622 ret <vscale x 16 x i32> %a623}624 625define <vscale x 16 x i32> @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {626; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32:627; CHECK: # %bb.0: # %entry628; CHECK-NEXT: vl8re32.v v24, (a0)629; CHECK-NEXT: csrwi vxrm, 0630; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu631; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t632; CHECK-NEXT: ret633entry:634 %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.nxv16i32(635 <vscale x 16 x i32> %0,636 <vscale x 16 x i32> %1,637 <vscale x 16 x i32> %2,638 <vscale x 16 x i1> %3,639 iXLen 0, iXLen %4, iXLen 1)640 641 ret <vscale x 16 x i32> %a642}643 644define <vscale x 1 x i64> @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, iXLen %2) nounwind {645; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64:646; CHECK: # %bb.0: # %entry647; CHECK-NEXT: csrwi vxrm, 0648; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma649; CHECK-NEXT: vsmul.vv v8, v8, v9650; CHECK-NEXT: ret651entry:652 %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.nxv1i64(653 <vscale x 1 x i64> poison,654 <vscale x 1 x i64> %0,655 <vscale x 1 x i64> %1,656 iXLen 0, iXLen %2)657 658 ret <vscale x 1 x i64> %a659}660 661define <vscale x 1 x i64> @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {662; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64:663; CHECK: # %bb.0: # %entry664; CHECK-NEXT: csrwi vxrm, 0665; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu666; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t667; CHECK-NEXT: ret668entry:669 %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(670 <vscale x 1 x i64> %0,671 <vscale x 1 x i64> %1,672 <vscale x 1 x i64> %2,673 <vscale x 1 x i1> %3,674 iXLen 0, iXLen %4, iXLen 1)675 676 ret <vscale x 1 x i64> %a677}678 679define <vscale x 2 x i64> @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, iXLen %2) nounwind {680; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64:681; CHECK: # %bb.0: # %entry682; CHECK-NEXT: csrwi vxrm, 0683; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma684; CHECK-NEXT: vsmul.vv v8, v8, v10685; CHECK-NEXT: ret686entry:687 %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.nxv2i64(688 <vscale x 2 x i64> poison,689 <vscale x 2 x i64> %0,690 <vscale x 2 x i64> %1,691 iXLen 0, iXLen %2)692 693 ret <vscale x 2 x i64> %a694}695 696define <vscale x 2 x i64> @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {697; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64:698; CHECK: # %bb.0: # %entry699; CHECK-NEXT: csrwi vxrm, 0700; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu701; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t702; CHECK-NEXT: ret703entry:704 %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64(705 <vscale x 2 x i64> %0,706 <vscale x 2 x i64> %1,707 <vscale x 2 x i64> %2,708 <vscale x 2 x i1> %3,709 iXLen 0, iXLen %4, iXLen 1)710 711 ret <vscale x 2 x i64> %a712}713 714define <vscale x 4 x i64> @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, iXLen %2) nounwind {715; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64:716; CHECK: # %bb.0: # %entry717; CHECK-NEXT: csrwi vxrm, 0718; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma719; CHECK-NEXT: vsmul.vv v8, v8, v12720; CHECK-NEXT: ret721entry:722 %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.nxv4i64(723 <vscale x 4 x i64> poison,724 <vscale x 4 x i64> %0,725 <vscale x 4 x i64> %1,726 iXLen 0, iXLen %2)727 728 ret <vscale x 4 x i64> %a729}730 731define <vscale x 4 x i64> @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {732; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64:733; CHECK: # %bb.0: # %entry734; CHECK-NEXT: csrwi vxrm, 0735; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu736; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t737; CHECK-NEXT: ret738entry:739 %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64(740 <vscale x 4 x i64> %0,741 <vscale x 4 x i64> %1,742 <vscale x 4 x i64> %2,743 <vscale x 4 x i1> %3,744 iXLen 0, iXLen %4, iXLen 1)745 746 ret <vscale x 4 x i64> %a747}748 749define <vscale x 8 x i64> @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, iXLen %2) nounwind {750; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: csrwi vxrm, 0753; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma754; CHECK-NEXT: vsmul.vv v8, v8, v16755; CHECK-NEXT: ret756entry:757 %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.nxv8i64(758 <vscale x 8 x i64> poison,759 <vscale x 8 x i64> %0,760 <vscale x 8 x i64> %1,761 iXLen 0, iXLen %2)762 763 ret <vscale x 8 x i64> %a764}765 766define <vscale x 8 x i64> @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {767; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vl8re64.v v24, (a0)770; CHECK-NEXT: csrwi vxrm, 0771; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu772; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t773; CHECK-NEXT: ret774entry:775 %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.nxv8i64(776 <vscale x 8 x i64> %0,777 <vscale x 8 x i64> %1,778 <vscale x 8 x i64> %2,779 <vscale x 8 x i1> %3,780 iXLen 0, iXLen %4, iXLen 1)781 782 ret <vscale x 8 x i64> %a783}784 785define <vscale x 1 x i8> @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, iXLen %2) nounwind {786; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8:787; CHECK: # %bb.0: # %entry788; CHECK-NEXT: csrwi vxrm, 0789; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma790; CHECK-NEXT: vsmul.vx v8, v8, a0791; CHECK-NEXT: ret792entry:793 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.nxv1i8.i8(794 <vscale x 1 x i8> poison,795 <vscale x 1 x i8> %0,796 i8 %1,797 iXLen 0, iXLen %2)798 799 ret <vscale x 1 x i8> %a800}801 802define <vscale x 1 x i8> @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {803; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8:804; CHECK: # %bb.0: # %entry805; CHECK-NEXT: csrwi vxrm, 0806; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu807; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t808; CHECK-NEXT: ret809entry:810 %a = call <vscale x 1 x i8> @llvm.riscv.vsmul.mask.nxv1i8.i8(811 <vscale x 1 x i8> %0,812 <vscale x 1 x i8> %1,813 i8 %2,814 <vscale x 1 x i1> %3,815 iXLen 0, iXLen %4, iXLen 1)816 817 ret <vscale x 1 x i8> %a818}819 820define <vscale x 2 x i8> @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, iXLen %2) nounwind {821; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8:822; CHECK: # %bb.0: # %entry823; CHECK-NEXT: csrwi vxrm, 0824; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma825; CHECK-NEXT: vsmul.vx v8, v8, a0826; CHECK-NEXT: ret827entry:828 %a = call <vscale x 2 x i8> @llvm.riscv.vsmul.nxv2i8.i8(829 <vscale x 2 x i8> poison,830 <vscale x 2 x i8> %0,831 i8 %1,832 iXLen 0, iXLen %2)833 834 ret <vscale x 2 x i8> %a835}836 837define <vscale x 2 x i8> @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {838; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8:839; CHECK: # %bb.0: # %entry840; CHECK-NEXT: csrwi vxrm, 0841; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu842; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t843; CHECK-NEXT: ret844entry:845 %a = call <vscale x 2 x i8> @llvm.riscv.vsmul.mask.nxv2i8.i8(846 <vscale x 2 x i8> %0,847 <vscale x 2 x i8> %1,848 i8 %2,849 <vscale x 2 x i1> %3,850 iXLen 0, iXLen %4, iXLen 1)851 852 ret <vscale x 2 x i8> %a853}854 855define <vscale x 4 x i8> @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, iXLen %2) nounwind {856; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8:857; CHECK: # %bb.0: # %entry858; CHECK-NEXT: csrwi vxrm, 0859; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma860; CHECK-NEXT: vsmul.vx v8, v8, a0861; CHECK-NEXT: ret862entry:863 %a = call <vscale x 4 x i8> @llvm.riscv.vsmul.nxv4i8.i8(864 <vscale x 4 x i8> poison,865 <vscale x 4 x i8> %0,866 i8 %1,867 iXLen 0, iXLen %2)868 869 ret <vscale x 4 x i8> %a870}871 872define <vscale x 4 x i8> @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {873; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8:874; CHECK: # %bb.0: # %entry875; CHECK-NEXT: csrwi vxrm, 0876; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu877; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t878; CHECK-NEXT: ret879entry:880 %a = call <vscale x 4 x i8> @llvm.riscv.vsmul.mask.nxv4i8.i8(881 <vscale x 4 x i8> %0,882 <vscale x 4 x i8> %1,883 i8 %2,884 <vscale x 4 x i1> %3,885 iXLen 0, iXLen %4, iXLen 1)886 887 ret <vscale x 4 x i8> %a888}889 890define <vscale x 8 x i8> @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, iXLen %2) nounwind {891; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8:892; CHECK: # %bb.0: # %entry893; CHECK-NEXT: csrwi vxrm, 0894; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma895; CHECK-NEXT: vsmul.vx v8, v8, a0896; CHECK-NEXT: ret897entry:898 %a = call <vscale x 8 x i8> @llvm.riscv.vsmul.nxv8i8.i8(899 <vscale x 8 x i8> poison,900 <vscale x 8 x i8> %0,901 i8 %1,902 iXLen 0, iXLen %2)903 904 ret <vscale x 8 x i8> %a905}906 907define <vscale x 8 x i8> @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {908; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8:909; CHECK: # %bb.0: # %entry910; CHECK-NEXT: csrwi vxrm, 0911; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu912; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t913; CHECK-NEXT: ret914entry:915 %a = call <vscale x 8 x i8> @llvm.riscv.vsmul.mask.nxv8i8.i8(916 <vscale x 8 x i8> %0,917 <vscale x 8 x i8> %1,918 i8 %2,919 <vscale x 8 x i1> %3,920 iXLen 0, iXLen %4, iXLen 1)921 922 ret <vscale x 8 x i8> %a923}924 925define <vscale x 16 x i8> @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, iXLen %2) nounwind {926; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8:927; CHECK: # %bb.0: # %entry928; CHECK-NEXT: csrwi vxrm, 0929; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma930; CHECK-NEXT: vsmul.vx v8, v8, a0931; CHECK-NEXT: ret932entry:933 %a = call <vscale x 16 x i8> @llvm.riscv.vsmul.nxv16i8.i8(934 <vscale x 16 x i8> poison,935 <vscale x 16 x i8> %0,936 i8 %1,937 iXLen 0, iXLen %2)938 939 ret <vscale x 16 x i8> %a940}941 942define <vscale x 16 x i8> @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {943; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8:944; CHECK: # %bb.0: # %entry945; CHECK-NEXT: csrwi vxrm, 0946; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu947; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t948; CHECK-NEXT: ret949entry:950 %a = call <vscale x 16 x i8> @llvm.riscv.vsmul.mask.nxv16i8.i8(951 <vscale x 16 x i8> %0,952 <vscale x 16 x i8> %1,953 i8 %2,954 <vscale x 16 x i1> %3,955 iXLen 0, iXLen %4, iXLen 1)956 957 ret <vscale x 16 x i8> %a958}959 960define <vscale x 32 x i8> @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, iXLen %2) nounwind {961; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8:962; CHECK: # %bb.0: # %entry963; CHECK-NEXT: csrwi vxrm, 0964; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma965; CHECK-NEXT: vsmul.vx v8, v8, a0966; CHECK-NEXT: ret967entry:968 %a = call <vscale x 32 x i8> @llvm.riscv.vsmul.nxv32i8.i8(969 <vscale x 32 x i8> poison,970 <vscale x 32 x i8> %0,971 i8 %1,972 iXLen 0, iXLen %2)973 974 ret <vscale x 32 x i8> %a975}976 977define <vscale x 32 x i8> @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {978; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8:979; CHECK: # %bb.0: # %entry980; CHECK-NEXT: csrwi vxrm, 0981; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu982; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t983; CHECK-NEXT: ret984entry:985 %a = call <vscale x 32 x i8> @llvm.riscv.vsmul.mask.nxv32i8.i8(986 <vscale x 32 x i8> %0,987 <vscale x 32 x i8> %1,988 i8 %2,989 <vscale x 32 x i1> %3,990 iXLen 0, iXLen %4, iXLen 1)991 992 ret <vscale x 32 x i8> %a993}994 995define <vscale x 64 x i8> @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, iXLen %2) nounwind {996; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8:997; CHECK: # %bb.0: # %entry998; CHECK-NEXT: csrwi vxrm, 0999; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma1000; CHECK-NEXT: vsmul.vx v8, v8, a01001; CHECK-NEXT: ret1002entry:1003 %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.nxv64i8.i8(1004 <vscale x 64 x i8> poison,1005 <vscale x 64 x i8> %0,1006 i8 %1,1007 iXLen 0, iXLen %2)1008 1009 ret <vscale x 64 x i8> %a1010}1011 1012define <vscale x 64 x i8> @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {1013; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8:1014; CHECK: # %bb.0: # %entry1015; CHECK-NEXT: csrwi vxrm, 01016; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu1017; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t1018; CHECK-NEXT: ret1019entry:1020 %a = call <vscale x 64 x i8> @llvm.riscv.vsmul.mask.nxv64i8.i8(1021 <vscale x 64 x i8> %0,1022 <vscale x 64 x i8> %1,1023 i8 %2,1024 <vscale x 64 x i1> %3,1025 iXLen 0, iXLen %4, iXLen 1)1026 1027 ret <vscale x 64 x i8> %a1028}1029 1030define <vscale x 1 x i16> @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, iXLen %2) nounwind {1031; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: csrwi vxrm, 01034; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma1035; CHECK-NEXT: vsmul.vx v8, v8, a01036; CHECK-NEXT: ret1037entry:1038 %a = call <vscale x 1 x i16> @llvm.riscv.vsmul.nxv1i16.i16(1039 <vscale x 1 x i16> poison,1040 <vscale x 1 x i16> %0,1041 i16 %1,1042 iXLen 0, iXLen %2)1043 1044 ret <vscale x 1 x i16> %a1045}1046 1047define <vscale x 1 x i16> @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1048; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16:1049; CHECK: # %bb.0: # %entry1050; CHECK-NEXT: csrwi vxrm, 01051; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu1052; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t1053; CHECK-NEXT: ret1054entry:1055 %a = call <vscale x 1 x i16> @llvm.riscv.vsmul.mask.nxv1i16.i16(1056 <vscale x 1 x i16> %0,1057 <vscale x 1 x i16> %1,1058 i16 %2,1059 <vscale x 1 x i1> %3,1060 iXLen 0, iXLen %4, iXLen 1)1061 1062 ret <vscale x 1 x i16> %a1063}1064 1065define <vscale x 2 x i16> @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, iXLen %2) nounwind {1066; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16:1067; CHECK: # %bb.0: # %entry1068; CHECK-NEXT: csrwi vxrm, 01069; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma1070; CHECK-NEXT: vsmul.vx v8, v8, a01071; CHECK-NEXT: ret1072entry:1073 %a = call <vscale x 2 x i16> @llvm.riscv.vsmul.nxv2i16.i16(1074 <vscale x 2 x i16> poison,1075 <vscale x 2 x i16> %0,1076 i16 %1,1077 iXLen 0, iXLen %2)1078 1079 ret <vscale x 2 x i16> %a1080}1081 1082define <vscale x 2 x i16> @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1083; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16:1084; CHECK: # %bb.0: # %entry1085; CHECK-NEXT: csrwi vxrm, 01086; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu1087; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t1088; CHECK-NEXT: ret1089entry:1090 %a = call <vscale x 2 x i16> @llvm.riscv.vsmul.mask.nxv2i16.i16(1091 <vscale x 2 x i16> %0,1092 <vscale x 2 x i16> %1,1093 i16 %2,1094 <vscale x 2 x i1> %3,1095 iXLen 0, iXLen %4, iXLen 1)1096 1097 ret <vscale x 2 x i16> %a1098}1099 1100define <vscale x 4 x i16> @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, iXLen %2) nounwind {1101; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16:1102; CHECK: # %bb.0: # %entry1103; CHECK-NEXT: csrwi vxrm, 01104; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma1105; CHECK-NEXT: vsmul.vx v8, v8, a01106; CHECK-NEXT: ret1107entry:1108 %a = call <vscale x 4 x i16> @llvm.riscv.vsmul.nxv4i16.i16(1109 <vscale x 4 x i16> poison,1110 <vscale x 4 x i16> %0,1111 i16 %1,1112 iXLen 0, iXLen %2)1113 1114 ret <vscale x 4 x i16> %a1115}1116 1117define <vscale x 4 x i16> @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1118; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16:1119; CHECK: # %bb.0: # %entry1120; CHECK-NEXT: csrwi vxrm, 01121; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu1122; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t1123; CHECK-NEXT: ret1124entry:1125 %a = call <vscale x 4 x i16> @llvm.riscv.vsmul.mask.nxv4i16.i16(1126 <vscale x 4 x i16> %0,1127 <vscale x 4 x i16> %1,1128 i16 %2,1129 <vscale x 4 x i1> %3,1130 iXLen 0, iXLen %4, iXLen 1)1131 1132 ret <vscale x 4 x i16> %a1133}1134 1135define <vscale x 8 x i16> @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, iXLen %2) nounwind {1136; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16:1137; CHECK: # %bb.0: # %entry1138; CHECK-NEXT: csrwi vxrm, 01139; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma1140; CHECK-NEXT: vsmul.vx v8, v8, a01141; CHECK-NEXT: ret1142entry:1143 %a = call <vscale x 8 x i16> @llvm.riscv.vsmul.nxv8i16.i16(1144 <vscale x 8 x i16> poison,1145 <vscale x 8 x i16> %0,1146 i16 %1,1147 iXLen 0, iXLen %2)1148 1149 ret <vscale x 8 x i16> %a1150}1151 1152define <vscale x 8 x i16> @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1153; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16:1154; CHECK: # %bb.0: # %entry1155; CHECK-NEXT: csrwi vxrm, 01156; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu1157; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t1158; CHECK-NEXT: ret1159entry:1160 %a = call <vscale x 8 x i16> @llvm.riscv.vsmul.mask.nxv8i16.i16(1161 <vscale x 8 x i16> %0,1162 <vscale x 8 x i16> %1,1163 i16 %2,1164 <vscale x 8 x i1> %3,1165 iXLen 0, iXLen %4, iXLen 1)1166 1167 ret <vscale x 8 x i16> %a1168}1169 1170define <vscale x 16 x i16> @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, iXLen %2) nounwind {1171; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16:1172; CHECK: # %bb.0: # %entry1173; CHECK-NEXT: csrwi vxrm, 01174; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma1175; CHECK-NEXT: vsmul.vx v8, v8, a01176; CHECK-NEXT: ret1177entry:1178 %a = call <vscale x 16 x i16> @llvm.riscv.vsmul.nxv16i16.i16(1179 <vscale x 16 x i16> poison,1180 <vscale x 16 x i16> %0,1181 i16 %1,1182 iXLen 0, iXLen %2)1183 1184 ret <vscale x 16 x i16> %a1185}1186 1187define <vscale x 16 x i16> @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1188; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16:1189; CHECK: # %bb.0: # %entry1190; CHECK-NEXT: csrwi vxrm, 01191; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu1192; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t1193; CHECK-NEXT: ret1194entry:1195 %a = call <vscale x 16 x i16> @llvm.riscv.vsmul.mask.nxv16i16.i16(1196 <vscale x 16 x i16> %0,1197 <vscale x 16 x i16> %1,1198 i16 %2,1199 <vscale x 16 x i1> %3,1200 iXLen 0, iXLen %4, iXLen 1)1201 1202 ret <vscale x 16 x i16> %a1203}1204 1205define <vscale x 32 x i16> @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, iXLen %2) nounwind {1206; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16:1207; CHECK: # %bb.0: # %entry1208; CHECK-NEXT: csrwi vxrm, 01209; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma1210; CHECK-NEXT: vsmul.vx v8, v8, a01211; CHECK-NEXT: ret1212entry:1213 %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.nxv32i16.i16(1214 <vscale x 32 x i16> poison,1215 <vscale x 32 x i16> %0,1216 i16 %1,1217 iXLen 0, iXLen %2)1218 1219 ret <vscale x 32 x i16> %a1220}1221 1222define <vscale x 32 x i16> @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {1223; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16:1224; CHECK: # %bb.0: # %entry1225; CHECK-NEXT: csrwi vxrm, 01226; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu1227; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t1228; CHECK-NEXT: ret1229entry:1230 %a = call <vscale x 32 x i16> @llvm.riscv.vsmul.mask.nxv32i16.i16(1231 <vscale x 32 x i16> %0,1232 <vscale x 32 x i16> %1,1233 i16 %2,1234 <vscale x 32 x i1> %3,1235 iXLen 0, iXLen %4, iXLen 1)1236 1237 ret <vscale x 32 x i16> %a1238}1239 1240define <vscale x 1 x i32> @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, iXLen %2) nounwind {1241; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32:1242; CHECK: # %bb.0: # %entry1243; CHECK-NEXT: csrwi vxrm, 01244; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma1245; CHECK-NEXT: vsmul.vx v8, v8, a01246; CHECK-NEXT: ret1247entry:1248 %a = call <vscale x 1 x i32> @llvm.riscv.vsmul.nxv1i32.i32(1249 <vscale x 1 x i32> poison,1250 <vscale x 1 x i32> %0,1251 i32 %1,1252 iXLen 0, iXLen %2)1253 1254 ret <vscale x 1 x i32> %a1255}1256 1257define <vscale x 1 x i32> @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1258; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32:1259; CHECK: # %bb.0: # %entry1260; CHECK-NEXT: csrwi vxrm, 01261; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu1262; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t1263; CHECK-NEXT: ret1264entry:1265 %a = call <vscale x 1 x i32> @llvm.riscv.vsmul.mask.nxv1i32.i32(1266 <vscale x 1 x i32> %0,1267 <vscale x 1 x i32> %1,1268 i32 %2,1269 <vscale x 1 x i1> %3,1270 iXLen 0, iXLen %4, iXLen 1)1271 1272 ret <vscale x 1 x i32> %a1273}1274 1275define <vscale x 2 x i32> @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, iXLen %2) nounwind {1276; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32:1277; CHECK: # %bb.0: # %entry1278; CHECK-NEXT: csrwi vxrm, 01279; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma1280; CHECK-NEXT: vsmul.vx v8, v8, a01281; CHECK-NEXT: ret1282entry:1283 %a = call <vscale x 2 x i32> @llvm.riscv.vsmul.nxv2i32.i32(1284 <vscale x 2 x i32> poison,1285 <vscale x 2 x i32> %0,1286 i32 %1,1287 iXLen 0, iXLen %2)1288 1289 ret <vscale x 2 x i32> %a1290}1291 1292define <vscale x 2 x i32> @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1293; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32:1294; CHECK: # %bb.0: # %entry1295; CHECK-NEXT: csrwi vxrm, 01296; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu1297; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t1298; CHECK-NEXT: ret1299entry:1300 %a = call <vscale x 2 x i32> @llvm.riscv.vsmul.mask.nxv2i32.i32(1301 <vscale x 2 x i32> %0,1302 <vscale x 2 x i32> %1,1303 i32 %2,1304 <vscale x 2 x i1> %3,1305 iXLen 0, iXLen %4, iXLen 1)1306 1307 ret <vscale x 2 x i32> %a1308}1309 1310define <vscale x 4 x i32> @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, iXLen %2) nounwind {1311; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32:1312; CHECK: # %bb.0: # %entry1313; CHECK-NEXT: csrwi vxrm, 01314; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1315; CHECK-NEXT: vsmul.vx v8, v8, a01316; CHECK-NEXT: ret1317entry:1318 %a = call <vscale x 4 x i32> @llvm.riscv.vsmul.nxv4i32.i32(1319 <vscale x 4 x i32> poison,1320 <vscale x 4 x i32> %0,1321 i32 %1,1322 iXLen 0, iXLen %2)1323 1324 ret <vscale x 4 x i32> %a1325}1326 1327define <vscale x 4 x i32> @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1328; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32:1329; CHECK: # %bb.0: # %entry1330; CHECK-NEXT: csrwi vxrm, 01331; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu1332; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t1333; CHECK-NEXT: ret1334entry:1335 %a = call <vscale x 4 x i32> @llvm.riscv.vsmul.mask.nxv4i32.i32(1336 <vscale x 4 x i32> %0,1337 <vscale x 4 x i32> %1,1338 i32 %2,1339 <vscale x 4 x i1> %3,1340 iXLen 0, iXLen %4, iXLen 1)1341 1342 ret <vscale x 4 x i32> %a1343}1344 1345define <vscale x 8 x i32> @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, iXLen %2) nounwind {1346; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32:1347; CHECK: # %bb.0: # %entry1348; CHECK-NEXT: csrwi vxrm, 01349; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1350; CHECK-NEXT: vsmul.vx v8, v8, a01351; CHECK-NEXT: ret1352entry:1353 %a = call <vscale x 8 x i32> @llvm.riscv.vsmul.nxv8i32.i32(1354 <vscale x 8 x i32> poison,1355 <vscale x 8 x i32> %0,1356 i32 %1,1357 iXLen 0, iXLen %2)1358 1359 ret <vscale x 8 x i32> %a1360}1361 1362define <vscale x 8 x i32> @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1363; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32:1364; CHECK: # %bb.0: # %entry1365; CHECK-NEXT: csrwi vxrm, 01366; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu1367; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t1368; CHECK-NEXT: ret1369entry:1370 %a = call <vscale x 8 x i32> @llvm.riscv.vsmul.mask.nxv8i32.i32(1371 <vscale x 8 x i32> %0,1372 <vscale x 8 x i32> %1,1373 i32 %2,1374 <vscale x 8 x i1> %3,1375 iXLen 0, iXLen %4, iXLen 1)1376 1377 ret <vscale x 8 x i32> %a1378}1379 1380define <vscale x 16 x i32> @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, iXLen %2) nounwind {1381; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32:1382; CHECK: # %bb.0: # %entry1383; CHECK-NEXT: csrwi vxrm, 01384; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1385; CHECK-NEXT: vsmul.vx v8, v8, a01386; CHECK-NEXT: ret1387entry:1388 %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.nxv16i32.i32(1389 <vscale x 16 x i32> poison,1390 <vscale x 16 x i32> %0,1391 i32 %1,1392 iXLen 0, iXLen %2)1393 1394 ret <vscale x 16 x i32> %a1395}1396 1397define <vscale x 16 x i32> @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {1398; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32:1399; CHECK: # %bb.0: # %entry1400; CHECK-NEXT: csrwi vxrm, 01401; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu1402; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t1403; CHECK-NEXT: ret1404entry:1405 %a = call <vscale x 16 x i32> @llvm.riscv.vsmul.mask.nxv16i32.i32(1406 <vscale x 16 x i32> %0,1407 <vscale x 16 x i32> %1,1408 i32 %2,1409 <vscale x 16 x i1> %3,1410 iXLen 0, iXLen %4, iXLen 1)1411 1412 ret <vscale x 16 x i32> %a1413}1414 1415define <vscale x 1 x i64> @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, iXLen %2) nounwind {1416; RV32-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:1417; RV32: # %bb.0: # %entry1418; RV32-NEXT: addi sp, sp, -161419; RV32-NEXT: sw a0, 8(sp)1420; RV32-NEXT: sw a1, 12(sp)1421; RV32-NEXT: addi a0, sp, 81422; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1423; RV32-NEXT: vlse64.v v9, (a0), zero1424; RV32-NEXT: csrwi vxrm, 01425; RV32-NEXT: vsmul.vv v8, v8, v91426; RV32-NEXT: addi sp, sp, 161427; RV32-NEXT: ret1428;1429; RV64-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64:1430; RV64: # %bb.0: # %entry1431; RV64-NEXT: csrwi vxrm, 01432; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1433; RV64-NEXT: vsmul.vx v8, v8, a01434; RV64-NEXT: ret1435entry:1436 %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.nxv1i64.i64(1437 <vscale x 1 x i64> poison,1438 <vscale x 1 x i64> %0,1439 i64 %1,1440 iXLen 0, iXLen %2)1441 1442 ret <vscale x 1 x i64> %a1443}1444 1445define <vscale x 1 x i64> @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {1446; RV32-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64:1447; RV32: # %bb.0: # %entry1448; RV32-NEXT: addi sp, sp, -161449; RV32-NEXT: sw a0, 8(sp)1450; RV32-NEXT: sw a1, 12(sp)1451; RV32-NEXT: addi a0, sp, 81452; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu1453; RV32-NEXT: vlse64.v v10, (a0), zero1454; RV32-NEXT: csrwi vxrm, 01455; RV32-NEXT: vsmul.vv v8, v9, v10, v0.t1456; RV32-NEXT: addi sp, sp, 161457; RV32-NEXT: ret1458;1459; RV64-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64:1460; RV64: # %bb.0: # %entry1461; RV64-NEXT: csrwi vxrm, 01462; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu1463; RV64-NEXT: vsmul.vx v8, v9, a0, v0.t1464; RV64-NEXT: ret1465entry:1466 %a = call <vscale x 1 x i64> @llvm.riscv.vsmul.mask.nxv1i64.i64(1467 <vscale x 1 x i64> %0,1468 <vscale x 1 x i64> %1,1469 i64 %2,1470 <vscale x 1 x i1> %3,1471 iXLen 0, iXLen %4, iXLen 1)1472 1473 ret <vscale x 1 x i64> %a1474}1475 1476define <vscale x 2 x i64> @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, iXLen %2) nounwind {1477; RV32-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64:1478; RV32: # %bb.0: # %entry1479; RV32-NEXT: addi sp, sp, -161480; RV32-NEXT: sw a0, 8(sp)1481; RV32-NEXT: sw a1, 12(sp)1482; RV32-NEXT: addi a0, sp, 81483; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1484; RV32-NEXT: vlse64.v v10, (a0), zero1485; RV32-NEXT: csrwi vxrm, 01486; RV32-NEXT: vsmul.vv v8, v8, v101487; RV32-NEXT: addi sp, sp, 161488; RV32-NEXT: ret1489;1490; RV64-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64:1491; RV64: # %bb.0: # %entry1492; RV64-NEXT: csrwi vxrm, 01493; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1494; RV64-NEXT: vsmul.vx v8, v8, a01495; RV64-NEXT: ret1496entry:1497 %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.nxv2i64.i64(1498 <vscale x 2 x i64> poison,1499 <vscale x 2 x i64> %0,1500 i64 %1,1501 iXLen 0, iXLen %2)1502 1503 ret <vscale x 2 x i64> %a1504}1505 1506define <vscale x 2 x i64> @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {1507; RV32-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64:1508; RV32: # %bb.0: # %entry1509; RV32-NEXT: addi sp, sp, -161510; RV32-NEXT: sw a0, 8(sp)1511; RV32-NEXT: sw a1, 12(sp)1512; RV32-NEXT: addi a0, sp, 81513; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, mu1514; RV32-NEXT: vlse64.v v12, (a0), zero1515; RV32-NEXT: csrwi vxrm, 01516; RV32-NEXT: vsmul.vv v8, v10, v12, v0.t1517; RV32-NEXT: addi sp, sp, 161518; RV32-NEXT: ret1519;1520; RV64-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64:1521; RV64: # %bb.0: # %entry1522; RV64-NEXT: csrwi vxrm, 01523; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu1524; RV64-NEXT: vsmul.vx v8, v10, a0, v0.t1525; RV64-NEXT: ret1526entry:1527 %a = call <vscale x 2 x i64> @llvm.riscv.vsmul.mask.nxv2i64.i64(1528 <vscale x 2 x i64> %0,1529 <vscale x 2 x i64> %1,1530 i64 %2,1531 <vscale x 2 x i1> %3,1532 iXLen 0, iXLen %4, iXLen 1)1533 1534 ret <vscale x 2 x i64> %a1535}1536 1537define <vscale x 4 x i64> @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, iXLen %2) nounwind {1538; RV32-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64:1539; RV32: # %bb.0: # %entry1540; RV32-NEXT: addi sp, sp, -161541; RV32-NEXT: sw a0, 8(sp)1542; RV32-NEXT: sw a1, 12(sp)1543; RV32-NEXT: addi a0, sp, 81544; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1545; RV32-NEXT: vlse64.v v12, (a0), zero1546; RV32-NEXT: csrwi vxrm, 01547; RV32-NEXT: vsmul.vv v8, v8, v121548; RV32-NEXT: addi sp, sp, 161549; RV32-NEXT: ret1550;1551; RV64-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64:1552; RV64: # %bb.0: # %entry1553; RV64-NEXT: csrwi vxrm, 01554; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1555; RV64-NEXT: vsmul.vx v8, v8, a01556; RV64-NEXT: ret1557entry:1558 %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.nxv4i64.i64(1559 <vscale x 4 x i64> poison,1560 <vscale x 4 x i64> %0,1561 i64 %1,1562 iXLen 0, iXLen %2)1563 1564 ret <vscale x 4 x i64> %a1565}1566 1567define <vscale x 4 x i64> @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {1568; RV32-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64:1569; RV32: # %bb.0: # %entry1570; RV32-NEXT: addi sp, sp, -161571; RV32-NEXT: sw a0, 8(sp)1572; RV32-NEXT: sw a1, 12(sp)1573; RV32-NEXT: addi a0, sp, 81574; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, mu1575; RV32-NEXT: vlse64.v v16, (a0), zero1576; RV32-NEXT: csrwi vxrm, 01577; RV32-NEXT: vsmul.vv v8, v12, v16, v0.t1578; RV32-NEXT: addi sp, sp, 161579; RV32-NEXT: ret1580;1581; RV64-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64:1582; RV64: # %bb.0: # %entry1583; RV64-NEXT: csrwi vxrm, 01584; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu1585; RV64-NEXT: vsmul.vx v8, v12, a0, v0.t1586; RV64-NEXT: ret1587entry:1588 %a = call <vscale x 4 x i64> @llvm.riscv.vsmul.mask.nxv4i64.i64(1589 <vscale x 4 x i64> %0,1590 <vscale x 4 x i64> %1,1591 i64 %2,1592 <vscale x 4 x i1> %3,1593 iXLen 0, iXLen %4, iXLen 1)1594 1595 ret <vscale x 4 x i64> %a1596}1597 1598define <vscale x 8 x i64> @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, iXLen %2) nounwind {1599; RV32-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64:1600; RV32: # %bb.0: # %entry1601; RV32-NEXT: addi sp, sp, -161602; RV32-NEXT: sw a0, 8(sp)1603; RV32-NEXT: sw a1, 12(sp)1604; RV32-NEXT: addi a0, sp, 81605; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1606; RV32-NEXT: vlse64.v v16, (a0), zero1607; RV32-NEXT: csrwi vxrm, 01608; RV32-NEXT: vsmul.vv v8, v8, v161609; RV32-NEXT: addi sp, sp, 161610; RV32-NEXT: ret1611;1612; RV64-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64:1613; RV64: # %bb.0: # %entry1614; RV64-NEXT: csrwi vxrm, 01615; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1616; RV64-NEXT: vsmul.vx v8, v8, a01617; RV64-NEXT: ret1618entry:1619 %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.nxv8i64.i64(1620 <vscale x 8 x i64> poison,1621 <vscale x 8 x i64> %0,1622 i64 %1,1623 iXLen 0, iXLen %2)1624 1625 ret <vscale x 8 x i64> %a1626}1627 1628define <vscale x 8 x i64> @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {1629; RV32-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64:1630; RV32: # %bb.0: # %entry1631; RV32-NEXT: addi sp, sp, -161632; RV32-NEXT: sw a0, 8(sp)1633; RV32-NEXT: sw a1, 12(sp)1634; RV32-NEXT: addi a0, sp, 81635; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, mu1636; RV32-NEXT: vlse64.v v24, (a0), zero1637; RV32-NEXT: csrwi vxrm, 01638; RV32-NEXT: vsmul.vv v8, v16, v24, v0.t1639; RV32-NEXT: addi sp, sp, 161640; RV32-NEXT: ret1641;1642; RV64-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64:1643; RV64: # %bb.0: # %entry1644; RV64-NEXT: csrwi vxrm, 01645; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu1646; RV64-NEXT: vsmul.vx v8, v16, a0, v0.t1647; RV64-NEXT: ret1648entry:1649 %a = call <vscale x 8 x i64> @llvm.riscv.vsmul.mask.nxv8i64.i64(1650 <vscale x 8 x i64> %0,1651 <vscale x 8 x i64> %1,1652 i64 %2,1653 <vscale x 8 x i1> %3,1654 iXLen 0, iXLen %4, iXLen 1)1655 1656 ret <vscale x 8 x i64> %a1657}1658