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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -verify-machineinstrs \3; RUN: < %s | FileCheck %s4 5; The intrinsics are not supported with RV32.6 7define void @intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {8; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i8_nxv1i8_nxv1i64:9; CHECK: # %bb.0: # %entry10; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma11; CHECK-NEXT: vsoxei64.v v8, (a0), v912; CHECK-NEXT: ret13entry:14 call void @llvm.riscv.vsoxei.nxv1i8.nxv1i64(15 <vscale x 1 x i8> %0,16 ptr %1,17 <vscale x 1 x i64> %2,18 i64 %3)19 20 ret void21}22 23define void @intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i64(<vscale x 1 x i8> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {24; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i8_nxv1i8_nxv1i64:25; CHECK: # %bb.0: # %entry26; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma27; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t28; CHECK-NEXT: ret29entry:30 call void @llvm.riscv.vsoxei.mask.nxv1i8.nxv1i64(31 <vscale x 1 x i8> %0,32 ptr %1,33 <vscale x 1 x i64> %2,34 <vscale x 1 x i1> %3,35 i64 %4)36 37 ret void38}39 40define void @intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {41; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i8_nxv2i8_nxv2i64:42; CHECK: # %bb.0: # %entry43; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma44; CHECK-NEXT: vsoxei64.v v8, (a0), v1045; CHECK-NEXT: ret46entry:47 call void @llvm.riscv.vsoxei.nxv2i8.nxv2i64(48 <vscale x 2 x i8> %0,49 ptr %1,50 <vscale x 2 x i64> %2,51 i64 %3)52 53 ret void54}55 56define void @intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i64(<vscale x 2 x i8> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {57; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i8_nxv2i8_nxv2i64:58; CHECK: # %bb.0: # %entry59; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma60; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t61; CHECK-NEXT: ret62entry:63 call void @llvm.riscv.vsoxei.mask.nxv2i8.nxv2i64(64 <vscale x 2 x i8> %0,65 ptr %1,66 <vscale x 2 x i64> %2,67 <vscale x 2 x i1> %3,68 i64 %4)69 70 ret void71}72 73define void @intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {74; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i8_nxv4i8_nxv4i64:75; CHECK: # %bb.0: # %entry76; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma77; CHECK-NEXT: vsoxei64.v v8, (a0), v1278; CHECK-NEXT: ret79entry:80 call void @llvm.riscv.vsoxei.nxv4i8.nxv4i64(81 <vscale x 4 x i8> %0,82 ptr %1,83 <vscale x 4 x i64> %2,84 i64 %3)85 86 ret void87}88 89define void @intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i64(<vscale x 4 x i8> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {90; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i8_nxv4i8_nxv4i64:91; CHECK: # %bb.0: # %entry92; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma93; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t94; CHECK-NEXT: ret95entry:96 call void @llvm.riscv.vsoxei.mask.nxv4i8.nxv4i64(97 <vscale x 4 x i8> %0,98 ptr %1,99 <vscale x 4 x i64> %2,100 <vscale x 4 x i1> %3,101 i64 %4)102 103 ret void104}105 106define void @intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {107; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i8_nxv8i8_nxv8i64:108; CHECK: # %bb.0: # %entry109; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma110; CHECK-NEXT: vsoxei64.v v8, (a0), v16111; CHECK-NEXT: ret112entry:113 call void @llvm.riscv.vsoxei.nxv8i8.nxv8i64(114 <vscale x 8 x i8> %0,115 ptr %1,116 <vscale x 8 x i64> %2,117 i64 %3)118 119 ret void120}121 122define void @intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64(<vscale x 8 x i8> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {123; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i8_nxv8i8_nxv8i64:124; CHECK: # %bb.0: # %entry125; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma126; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t127; CHECK-NEXT: ret128entry:129 call void @llvm.riscv.vsoxei.mask.nxv8i8.nxv8i64(130 <vscale x 8 x i8> %0,131 ptr %1,132 <vscale x 8 x i64> %2,133 <vscale x 8 x i1> %3,134 i64 %4)135 136 ret void137}138 139define void @intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {140; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i16_nxv1i16_nxv1i64:141; CHECK: # %bb.0: # %entry142; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma143; CHECK-NEXT: vsoxei64.v v8, (a0), v9144; CHECK-NEXT: ret145entry:146 call void @llvm.riscv.vsoxei.nxv1i16.nxv1i64(147 <vscale x 1 x i16> %0,148 ptr %1,149 <vscale x 1 x i64> %2,150 i64 %3)151 152 ret void153}154 155define void @intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i64(<vscale x 1 x i16> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {156; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i16_nxv1i16_nxv1i64:157; CHECK: # %bb.0: # %entry158; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma159; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t160; CHECK-NEXT: ret161entry:162 call void @llvm.riscv.vsoxei.mask.nxv1i16.nxv1i64(163 <vscale x 1 x i16> %0,164 ptr %1,165 <vscale x 1 x i64> %2,166 <vscale x 1 x i1> %3,167 i64 %4)168 169 ret void170}171 172define void @intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {173; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i16_nxv2i16_nxv2i64:174; CHECK: # %bb.0: # %entry175; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma176; CHECK-NEXT: vsoxei64.v v8, (a0), v10177; CHECK-NEXT: ret178entry:179 call void @llvm.riscv.vsoxei.nxv2i16.nxv2i64(180 <vscale x 2 x i16> %0,181 ptr %1,182 <vscale x 2 x i64> %2,183 i64 %3)184 185 ret void186}187 188define void @intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i64(<vscale x 2 x i16> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {189; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i16_nxv2i16_nxv2i64:190; CHECK: # %bb.0: # %entry191; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma192; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t193; CHECK-NEXT: ret194entry:195 call void @llvm.riscv.vsoxei.mask.nxv2i16.nxv2i64(196 <vscale x 2 x i16> %0,197 ptr %1,198 <vscale x 2 x i64> %2,199 <vscale x 2 x i1> %3,200 i64 %4)201 202 ret void203}204 205define void @intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {206; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i16_nxv4i16_nxv4i64:207; CHECK: # %bb.0: # %entry208; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma209; CHECK-NEXT: vsoxei64.v v8, (a0), v12210; CHECK-NEXT: ret211entry:212 call void @llvm.riscv.vsoxei.nxv4i16.nxv4i64(213 <vscale x 4 x i16> %0,214 ptr %1,215 <vscale x 4 x i64> %2,216 i64 %3)217 218 ret void219}220 221define void @intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i64(<vscale x 4 x i16> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {222; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i16_nxv4i16_nxv4i64:223; CHECK: # %bb.0: # %entry224; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma225; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t226; CHECK-NEXT: ret227entry:228 call void @llvm.riscv.vsoxei.mask.nxv4i16.nxv4i64(229 <vscale x 4 x i16> %0,230 ptr %1,231 <vscale x 4 x i64> %2,232 <vscale x 4 x i1> %3,233 i64 %4)234 235 ret void236}237 238define void @intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {239; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i16_nxv8i16_nxv8i64:240; CHECK: # %bb.0: # %entry241; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma242; CHECK-NEXT: vsoxei64.v v8, (a0), v16243; CHECK-NEXT: ret244entry:245 call void @llvm.riscv.vsoxei.nxv8i16.nxv8i64(246 <vscale x 8 x i16> %0,247 ptr %1,248 <vscale x 8 x i64> %2,249 i64 %3)250 251 ret void252}253 254define void @intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64(<vscale x 8 x i16> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {255; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i16_nxv8i16_nxv8i64:256; CHECK: # %bb.0: # %entry257; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma258; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t259; CHECK-NEXT: ret260entry:261 call void @llvm.riscv.vsoxei.mask.nxv8i16.nxv8i64(262 <vscale x 8 x i16> %0,263 ptr %1,264 <vscale x 8 x i64> %2,265 <vscale x 8 x i1> %3,266 i64 %4)267 268 ret void269}270 271define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {272; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i64:273; CHECK: # %bb.0: # %entry274; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma275; CHECK-NEXT: vsoxei64.v v8, (a0), v9276; CHECK-NEXT: ret277entry:278 call void @llvm.riscv.vsoxei.nxv1i32.nxv1i64(279 <vscale x 1 x i32> %0,280 ptr %1,281 <vscale x 1 x i64> %2,282 i64 %3)283 284 ret void285}286 287define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i64(<vscale x 1 x i32> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {288; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i64:289; CHECK: # %bb.0: # %entry290; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma291; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t292; CHECK-NEXT: ret293entry:294 call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i64(295 <vscale x 1 x i32> %0,296 ptr %1,297 <vscale x 1 x i64> %2,298 <vscale x 1 x i1> %3,299 i64 %4)300 301 ret void302}303 304define void @intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {305; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i32_nxv2i32_nxv2i64:306; CHECK: # %bb.0: # %entry307; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma308; CHECK-NEXT: vsoxei64.v v8, (a0), v10309; CHECK-NEXT: ret310entry:311 call void @llvm.riscv.vsoxei.nxv2i32.nxv2i64(312 <vscale x 2 x i32> %0,313 ptr %1,314 <vscale x 2 x i64> %2,315 i64 %3)316 317 ret void318}319 320define void @intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i64(<vscale x 2 x i32> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {321; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i32_nxv2i32_nxv2i64:322; CHECK: # %bb.0: # %entry323; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma324; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t325; CHECK-NEXT: ret326entry:327 call void @llvm.riscv.vsoxei.mask.nxv2i32.nxv2i64(328 <vscale x 2 x i32> %0,329 ptr %1,330 <vscale x 2 x i64> %2,331 <vscale x 2 x i1> %3,332 i64 %4)333 334 ret void335}336 337define void @intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {338; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i32_nxv4i32_nxv4i64:339; CHECK: # %bb.0: # %entry340; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma341; CHECK-NEXT: vsoxei64.v v8, (a0), v12342; CHECK-NEXT: ret343entry:344 call void @llvm.riscv.vsoxei.nxv4i32.nxv4i64(345 <vscale x 4 x i32> %0,346 ptr %1,347 <vscale x 4 x i64> %2,348 i64 %3)349 350 ret void351}352 353define void @intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i64(<vscale x 4 x i32> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {354; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i32_nxv4i32_nxv4i64:355; CHECK: # %bb.0: # %entry356; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma357; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t358; CHECK-NEXT: ret359entry:360 call void @llvm.riscv.vsoxei.mask.nxv4i32.nxv4i64(361 <vscale x 4 x i32> %0,362 ptr %1,363 <vscale x 4 x i64> %2,364 <vscale x 4 x i1> %3,365 i64 %4)366 367 ret void368}369 370define void @intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {371; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i32_nxv8i32_nxv8i64:372; CHECK: # %bb.0: # %entry373; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma374; CHECK-NEXT: vsoxei64.v v8, (a0), v16375; CHECK-NEXT: ret376entry:377 call void @llvm.riscv.vsoxei.nxv8i32.nxv8i64(378 <vscale x 8 x i32> %0,379 ptr %1,380 <vscale x 8 x i64> %2,381 i64 %3)382 383 ret void384}385 386define void @intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64(<vscale x 8 x i32> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {387; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i32_nxv8i32_nxv8i64:388; CHECK: # %bb.0: # %entry389; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma390; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t391; CHECK-NEXT: ret392entry:393 call void @llvm.riscv.vsoxei.mask.nxv8i32.nxv8i64(394 <vscale x 8 x i32> %0,395 ptr %1,396 <vscale x 8 x i64> %2,397 <vscale x 8 x i1> %3,398 i64 %4)399 400 ret void401}402 403define void @intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {404; CHECK-LABEL: intrinsic_vsoxei_v_nxv1i64_nxv1i64_nxv1i64:405; CHECK: # %bb.0: # %entry406; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma407; CHECK-NEXT: vsoxei64.v v8, (a0), v9408; CHECK-NEXT: ret409entry:410 call void @llvm.riscv.vsoxei.nxv1i64.nxv1i64(411 <vscale x 1 x i64> %0,412 ptr %1,413 <vscale x 1 x i64> %2,414 i64 %3)415 416 ret void417}418 419define void @intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {420; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1i64_nxv1i64_nxv1i64:421; CHECK: # %bb.0: # %entry422; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma423; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t424; CHECK-NEXT: ret425entry:426 call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64(427 <vscale x 1 x i64> %0,428 ptr %1,429 <vscale x 1 x i64> %2,430 <vscale x 1 x i1> %3,431 i64 %4)432 433 ret void434}435 436define void @intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {437; CHECK-LABEL: intrinsic_vsoxei_v_nxv2i64_nxv2i64_nxv2i64:438; CHECK: # %bb.0: # %entry439; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma440; CHECK-NEXT: vsoxei64.v v8, (a0), v10441; CHECK-NEXT: ret442entry:443 call void @llvm.riscv.vsoxei.nxv2i64.nxv2i64(444 <vscale x 2 x i64> %0,445 ptr %1,446 <vscale x 2 x i64> %2,447 i64 %3)448 449 ret void450}451 452define void @intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {453; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2i64_nxv2i64_nxv2i64:454; CHECK: # %bb.0: # %entry455; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma456; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t457; CHECK-NEXT: ret458entry:459 call void @llvm.riscv.vsoxei.mask.nxv2i64.nxv2i64(460 <vscale x 2 x i64> %0,461 ptr %1,462 <vscale x 2 x i64> %2,463 <vscale x 2 x i1> %3,464 i64 %4)465 466 ret void467}468 469define void @intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {470; CHECK-LABEL: intrinsic_vsoxei_v_nxv4i64_nxv4i64_nxv4i64:471; CHECK: # %bb.0: # %entry472; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma473; CHECK-NEXT: vsoxei64.v v8, (a0), v12474; CHECK-NEXT: ret475entry:476 call void @llvm.riscv.vsoxei.nxv4i64.nxv4i64(477 <vscale x 4 x i64> %0,478 ptr %1,479 <vscale x 4 x i64> %2,480 i64 %3)481 482 ret void483}484 485define void @intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {486; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4i64_nxv4i64_nxv4i64:487; CHECK: # %bb.0: # %entry488; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma489; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t490; CHECK-NEXT: ret491entry:492 call void @llvm.riscv.vsoxei.mask.nxv4i64.nxv4i64(493 <vscale x 4 x i64> %0,494 ptr %1,495 <vscale x 4 x i64> %2,496 <vscale x 4 x i1> %3,497 i64 %4)498 499 ret void500}501 502define void @intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {503; CHECK-LABEL: intrinsic_vsoxei_v_nxv8i64_nxv8i64_nxv8i64:504; CHECK: # %bb.0: # %entry505; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma506; CHECK-NEXT: vsoxei64.v v8, (a0), v16507; CHECK-NEXT: ret508entry:509 call void @llvm.riscv.vsoxei.nxv8i64.nxv8i64(510 <vscale x 8 x i64> %0,511 ptr %1,512 <vscale x 8 x i64> %2,513 i64 %3)514 515 ret void516}517 518define void @intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {519; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8i64_nxv8i64_nxv8i64:520; CHECK: # %bb.0: # %entry521; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma522; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t523; CHECK-NEXT: ret524entry:525 call void @llvm.riscv.vsoxei.mask.nxv8i64.nxv8i64(526 <vscale x 8 x i64> %0,527 ptr %1,528 <vscale x 8 x i64> %2,529 <vscale x 8 x i1> %3,530 i64 %4)531 532 ret void533}534 535define void @intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {536; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f16_nxv1f16_nxv1i64:537; CHECK: # %bb.0: # %entry538; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma539; CHECK-NEXT: vsoxei64.v v8, (a0), v9540; CHECK-NEXT: ret541entry:542 call void @llvm.riscv.vsoxei.nxv1f16.nxv1i64(543 <vscale x 1 x half> %0,544 ptr %1,545 <vscale x 1 x i64> %2,546 i64 %3)547 548 ret void549}550 551define void @intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i64(<vscale x 1 x half> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {552; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f16_nxv1f16_nxv1i64:553; CHECK: # %bb.0: # %entry554; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma555; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t556; CHECK-NEXT: ret557entry:558 call void @llvm.riscv.vsoxei.mask.nxv1f16.nxv1i64(559 <vscale x 1 x half> %0,560 ptr %1,561 <vscale x 1 x i64> %2,562 <vscale x 1 x i1> %3,563 i64 %4)564 565 ret void566}567 568define void @intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {569; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f16_nxv2f16_nxv2i64:570; CHECK: # %bb.0: # %entry571; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma572; CHECK-NEXT: vsoxei64.v v8, (a0), v10573; CHECK-NEXT: ret574entry:575 call void @llvm.riscv.vsoxei.nxv2f16.nxv2i64(576 <vscale x 2 x half> %0,577 ptr %1,578 <vscale x 2 x i64> %2,579 i64 %3)580 581 ret void582}583 584define void @intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i64(<vscale x 2 x half> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {585; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f16_nxv2f16_nxv2i64:586; CHECK: # %bb.0: # %entry587; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma588; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t589; CHECK-NEXT: ret590entry:591 call void @llvm.riscv.vsoxei.mask.nxv2f16.nxv2i64(592 <vscale x 2 x half> %0,593 ptr %1,594 <vscale x 2 x i64> %2,595 <vscale x 2 x i1> %3,596 i64 %4)597 598 ret void599}600 601define void @intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {602; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f16_nxv4f16_nxv4i64:603; CHECK: # %bb.0: # %entry604; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma605; CHECK-NEXT: vsoxei64.v v8, (a0), v12606; CHECK-NEXT: ret607entry:608 call void @llvm.riscv.vsoxei.nxv4f16.nxv4i64(609 <vscale x 4 x half> %0,610 ptr %1,611 <vscale x 4 x i64> %2,612 i64 %3)613 614 ret void615}616 617define void @intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i64(<vscale x 4 x half> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {618; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f16_nxv4f16_nxv4i64:619; CHECK: # %bb.0: # %entry620; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma621; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t622; CHECK-NEXT: ret623entry:624 call void @llvm.riscv.vsoxei.mask.nxv4f16.nxv4i64(625 <vscale x 4 x half> %0,626 ptr %1,627 <vscale x 4 x i64> %2,628 <vscale x 4 x i1> %3,629 i64 %4)630 631 ret void632}633 634define void @intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {635; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f16_nxv8f16_nxv8i64:636; CHECK: # %bb.0: # %entry637; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma638; CHECK-NEXT: vsoxei64.v v8, (a0), v16639; CHECK-NEXT: ret640entry:641 call void @llvm.riscv.vsoxei.nxv8f16.nxv8i64(642 <vscale x 8 x half> %0,643 ptr %1,644 <vscale x 8 x i64> %2,645 i64 %3)646 647 ret void648}649 650define void @intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64(<vscale x 8 x half> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {651; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f16_nxv8f16_nxv8i64:652; CHECK: # %bb.0: # %entry653; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma654; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t655; CHECK-NEXT: ret656entry:657 call void @llvm.riscv.vsoxei.mask.nxv8f16.nxv8i64(658 <vscale x 8 x half> %0,659 ptr %1,660 <vscale x 8 x i64> %2,661 <vscale x 8 x i1> %3,662 i64 %4)663 664 ret void665}666 667define void @intrinsic_vsoxei_v_nxv1bf16_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {668; CHECK-LABEL: intrinsic_vsoxei_v_nxv1bf16_nxv1bf16_nxv1i64:669; CHECK: # %bb.0: # %entry670; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma671; CHECK-NEXT: vsoxei64.v v8, (a0), v9672; CHECK-NEXT: ret673entry:674 call void @llvm.riscv.vsoxei.nxv1bf16.nxv1i64(675 <vscale x 1 x bfloat> %0,676 ptr %1,677 <vscale x 1 x i64> %2,678 i64 %3)679 680 ret void681}682 683define void @intrinsic_vsoxei_mask_v_nxv1bf16_nxv1bf16_nxv1i64(<vscale x 1 x bfloat> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {684; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1bf16_nxv1bf16_nxv1i64:685; CHECK: # %bb.0: # %entry686; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma687; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t688; CHECK-NEXT: ret689entry:690 call void @llvm.riscv.vsoxei.mask.nxv1bf16.nxv1i64(691 <vscale x 1 x bfloat> %0,692 ptr %1,693 <vscale x 1 x i64> %2,694 <vscale x 1 x i1> %3,695 i64 %4)696 697 ret void698}699 700define void @intrinsic_vsoxei_v_nxv2bf16_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {701; CHECK-LABEL: intrinsic_vsoxei_v_nxv2bf16_nxv2bf16_nxv2i64:702; CHECK: # %bb.0: # %entry703; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma704; CHECK-NEXT: vsoxei64.v v8, (a0), v10705; CHECK-NEXT: ret706entry:707 call void @llvm.riscv.vsoxei.nxv2bf16.nxv2i64(708 <vscale x 2 x bfloat> %0,709 ptr %1,710 <vscale x 2 x i64> %2,711 i64 %3)712 713 ret void714}715 716define void @intrinsic_vsoxei_mask_v_nxv2bf16_nxv2bf16_nxv2i64(<vscale x 2 x bfloat> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {717; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2bf16_nxv2bf16_nxv2i64:718; CHECK: # %bb.0: # %entry719; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma720; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t721; CHECK-NEXT: ret722entry:723 call void @llvm.riscv.vsoxei.mask.nxv2bf16.nxv2i64(724 <vscale x 2 x bfloat> %0,725 ptr %1,726 <vscale x 2 x i64> %2,727 <vscale x 2 x i1> %3,728 i64 %4)729 730 ret void731}732 733define void @intrinsic_vsoxei_v_nxv4bf16_nxv4bf16_nxv4i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {734; CHECK-LABEL: intrinsic_vsoxei_v_nxv4bf16_nxv4bf16_nxv4i64:735; CHECK: # %bb.0: # %entry736; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma737; CHECK-NEXT: vsoxei64.v v8, (a0), v12738; CHECK-NEXT: ret739entry:740 call void @llvm.riscv.vsoxei.nxv4bf16.nxv4i64(741 <vscale x 4 x bfloat> %0,742 ptr %1,743 <vscale x 4 x i64> %2,744 i64 %3)745 746 ret void747}748 749define void @intrinsic_vsoxei_mask_v_nxv4bf16_nxv4bf16_nxv4i64(<vscale x 4 x bfloat> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {750; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4bf16_nxv4bf16_nxv4i64:751; CHECK: # %bb.0: # %entry752; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma753; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t754; CHECK-NEXT: ret755entry:756 call void @llvm.riscv.vsoxei.mask.nxv4bf16.nxv4i64(757 <vscale x 4 x bfloat> %0,758 ptr %1,759 <vscale x 4 x i64> %2,760 <vscale x 4 x i1> %3,761 i64 %4)762 763 ret void764}765 766define void @intrinsic_vsoxei_v_nxv8bf16_nxv8bf16_nxv8i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {767; CHECK-LABEL: intrinsic_vsoxei_v_nxv8bf16_nxv8bf16_nxv8i64:768; CHECK: # %bb.0: # %entry769; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma770; CHECK-NEXT: vsoxei64.v v8, (a0), v16771; CHECK-NEXT: ret772entry:773 call void @llvm.riscv.vsoxei.nxv8bf16.nxv8i64(774 <vscale x 8 x bfloat> %0,775 ptr %1,776 <vscale x 8 x i64> %2,777 i64 %3)778 779 ret void780}781 782define void @intrinsic_vsoxei_mask_v_nxv8bf16_nxv8bf16_nxv8i64(<vscale x 8 x bfloat> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {783; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8bf16_nxv8bf16_nxv8i64:784; CHECK: # %bb.0: # %entry785; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma786; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t787; CHECK-NEXT: ret788entry:789 call void @llvm.riscv.vsoxei.mask.nxv8bf16.nxv8i64(790 <vscale x 8 x bfloat> %0,791 ptr %1,792 <vscale x 8 x i64> %2,793 <vscale x 8 x i1> %3,794 i64 %4)795 796 ret void797}798 799define void @intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {800; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f32_nxv1f32_nxv1i64:801; CHECK: # %bb.0: # %entry802; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma803; CHECK-NEXT: vsoxei64.v v8, (a0), v9804; CHECK-NEXT: ret805entry:806 call void @llvm.riscv.vsoxei.nxv1f32.nxv1i64(807 <vscale x 1 x float> %0,808 ptr %1,809 <vscale x 1 x i64> %2,810 i64 %3)811 812 ret void813}814 815define void @intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i64(<vscale x 1 x float> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {816; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f32_nxv1f32_nxv1i64:817; CHECK: # %bb.0: # %entry818; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma819; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t820; CHECK-NEXT: ret821entry:822 call void @llvm.riscv.vsoxei.mask.nxv1f32.nxv1i64(823 <vscale x 1 x float> %0,824 ptr %1,825 <vscale x 1 x i64> %2,826 <vscale x 1 x i1> %3,827 i64 %4)828 829 ret void830}831 832define void @intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {833; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f32_nxv2f32_nxv2i64:834; CHECK: # %bb.0: # %entry835; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma836; CHECK-NEXT: vsoxei64.v v8, (a0), v10837; CHECK-NEXT: ret838entry:839 call void @llvm.riscv.vsoxei.nxv2f32.nxv2i64(840 <vscale x 2 x float> %0,841 ptr %1,842 <vscale x 2 x i64> %2,843 i64 %3)844 845 ret void846}847 848define void @intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i64(<vscale x 2 x float> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {849; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f32_nxv2f32_nxv2i64:850; CHECK: # %bb.0: # %entry851; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma852; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t853; CHECK-NEXT: ret854entry:855 call void @llvm.riscv.vsoxei.mask.nxv2f32.nxv2i64(856 <vscale x 2 x float> %0,857 ptr %1,858 <vscale x 2 x i64> %2,859 <vscale x 2 x i1> %3,860 i64 %4)861 862 ret void863}864 865define void @intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {866; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f32_nxv4f32_nxv4i64:867; CHECK: # %bb.0: # %entry868; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma869; CHECK-NEXT: vsoxei64.v v8, (a0), v12870; CHECK-NEXT: ret871entry:872 call void @llvm.riscv.vsoxei.nxv4f32.nxv4i64(873 <vscale x 4 x float> %0,874 ptr %1,875 <vscale x 4 x i64> %2,876 i64 %3)877 878 ret void879}880 881define void @intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i64(<vscale x 4 x float> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {882; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f32_nxv4f32_nxv4i64:883; CHECK: # %bb.0: # %entry884; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma885; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t886; CHECK-NEXT: ret887entry:888 call void @llvm.riscv.vsoxei.mask.nxv4f32.nxv4i64(889 <vscale x 4 x float> %0,890 ptr %1,891 <vscale x 4 x i64> %2,892 <vscale x 4 x i1> %3,893 i64 %4)894 895 ret void896}897 898define void @intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {899; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f32_nxv8f32_nxv8i64:900; CHECK: # %bb.0: # %entry901; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma902; CHECK-NEXT: vsoxei64.v v8, (a0), v16903; CHECK-NEXT: ret904entry:905 call void @llvm.riscv.vsoxei.nxv8f32.nxv8i64(906 <vscale x 8 x float> %0,907 ptr %1,908 <vscale x 8 x i64> %2,909 i64 %3)910 911 ret void912}913 914define void @intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64(<vscale x 8 x float> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {915; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f32_nxv8f32_nxv8i64:916; CHECK: # %bb.0: # %entry917; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma918; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t919; CHECK-NEXT: ret920entry:921 call void @llvm.riscv.vsoxei.mask.nxv8f32.nxv8i64(922 <vscale x 8 x float> %0,923 ptr %1,924 <vscale x 8 x i64> %2,925 <vscale x 8 x i1> %3,926 i64 %4)927 928 ret void929}930 931define void @intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i64> %2, i64 %3) nounwind {932; CHECK-LABEL: intrinsic_vsoxei_v_nxv1f64_nxv1f64_nxv1i64:933; CHECK: # %bb.0: # %entry934; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma935; CHECK-NEXT: vsoxei64.v v8, (a0), v9936; CHECK-NEXT: ret937entry:938 call void @llvm.riscv.vsoxei.nxv1f64.nxv1i64(939 <vscale x 1 x double> %0,940 ptr %1,941 <vscale x 1 x i64> %2,942 i64 %3)943 944 ret void945}946 947define void @intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, ptr %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {948; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv1f64_nxv1f64_nxv1i64:949; CHECK: # %bb.0: # %entry950; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma951; CHECK-NEXT: vsoxei64.v v8, (a0), v9, v0.t952; CHECK-NEXT: ret953entry:954 call void @llvm.riscv.vsoxei.mask.nxv1f64.nxv1i64(955 <vscale x 1 x double> %0,956 ptr %1,957 <vscale x 1 x i64> %2,958 <vscale x 1 x i1> %3,959 i64 %4)960 961 ret void962}963 964define void @intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i64> %2, i64 %3) nounwind {965; CHECK-LABEL: intrinsic_vsoxei_v_nxv2f64_nxv2f64_nxv2i64:966; CHECK: # %bb.0: # %entry967; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma968; CHECK-NEXT: vsoxei64.v v8, (a0), v10969; CHECK-NEXT: ret970entry:971 call void @llvm.riscv.vsoxei.nxv2f64.nxv2i64(972 <vscale x 2 x double> %0,973 ptr %1,974 <vscale x 2 x i64> %2,975 i64 %3)976 977 ret void978}979 980define void @intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, ptr %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {981; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv2f64_nxv2f64_nxv2i64:982; CHECK: # %bb.0: # %entry983; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma984; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t985; CHECK-NEXT: ret986entry:987 call void @llvm.riscv.vsoxei.mask.nxv2f64.nxv2i64(988 <vscale x 2 x double> %0,989 ptr %1,990 <vscale x 2 x i64> %2,991 <vscale x 2 x i1> %3,992 i64 %4)993 994 ret void995}996 997define void @intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i64> %2, i64 %3) nounwind {998; CHECK-LABEL: intrinsic_vsoxei_v_nxv4f64_nxv4f64_nxv4i64:999; CHECK: # %bb.0: # %entry1000; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1001; CHECK-NEXT: vsoxei64.v v8, (a0), v121002; CHECK-NEXT: ret1003entry:1004 call void @llvm.riscv.vsoxei.nxv4f64.nxv4i64(1005 <vscale x 4 x double> %0,1006 ptr %1,1007 <vscale x 4 x i64> %2,1008 i64 %3)1009 1010 ret void1011}1012 1013define void @intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, ptr %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {1014; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv4f64_nxv4f64_nxv4i64:1015; CHECK: # %bb.0: # %entry1016; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma1017; CHECK-NEXT: vsoxei64.v v8, (a0), v12, v0.t1018; CHECK-NEXT: ret1019entry:1020 call void @llvm.riscv.vsoxei.mask.nxv4f64.nxv4i64(1021 <vscale x 4 x double> %0,1022 ptr %1,1023 <vscale x 4 x i64> %2,1024 <vscale x 4 x i1> %3,1025 i64 %4)1026 1027 ret void1028}1029 1030define void @intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i64> %2, i64 %3) nounwind {1031; CHECK-LABEL: intrinsic_vsoxei_v_nxv8f64_nxv8f64_nxv8i64:1032; CHECK: # %bb.0: # %entry1033; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1034; CHECK-NEXT: vsoxei64.v v8, (a0), v161035; CHECK-NEXT: ret1036entry:1037 call void @llvm.riscv.vsoxei.nxv8f64.nxv8i64(1038 <vscale x 8 x double> %0,1039 ptr %1,1040 <vscale x 8 x i64> %2,1041 i64 %3)1042 1043 ret void1044}1045 1046define void @intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, ptr %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {1047; CHECK-LABEL: intrinsic_vsoxei_mask_v_nxv8f64_nxv8f64_nxv8i64:1048; CHECK: # %bb.0: # %entry1049; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma1050; CHECK-NEXT: vsoxei64.v v8, (a0), v16, v0.t1051; CHECK-NEXT: ret1052entry:1053 call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64(1054 <vscale x 8 x double> %0,1055 ptr %1,1056 <vscale x 8 x i64> %2,1057 <vscale x 8 x i1> %3,1058 i64 %4)1059 1060 ret void1061}1062