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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV32V4; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV64V6 7define <vscale x 8 x i64> @vsplat_nxv8i64_1() {8; CHECK-LABEL: vsplat_nxv8i64_1:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma11; CHECK-NEXT: vmv.v.i v8, -112; CHECK-NEXT: ret13 ret <vscale x 8 x i64> splat (i64 -1)14}15 16define <vscale x 8 x i64> @vsplat_nxv8i64_2() {17; CHECK-LABEL: vsplat_nxv8i64_2:18; CHECK: # %bb.0:19; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma20; CHECK-NEXT: vmv.v.i v8, 421; CHECK-NEXT: ret22 ret <vscale x 8 x i64> splat (i64 4)23}24 25define <vscale x 8 x i64> @vsplat_nxv8i64_3() {26; CHECK-LABEL: vsplat_nxv8i64_3:27; CHECK: # %bb.0:28; CHECK-NEXT: li a0, 25529; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma30; CHECK-NEXT: vmv.v.x v8, a031; CHECK-NEXT: ret32 ret <vscale x 8 x i64> splat (i64 255)33}34 35define <vscale x 8 x i64> @vsplat_nxv8i64_4() {36; RV32V-LABEL: vsplat_nxv8i64_4:37; RV32V: # %bb.0:38; RV32V-NEXT: addi sp, sp, -1639; RV32V-NEXT: .cfi_def_cfa_offset 1640; RV32V-NEXT: lui a0, 102809641; RV32V-NEXT: addi a0, a0, -128142; RV32V-NEXT: sw a0, 8(sp)43; RV32V-NEXT: sw zero, 12(sp)44; RV32V-NEXT: addi a0, sp, 845; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma46; RV32V-NEXT: vlse64.v v8, (a0), zero47; RV32V-NEXT: addi sp, sp, 1648; RV32V-NEXT: .cfi_def_cfa_offset 049; RV32V-NEXT: ret50;51; RV64V-LABEL: vsplat_nxv8i64_4:52; RV64V: # %bb.0:53; RV64V-NEXT: li a0, 25154; RV64V-NEXT: slli a0, a0, 2455; RV64V-NEXT: addi a0, a0, -128156; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma57; RV64V-NEXT: vmv.v.x v8, a058; RV64V-NEXT: ret59 ret <vscale x 8 x i64> splat (i64 4211079935)60}61 62define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) {63; RV32V-LABEL: vsplat_nxv8i64_5:64; RV32V: # %bb.0:65; RV32V-NEXT: addi sp, sp, -1666; RV32V-NEXT: .cfi_def_cfa_offset 1667; RV32V-NEXT: sw a0, 8(sp)68; RV32V-NEXT: sw a1, 12(sp)69; RV32V-NEXT: addi a0, sp, 870; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma71; RV32V-NEXT: vlse64.v v8, (a0), zero72; RV32V-NEXT: addi sp, sp, 1673; RV32V-NEXT: .cfi_def_cfa_offset 074; RV32V-NEXT: ret75;76; RV64V-LABEL: vsplat_nxv8i64_5:77; RV64V: # %bb.0:78; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma79; RV64V-NEXT: vmv.v.x v8, a080; RV64V-NEXT: ret81 %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 082 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer83 ret <vscale x 8 x i64> %splat84}85 86define <vscale x 8 x i64> @vadd_vx_nxv8i64_6(<vscale x 8 x i64> %v) {87; CHECK-LABEL: vadd_vx_nxv8i64_6:88; CHECK: # %bb.0:89; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma90; CHECK-NEXT: vadd.vi v8, v8, 291; CHECK-NEXT: ret92 %vret = add <vscale x 8 x i64> %v, splat (i64 2)93 ret <vscale x 8 x i64> %vret94}95 96define <vscale x 8 x i64> @vadd_vx_nxv8i64_7(<vscale x 8 x i64> %v) {97; CHECK-LABEL: vadd_vx_nxv8i64_7:98; CHECK: # %bb.0:99; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma100; CHECK-NEXT: vadd.vi v8, v8, -1101; CHECK-NEXT: ret102 %vret = add <vscale x 8 x i64> %v, splat (i64 -1)103 ret <vscale x 8 x i64> %vret104}105 106define <vscale x 8 x i64> @vadd_vx_nxv8i64_8(<vscale x 8 x i64> %v) {107; CHECK-LABEL: vadd_vx_nxv8i64_8:108; CHECK: # %bb.0:109; CHECK-NEXT: li a0, 255110; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma111; CHECK-NEXT: vadd.vx v8, v8, a0112; CHECK-NEXT: ret113 %vret = add <vscale x 8 x i64> %v, splat (i64 255)114 ret <vscale x 8 x i64> %vret115}116 117define <vscale x 8 x i64> @vadd_vx_nxv8i64_9(<vscale x 8 x i64> %v) {118; CHECK-LABEL: vadd_vx_nxv8i64_9:119; CHECK: # %bb.0:120; CHECK-NEXT: lui a0, 503808121; CHECK-NEXT: addi a0, a0, -1281122; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma123; CHECK-NEXT: vadd.vx v8, v8, a0124; CHECK-NEXT: ret125 %vret = add <vscale x 8 x i64> %v, splat (i64 2063596287)126 ret <vscale x 8 x i64> %vret127}128 129define <vscale x 8 x i64> @vadd_vx_nxv8i64_10(<vscale x 8 x i64> %v) {130; RV32V-LABEL: vadd_vx_nxv8i64_10:131; RV32V: # %bb.0:132; RV32V-NEXT: addi sp, sp, -16133; RV32V-NEXT: .cfi_def_cfa_offset 16134; RV32V-NEXT: lui a0, 1028096135; RV32V-NEXT: addi a0, a0, -1281136; RV32V-NEXT: sw a0, 8(sp)137; RV32V-NEXT: sw zero, 12(sp)138; RV32V-NEXT: addi a0, sp, 8139; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma140; RV32V-NEXT: vlse64.v v16, (a0), zero141; RV32V-NEXT: vadd.vv v8, v8, v16142; RV32V-NEXT: addi sp, sp, 16143; RV32V-NEXT: .cfi_def_cfa_offset 0144; RV32V-NEXT: ret145;146; RV64V-LABEL: vadd_vx_nxv8i64_10:147; RV64V: # %bb.0:148; RV64V-NEXT: li a0, 251149; RV64V-NEXT: slli a0, a0, 24150; RV64V-NEXT: addi a0, a0, -1281151; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma152; RV64V-NEXT: vadd.vx v8, v8, a0153; RV64V-NEXT: ret154 %vret = add <vscale x 8 x i64> %v, splat (i64 4211079935)155 ret <vscale x 8 x i64> %vret156}157 158define <vscale x 8 x i64> @vadd_vx_nxv8i64_11(<vscale x 8 x i64> %v) {159; RV32V-LABEL: vadd_vx_nxv8i64_11:160; RV32V: # %bb.0:161; RV32V-NEXT: addi sp, sp, -16162; RV32V-NEXT: .cfi_def_cfa_offset 16163; RV32V-NEXT: li a0, 1164; RV32V-NEXT: lui a1, 1028096165; RV32V-NEXT: addi a1, a1, -1281166; RV32V-NEXT: sw a1, 8(sp)167; RV32V-NEXT: sw a0, 12(sp)168; RV32V-NEXT: addi a0, sp, 8169; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma170; RV32V-NEXT: vlse64.v v16, (a0), zero171; RV32V-NEXT: vadd.vv v8, v8, v16172; RV32V-NEXT: addi sp, sp, 16173; RV32V-NEXT: .cfi_def_cfa_offset 0174; RV32V-NEXT: ret175;176; RV64V-LABEL: vadd_vx_nxv8i64_11:177; RV64V: # %bb.0:178; RV64V-NEXT: li a0, 507179; RV64V-NEXT: slli a0, a0, 24180; RV64V-NEXT: addi a0, a0, -1281181; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma182; RV64V-NEXT: vadd.vx v8, v8, a0183; RV64V-NEXT: ret184 %vret = add <vscale x 8 x i64> %v, splat (i64 8506047231)185 ret <vscale x 8 x i64> %vret186}187 188define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) {189; RV32V-LABEL: vadd_vx_nxv8i64_12:190; RV32V: # %bb.0:191; RV32V-NEXT: addi sp, sp, -16192; RV32V-NEXT: .cfi_def_cfa_offset 16193; RV32V-NEXT: sw a0, 8(sp)194; RV32V-NEXT: sw a1, 12(sp)195; RV32V-NEXT: addi a0, sp, 8196; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma197; RV32V-NEXT: vlse64.v v16, (a0), zero198; RV32V-NEXT: vadd.vv v8, v8, v16199; RV32V-NEXT: addi sp, sp, 16200; RV32V-NEXT: .cfi_def_cfa_offset 0201; RV32V-NEXT: ret202;203; RV64V-LABEL: vadd_vx_nxv8i64_12:204; RV64V: # %bb.0:205; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma206; RV64V-NEXT: vadd.vx v8, v8, a0207; RV64V-NEXT: ret208 %head = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0209 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer210 %vret = add <vscale x 8 x i64> %v, %splat211 ret <vscale x 8 x i64> %vret212}213 214define <vscale x 8 x i64> @vsplat_nxv8i64_13(i32 %a) {215; RV32V-LABEL: vsplat_nxv8i64_13:216; RV32V: # %bb.0:217; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma218; RV32V-NEXT: vmv.v.x v8, a0219; RV32V-NEXT: ret220;221; RV64V-LABEL: vsplat_nxv8i64_13:222; RV64V: # %bb.0:223; RV64V-NEXT: sext.w a0, a0224; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma225; RV64V-NEXT: vmv.v.x v8, a0226; RV64V-NEXT: ret227 %b = sext i32 %a to i64228 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0229 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer230 ret <vscale x 8 x i64> %splat231}232 233define <vscale x 8 x i64> @vsplat_nxv8i64_14(i32 %a) {234; RV32V-LABEL: vsplat_nxv8i64_14:235; RV32V: # %bb.0:236; RV32V-NEXT: addi sp, sp, -16237; RV32V-NEXT: .cfi_def_cfa_offset 16238; RV32V-NEXT: sw a0, 8(sp)239; RV32V-NEXT: sw zero, 12(sp)240; RV32V-NEXT: addi a0, sp, 8241; RV32V-NEXT: vsetvli a1, zero, e64, m8, ta, ma242; RV32V-NEXT: vlse64.v v8, (a0), zero243; RV32V-NEXT: addi sp, sp, 16244; RV32V-NEXT: .cfi_def_cfa_offset 0245; RV32V-NEXT: ret246;247; RV64V-LABEL: vsplat_nxv8i64_14:248; RV64V: # %bb.0:249; RV64V-NEXT: slli a0, a0, 32250; RV64V-NEXT: srli a0, a0, 32251; RV64V-NEXT: vsetvli a1, zero, e64, m8, ta, ma252; RV64V-NEXT: vmv.v.x v8, a0253; RV64V-NEXT: ret254 %b = zext i32 %a to i64255 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0256 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer257 ret <vscale x 8 x i64> %splat258}259