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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s4 5define <vscale x 1 x i8> @vsra_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {6; CHECK-LABEL: vsra_vv_nxv1i8:7; CHECK: # %bb.0:8; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma9; CHECK-NEXT: vsra.vv v8, v8, v910; CHECK-NEXT: ret11 %vc = ashr <vscale x 1 x i8> %va, %vb12 ret <vscale x 1 x i8> %vc13}14 15define <vscale x 1 x i8> @vsra_vv_nxv1i8_sext_zext(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {16; CHECK-LABEL: vsra_vv_nxv1i8_sext_zext:17; CHECK: # %bb.0:18; CHECK-NEXT: li a0, 719; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma20; CHECK-NEXT: vmin.vx v9, v8, a021; CHECK-NEXT: vsra.vv v8, v8, v922; CHECK-NEXT: ret23 %sexted_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>24 %zexted_vb = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>25 %expand = ashr <vscale x 1 x i32> %sexted_va, %zexted_vb26 %vc = trunc <vscale x 1 x i32> %expand to <vscale x 1 x i8>27 ret <vscale x 1 x i8> %vc28}29 30define <vscale x 1 x i8> @vsra_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {31; CHECK-LABEL: vsra_vx_nxv1i8:32; CHECK: # %bb.0:33; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma34; CHECK-NEXT: vsra.vx v8, v8, a035; CHECK-NEXT: ret36 %head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 037 %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer38 %vc = ashr <vscale x 1 x i8> %va, %splat39 ret <vscale x 1 x i8> %vc40}41 42define <vscale x 1 x i8> @vsra_vi_nxv1i8_0(<vscale x 1 x i8> %va) {43; CHECK-LABEL: vsra_vi_nxv1i8_0:44; CHECK: # %bb.0:45; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma46; CHECK-NEXT: vsra.vi v8, v8, 647; CHECK-NEXT: ret48 %vc = ashr <vscale x 1 x i8> %va, splat (i8 6)49 ret <vscale x 1 x i8> %vc50}51 52define <vscale x 2 x i8> @vsra_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {53; CHECK-LABEL: vsra_vv_nxv2i8:54; CHECK: # %bb.0:55; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma56; CHECK-NEXT: vsra.vv v8, v8, v957; CHECK-NEXT: ret58 %vc = ashr <vscale x 2 x i8> %va, %vb59 ret <vscale x 2 x i8> %vc60}61 62define <vscale x 2 x i8> @vsra_vv_nxv2i8_sext_zext(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb) {63; CHECK-LABEL: vsra_vv_nxv2i8_sext_zext:64; CHECK: # %bb.0:65; CHECK-NEXT: li a0, 766; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma67; CHECK-NEXT: vmin.vx v9, v8, a068; CHECK-NEXT: vsra.vv v8, v8, v969; CHECK-NEXT: ret70 %sexted_va = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>71 %zexted_vb = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>72 %expand = ashr <vscale x 2 x i32> %sexted_va, %zexted_vb73 %vc = trunc <vscale x 2 x i32> %expand to <vscale x 2 x i8>74 ret <vscale x 2 x i8> %vc75}76 77define <vscale x 2 x i8> @vsra_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {78; CHECK-LABEL: vsra_vx_nxv2i8:79; CHECK: # %bb.0:80; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma81; CHECK-NEXT: vsra.vx v8, v8, a082; CHECK-NEXT: ret83 %head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 084 %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer85 %vc = ashr <vscale x 2 x i8> %va, %splat86 ret <vscale x 2 x i8> %vc87}88 89define <vscale x 2 x i8> @vsra_vi_nxv2i8_0(<vscale x 2 x i8> %va) {90; CHECK-LABEL: vsra_vi_nxv2i8_0:91; CHECK: # %bb.0:92; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma93; CHECK-NEXT: vsra.vi v8, v8, 694; CHECK-NEXT: ret95 %vc = ashr <vscale x 2 x i8> %va, splat (i8 6)96 ret <vscale x 2 x i8> %vc97}98 99define <vscale x 4 x i8> @vsra_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {100; CHECK-LABEL: vsra_vv_nxv4i8:101; CHECK: # %bb.0:102; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma103; CHECK-NEXT: vsra.vv v8, v8, v9104; CHECK-NEXT: ret105 %vc = ashr <vscale x 4 x i8> %va, %vb106 ret <vscale x 4 x i8> %vc107}108 109define <vscale x 4 x i8> @vsra_vv_nxv4i8_sext_zext(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb) {110; CHECK-LABEL: vsra_vv_nxv4i8_sext_zext:111; CHECK: # %bb.0:112; CHECK-NEXT: li a0, 7113; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma114; CHECK-NEXT: vmin.vx v9, v8, a0115; CHECK-NEXT: vsra.vv v8, v8, v9116; CHECK-NEXT: ret117 %sexted_va = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>118 %zexted_vb = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>119 %expand = ashr <vscale x 4 x i32> %sexted_va, %zexted_vb120 %vc = trunc <vscale x 4 x i32> %expand to <vscale x 4 x i8>121 ret <vscale x 4 x i8> %vc122}123 124define <vscale x 4 x i8> @vsra_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {125; CHECK-LABEL: vsra_vx_nxv4i8:126; CHECK: # %bb.0:127; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma128; CHECK-NEXT: vsra.vx v8, v8, a0129; CHECK-NEXT: ret130 %head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0131 %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer132 %vc = ashr <vscale x 4 x i8> %va, %splat133 ret <vscale x 4 x i8> %vc134}135 136define <vscale x 4 x i8> @vsra_vi_nxv4i8_0(<vscale x 4 x i8> %va) {137; CHECK-LABEL: vsra_vi_nxv4i8_0:138; CHECK: # %bb.0:139; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma140; CHECK-NEXT: vsra.vi v8, v8, 6141; CHECK-NEXT: ret142 %vc = ashr <vscale x 4 x i8> %va, splat (i8 6)143 ret <vscale x 4 x i8> %vc144}145 146define <vscale x 8 x i8> @vsra_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {147; CHECK-LABEL: vsra_vv_nxv8i8:148; CHECK: # %bb.0:149; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma150; CHECK-NEXT: vsra.vv v8, v8, v9151; CHECK-NEXT: ret152 %vc = ashr <vscale x 8 x i8> %va, %vb153 ret <vscale x 8 x i8> %vc154}155 156define <vscale x 8 x i8> @vsra_vv_nxv8i8_sext_zext(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {157; CHECK-LABEL: vsra_vv_nxv8i8_sext_zext:158; CHECK: # %bb.0:159; CHECK-NEXT: li a0, 7160; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma161; CHECK-NEXT: vmin.vx v9, v8, a0162; CHECK-NEXT: vsra.vv v8, v8, v9163; CHECK-NEXT: ret164 %sexted_va = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>165 %zexted_vb = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>166 %expand = ashr <vscale x 8 x i32> %sexted_va, %zexted_vb167 %vc = trunc <vscale x 8 x i32> %expand to <vscale x 8 x i8>168 ret <vscale x 8 x i8> %vc169}170 171define <vscale x 8 x i8> @vsra_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {172; CHECK-LABEL: vsra_vx_nxv8i8:173; CHECK: # %bb.0:174; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma175; CHECK-NEXT: vsra.vx v8, v8, a0176; CHECK-NEXT: ret177 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0178 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer179 %vc = ashr <vscale x 8 x i8> %va, %splat180 ret <vscale x 8 x i8> %vc181}182 183define <vscale x 8 x i8> @vsra_vi_nxv8i8_0(<vscale x 8 x i8> %va) {184; CHECK-LABEL: vsra_vi_nxv8i8_0:185; CHECK: # %bb.0:186; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma187; CHECK-NEXT: vsra.vi v8, v8, 6188; CHECK-NEXT: ret189 %vc = ashr <vscale x 8 x i8> %va, splat (i8 6)190 ret <vscale x 8 x i8> %vc191}192 193define <vscale x 16 x i8> @vsra_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {194; CHECK-LABEL: vsra_vv_nxv16i8:195; CHECK: # %bb.0:196; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma197; CHECK-NEXT: vsra.vv v8, v8, v10198; CHECK-NEXT: ret199 %vc = ashr <vscale x 16 x i8> %va, %vb200 ret <vscale x 16 x i8> %vc201}202 203define <vscale x 16 x i8> @vsra_vv_nxv16i8_sext_zext(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb) {204; CHECK-LABEL: vsra_vv_nxv16i8_sext_zext:205; CHECK: # %bb.0:206; CHECK-NEXT: li a0, 7207; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma208; CHECK-NEXT: vmin.vx v10, v8, a0209; CHECK-NEXT: vsra.vv v8, v8, v10210; CHECK-NEXT: ret211 %sexted_va = sext <vscale x 16 x i8> %va to <vscale x 16 x i32>212 %zexted_vb = zext <vscale x 16 x i8> %va to <vscale x 16 x i32>213 %expand = ashr <vscale x 16 x i32> %sexted_va, %zexted_vb214 %vc = trunc <vscale x 16 x i32> %expand to <vscale x 16 x i8>215 ret <vscale x 16 x i8> %vc216}217 218define <vscale x 16 x i8> @vsra_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {219; CHECK-LABEL: vsra_vx_nxv16i8:220; CHECK: # %bb.0:221; CHECK-NEXT: vsetvli a1, zero, e8, m2, ta, ma222; CHECK-NEXT: vsra.vx v8, v8, a0223; CHECK-NEXT: ret224 %head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0225 %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer226 %vc = ashr <vscale x 16 x i8> %va, %splat227 ret <vscale x 16 x i8> %vc228}229 230define <vscale x 16 x i8> @vsra_vi_nxv16i8_0(<vscale x 16 x i8> %va) {231; CHECK-LABEL: vsra_vi_nxv16i8_0:232; CHECK: # %bb.0:233; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma234; CHECK-NEXT: vsra.vi v8, v8, 6235; CHECK-NEXT: ret236 %vc = ashr <vscale x 16 x i8> %va, splat (i8 6)237 ret <vscale x 16 x i8> %vc238}239 240define <vscale x 32 x i8> @vsra_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb) {241; CHECK-LABEL: vsra_vv_nxv32i8:242; CHECK: # %bb.0:243; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma244; CHECK-NEXT: vsra.vv v8, v8, v12245; CHECK-NEXT: ret246 %vc = ashr <vscale x 32 x i8> %va, %vb247 ret <vscale x 32 x i8> %vc248}249 250define <vscale x 32 x i8> @vsra_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {251; CHECK-LABEL: vsra_vx_nxv32i8:252; CHECK: # %bb.0:253; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma254; CHECK-NEXT: vsra.vx v8, v8, a0255; CHECK-NEXT: ret256 %head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0257 %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer258 %vc = ashr <vscale x 32 x i8> %va, %splat259 ret <vscale x 32 x i8> %vc260}261 262define <vscale x 32 x i8> @vsra_vi_nxv32i8_0(<vscale x 32 x i8> %va) {263; CHECK-LABEL: vsra_vi_nxv32i8_0:264; CHECK: # %bb.0:265; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma266; CHECK-NEXT: vsra.vi v8, v8, 6267; CHECK-NEXT: ret268 %vc = ashr <vscale x 32 x i8> %va, splat (i8 6)269 ret <vscale x 32 x i8> %vc270}271 272define <vscale x 64 x i8> @vsra_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb) {273; CHECK-LABEL: vsra_vv_nxv64i8:274; CHECK: # %bb.0:275; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma276; CHECK-NEXT: vsra.vv v8, v8, v16277; CHECK-NEXT: ret278 %vc = ashr <vscale x 64 x i8> %va, %vb279 ret <vscale x 64 x i8> %vc280}281 282define <vscale x 64 x i8> @vsra_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {283; CHECK-LABEL: vsra_vx_nxv64i8:284; CHECK: # %bb.0:285; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma286; CHECK-NEXT: vsra.vx v8, v8, a0287; CHECK-NEXT: ret288 %head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0289 %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer290 %vc = ashr <vscale x 64 x i8> %va, %splat291 ret <vscale x 64 x i8> %vc292}293 294define <vscale x 64 x i8> @vsra_vi_nxv64i8_0(<vscale x 64 x i8> %va) {295; CHECK-LABEL: vsra_vi_nxv64i8_0:296; CHECK: # %bb.0:297; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma298; CHECK-NEXT: vsra.vi v8, v8, 6299; CHECK-NEXT: ret300 %vc = ashr <vscale x 64 x i8> %va, splat (i8 6)301 ret <vscale x 64 x i8> %vc302}303 304define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {305; CHECK-LABEL: vsra_vv_nxv1i16:306; CHECK: # %bb.0:307; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma308; CHECK-NEXT: vsra.vv v8, v8, v9309; CHECK-NEXT: ret310 %vc = ashr <vscale x 1 x i16> %va, %vb311 ret <vscale x 1 x i16> %vc312}313 314define <vscale x 1 x i16> @vsra_vv_nxv1i16_sext_zext(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb) {315; CHECK-LABEL: vsra_vv_nxv1i16_sext_zext:316; CHECK: # %bb.0:317; CHECK-NEXT: li a0, 15318; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma319; CHECK-NEXT: vmin.vx v9, v8, a0320; CHECK-NEXT: vsra.vv v8, v8, v9321; CHECK-NEXT: ret322 %sexted_va = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>323 %zexted_vb = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>324 %expand = ashr <vscale x 1 x i32> %sexted_va, %zexted_vb325 %vc = trunc <vscale x 1 x i32> %expand to <vscale x 1 x i16>326 ret <vscale x 1 x i16> %vc327}328 329define <vscale x 1 x i16> @vsra_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {330; CHECK-LABEL: vsra_vx_nxv1i16:331; CHECK: # %bb.0:332; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma333; CHECK-NEXT: vsra.vx v8, v8, a0334; CHECK-NEXT: ret335 %head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0336 %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer337 %vc = ashr <vscale x 1 x i16> %va, %splat338 ret <vscale x 1 x i16> %vc339}340 341define <vscale x 1 x i16> @vsra_vi_nxv1i16_0(<vscale x 1 x i16> %va) {342; CHECK-LABEL: vsra_vi_nxv1i16_0:343; CHECK: # %bb.0:344; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma345; CHECK-NEXT: vsra.vi v8, v8, 6346; CHECK-NEXT: ret347 %vc = ashr <vscale x 1 x i16> %va, splat (i16 6)348 ret <vscale x 1 x i16> %vc349}350 351define <vscale x 2 x i16> @vsra_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {352; CHECK-LABEL: vsra_vv_nxv2i16:353; CHECK: # %bb.0:354; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma355; CHECK-NEXT: vsra.vv v8, v8, v9356; CHECK-NEXT: ret357 %vc = ashr <vscale x 2 x i16> %va, %vb358 ret <vscale x 2 x i16> %vc359}360 361define <vscale x 2 x i16> @vsra_vv_nxv2i16_sext_zext(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb) {362; CHECK-LABEL: vsra_vv_nxv2i16_sext_zext:363; CHECK: # %bb.0:364; CHECK-NEXT: li a0, 15365; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma366; CHECK-NEXT: vmin.vx v9, v8, a0367; CHECK-NEXT: vsra.vv v8, v8, v9368; CHECK-NEXT: ret369 %sexted_va = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>370 %zexted_vb = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>371 %expand = ashr <vscale x 2 x i32> %sexted_va, %zexted_vb372 %vc = trunc <vscale x 2 x i32> %expand to <vscale x 2 x i16>373 ret <vscale x 2 x i16> %vc374}375 376define <vscale x 2 x i16> @vsra_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {377; CHECK-LABEL: vsra_vx_nxv2i16:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma380; CHECK-NEXT: vsra.vx v8, v8, a0381; CHECK-NEXT: ret382 %head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0383 %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer384 %vc = ashr <vscale x 2 x i16> %va, %splat385 ret <vscale x 2 x i16> %vc386}387 388define <vscale x 2 x i16> @vsra_vi_nxv2i16_0(<vscale x 2 x i16> %va) {389; CHECK-LABEL: vsra_vi_nxv2i16_0:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma392; CHECK-NEXT: vsra.vi v8, v8, 6393; CHECK-NEXT: ret394 %vc = ashr <vscale x 2 x i16> %va, splat (i16 6)395 ret <vscale x 2 x i16> %vc396}397 398define <vscale x 4 x i16> @vsra_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {399; CHECK-LABEL: vsra_vv_nxv4i16:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma402; CHECK-NEXT: vsra.vv v8, v8, v9403; CHECK-NEXT: ret404 %vc = ashr <vscale x 4 x i16> %va, %vb405 ret <vscale x 4 x i16> %vc406}407 408define <vscale x 4 x i16> @vsra_vv_nxv4i16_sext_zext(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb) {409; CHECK-LABEL: vsra_vv_nxv4i16_sext_zext:410; CHECK: # %bb.0:411; CHECK-NEXT: li a0, 15412; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma413; CHECK-NEXT: vmin.vx v9, v8, a0414; CHECK-NEXT: vsra.vv v8, v8, v9415; CHECK-NEXT: ret416 %sexted_va = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>417 %zexted_vb = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>418 %expand = ashr <vscale x 4 x i32> %sexted_va, %zexted_vb419 %vc = trunc <vscale x 4 x i32> %expand to <vscale x 4 x i16>420 ret <vscale x 4 x i16> %vc421}422 423define <vscale x 4 x i16> @vsra_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {424; CHECK-LABEL: vsra_vx_nxv4i16:425; CHECK: # %bb.0:426; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma427; CHECK-NEXT: vsra.vx v8, v8, a0428; CHECK-NEXT: ret429 %head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0430 %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer431 %vc = ashr <vscale x 4 x i16> %va, %splat432 ret <vscale x 4 x i16> %vc433}434 435define <vscale x 4 x i16> @vsra_vi_nxv4i16_0(<vscale x 4 x i16> %va) {436; CHECK-LABEL: vsra_vi_nxv4i16_0:437; CHECK: # %bb.0:438; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma439; CHECK-NEXT: vsra.vi v8, v8, 6440; CHECK-NEXT: ret441 %vc = ashr <vscale x 4 x i16> %va, splat (i16 6)442 ret <vscale x 4 x i16> %vc443}444 445define <vscale x 8 x i16> @vsra_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {446; CHECK-LABEL: vsra_vv_nxv8i16:447; CHECK: # %bb.0:448; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma449; CHECK-NEXT: vsra.vv v8, v8, v10450; CHECK-NEXT: ret451 %vc = ashr <vscale x 8 x i16> %va, %vb452 ret <vscale x 8 x i16> %vc453}454 455define <vscale x 8 x i16> @vsra_vv_nxv8i16_sext_zext(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {456; CHECK-LABEL: vsra_vv_nxv8i16_sext_zext:457; CHECK: # %bb.0:458; CHECK-NEXT: li a0, 15459; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma460; CHECK-NEXT: vmin.vx v10, v8, a0461; CHECK-NEXT: vsra.vv v8, v8, v10462; CHECK-NEXT: ret463 %sexted_va = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>464 %zexted_vb = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>465 %expand = ashr <vscale x 8 x i32> %sexted_va, %zexted_vb466 %vc = trunc <vscale x 8 x i32> %expand to <vscale x 8 x i16>467 ret <vscale x 8 x i16> %vc468}469 470define <vscale x 8 x i16> @vsra_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {471; CHECK-LABEL: vsra_vx_nxv8i16:472; CHECK: # %bb.0:473; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma474; CHECK-NEXT: vsra.vx v8, v8, a0475; CHECK-NEXT: ret476 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0477 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer478 %vc = ashr <vscale x 8 x i16> %va, %splat479 ret <vscale x 8 x i16> %vc480}481 482define <vscale x 8 x i16> @vsra_vi_nxv8i16_0(<vscale x 8 x i16> %va) {483; CHECK-LABEL: vsra_vi_nxv8i16_0:484; CHECK: # %bb.0:485; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma486; CHECK-NEXT: vsra.vi v8, v8, 6487; CHECK-NEXT: ret488 %vc = ashr <vscale x 8 x i16> %va, splat (i16 6)489 ret <vscale x 8 x i16> %vc490}491 492define <vscale x 16 x i16> @vsra_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {493; CHECK-LABEL: vsra_vv_nxv16i16:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma496; CHECK-NEXT: vsra.vv v8, v8, v12497; CHECK-NEXT: ret498 %vc = ashr <vscale x 16 x i16> %va, %vb499 ret <vscale x 16 x i16> %vc500}501 502define <vscale x 16 x i16> @vsra_vv_nxv16i16_sext_zext(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb) {503; CHECK-LABEL: vsra_vv_nxv16i16_sext_zext:504; CHECK: # %bb.0:505; CHECK-NEXT: li a0, 15506; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma507; CHECK-NEXT: vmin.vx v12, v8, a0508; CHECK-NEXT: vsra.vv v8, v8, v12509; CHECK-NEXT: ret510 %sexted_va = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>511 %zexted_vb = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>512 %expand = ashr <vscale x 16 x i32> %sexted_va, %zexted_vb513 %vc = trunc <vscale x 16 x i32> %expand to <vscale x 16 x i16>514 ret <vscale x 16 x i16> %vc515}516 517define <vscale x 16 x i16> @vsra_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {518; CHECK-LABEL: vsra_vx_nxv16i16:519; CHECK: # %bb.0:520; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma521; CHECK-NEXT: vsra.vx v8, v8, a0522; CHECK-NEXT: ret523 %head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0524 %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer525 %vc = ashr <vscale x 16 x i16> %va, %splat526 ret <vscale x 16 x i16> %vc527}528 529define <vscale x 16 x i16> @vsra_vi_nxv16i16_0(<vscale x 16 x i16> %va) {530; CHECK-LABEL: vsra_vi_nxv16i16_0:531; CHECK: # %bb.0:532; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma533; CHECK-NEXT: vsra.vi v8, v8, 6534; CHECK-NEXT: ret535 %vc = ashr <vscale x 16 x i16> %va, splat (i16 6)536 ret <vscale x 16 x i16> %vc537}538 539define <vscale x 32 x i16> @vsra_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb) {540; CHECK-LABEL: vsra_vv_nxv32i16:541; CHECK: # %bb.0:542; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma543; CHECK-NEXT: vsra.vv v8, v8, v16544; CHECK-NEXT: ret545 %vc = ashr <vscale x 32 x i16> %va, %vb546 ret <vscale x 32 x i16> %vc547}548 549define <vscale x 32 x i16> @vsra_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {550; CHECK-LABEL: vsra_vx_nxv32i16:551; CHECK: # %bb.0:552; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma553; CHECK-NEXT: vsra.vx v8, v8, a0554; CHECK-NEXT: ret555 %head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0556 %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer557 %vc = ashr <vscale x 32 x i16> %va, %splat558 ret <vscale x 32 x i16> %vc559}560 561define <vscale x 32 x i16> @vsra_vi_nxv32i16_0(<vscale x 32 x i16> %va) {562; CHECK-LABEL: vsra_vi_nxv32i16_0:563; CHECK: # %bb.0:564; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma565; CHECK-NEXT: vsra.vi v8, v8, 6566; CHECK-NEXT: ret567 %vc = ashr <vscale x 32 x i16> %va, splat (i16 6)568 ret <vscale x 32 x i16> %vc569}570 571define <vscale x 1 x i32> @vsra_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {572; CHECK-LABEL: vsra_vv_nxv1i32:573; CHECK: # %bb.0:574; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma575; CHECK-NEXT: vsra.vv v8, v8, v9576; CHECK-NEXT: ret577 %vc = ashr <vscale x 1 x i32> %va, %vb578 ret <vscale x 1 x i32> %vc579}580 581define <vscale x 1 x i32> @vsra_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {582; CHECK-LABEL: vsra_vx_nxv1i32:583; CHECK: # %bb.0:584; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma585; CHECK-NEXT: vsra.vx v8, v8, a0586; CHECK-NEXT: ret587 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0588 %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer589 %vc = ashr <vscale x 1 x i32> %va, %splat590 ret <vscale x 1 x i32> %vc591}592 593define <vscale x 1 x i32> @vsra_vi_nxv1i32_0(<vscale x 1 x i32> %va) {594; CHECK-LABEL: vsra_vi_nxv1i32_0:595; CHECK: # %bb.0:596; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma597; CHECK-NEXT: vsra.vi v8, v8, 31598; CHECK-NEXT: ret599 %vc = ashr <vscale x 1 x i32> %va, splat (i32 31)600 ret <vscale x 1 x i32> %vc601}602 603define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {604; CHECK-LABEL: vsra_vv_nxv2i32:605; CHECK: # %bb.0:606; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma607; CHECK-NEXT: vsra.vv v8, v8, v9608; CHECK-NEXT: ret609 %vc = ashr <vscale x 2 x i32> %va, %vb610 ret <vscale x 2 x i32> %vc611}612 613define <vscale x 2 x i32> @vsra_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {614; CHECK-LABEL: vsra_vx_nxv2i32:615; CHECK: # %bb.0:616; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma617; CHECK-NEXT: vsra.vx v8, v8, a0618; CHECK-NEXT: ret619 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0620 %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer621 %vc = ashr <vscale x 2 x i32> %va, %splat622 ret <vscale x 2 x i32> %vc623}624 625define <vscale x 2 x i32> @vsra_vi_nxv2i32_0(<vscale x 2 x i32> %va) {626; CHECK-LABEL: vsra_vi_nxv2i32_0:627; CHECK: # %bb.0:628; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma629; CHECK-NEXT: vsra.vi v8, v8, 31630; CHECK-NEXT: ret631 %vc = ashr <vscale x 2 x i32> %va, splat (i32 31)632 ret <vscale x 2 x i32> %vc633}634 635define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {636; CHECK-LABEL: vsra_vv_nxv4i32:637; CHECK: # %bb.0:638; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma639; CHECK-NEXT: vsra.vv v8, v8, v10640; CHECK-NEXT: ret641 %vc = ashr <vscale x 4 x i32> %va, %vb642 ret <vscale x 4 x i32> %vc643}644 645define <vscale x 4 x i32> @vsra_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {646; CHECK-LABEL: vsra_vx_nxv4i32:647; CHECK: # %bb.0:648; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma649; CHECK-NEXT: vsra.vx v8, v8, a0650; CHECK-NEXT: ret651 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0652 %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer653 %vc = ashr <vscale x 4 x i32> %va, %splat654 ret <vscale x 4 x i32> %vc655}656 657define <vscale x 4 x i32> @vsra_vi_nxv4i32_0(<vscale x 4 x i32> %va) {658; CHECK-LABEL: vsra_vi_nxv4i32_0:659; CHECK: # %bb.0:660; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma661; CHECK-NEXT: vsra.vi v8, v8, 31662; CHECK-NEXT: ret663 %vc = ashr <vscale x 4 x i32> %va, splat (i32 31)664 ret <vscale x 4 x i32> %vc665}666 667define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {668; CHECK-LABEL: vsra_vv_nxv8i32:669; CHECK: # %bb.0:670; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma671; CHECK-NEXT: vsra.vv v8, v8, v12672; CHECK-NEXT: ret673 %vc = ashr <vscale x 8 x i32> %va, %vb674 ret <vscale x 8 x i32> %vc675}676 677define <vscale x 8 x i32> @vsra_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {678; CHECK-LABEL: vsra_vx_nxv8i32:679; CHECK: # %bb.0:680; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma681; CHECK-NEXT: vsra.vx v8, v8, a0682; CHECK-NEXT: ret683 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0684 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer685 %vc = ashr <vscale x 8 x i32> %va, %splat686 ret <vscale x 8 x i32> %vc687}688 689define <vscale x 8 x i32> @vsra_vi_nxv8i32_0(<vscale x 8 x i32> %va) {690; CHECK-LABEL: vsra_vi_nxv8i32_0:691; CHECK: # %bb.0:692; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma693; CHECK-NEXT: vsra.vi v8, v8, 31694; CHECK-NEXT: ret695 %vc = ashr <vscale x 8 x i32> %va, splat (i32 31)696 ret <vscale x 8 x i32> %vc697}698 699define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb) {700; CHECK-LABEL: vsra_vv_nxv16i32:701; CHECK: # %bb.0:702; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma703; CHECK-NEXT: vsra.vv v8, v8, v16704; CHECK-NEXT: ret705 %vc = ashr <vscale x 16 x i32> %va, %vb706 ret <vscale x 16 x i32> %vc707}708 709define <vscale x 16 x i32> @vsra_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {710; CHECK-LABEL: vsra_vx_nxv16i32:711; CHECK: # %bb.0:712; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma713; CHECK-NEXT: vsra.vx v8, v8, a0714; CHECK-NEXT: ret715 %head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0716 %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer717 %vc = ashr <vscale x 16 x i32> %va, %splat718 ret <vscale x 16 x i32> %vc719}720 721define <vscale x 16 x i32> @vsra_vi_nxv16i32_0(<vscale x 16 x i32> %va) {722; CHECK-LABEL: vsra_vi_nxv16i32_0:723; CHECK: # %bb.0:724; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma725; CHECK-NEXT: vsra.vi v8, v8, 31726; CHECK-NEXT: ret727 %vc = ashr <vscale x 16 x i32> %va, splat (i32 31)728 ret <vscale x 16 x i32> %vc729}730 731define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb) {732; CHECK-LABEL: vsra_vv_nxv1i64:733; CHECK: # %bb.0:734; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma735; CHECK-NEXT: vsra.vv v8, v8, v9736; CHECK-NEXT: ret737 %vc = ashr <vscale x 1 x i64> %va, %vb738 ret <vscale x 1 x i64> %vc739}740 741define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {742; CHECK-LABEL: vsra_vx_nxv1i64:743; CHECK: # %bb.0:744; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma745; CHECK-NEXT: vsra.vx v8, v8, a0746; CHECK-NEXT: ret747 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0748 %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer749 %vc = ashr <vscale x 1 x i64> %va, %splat750 ret <vscale x 1 x i64> %vc751}752 753define <vscale x 1 x i64> @vsra_vi_nxv1i64_0(<vscale x 1 x i64> %va) {754; CHECK-LABEL: vsra_vi_nxv1i64_0:755; CHECK: # %bb.0:756; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma757; CHECK-NEXT: vsra.vi v8, v8, 31758; CHECK-NEXT: ret759 %vc = ashr <vscale x 1 x i64> %va, splat (i64 31)760 ret <vscale x 1 x i64> %vc761}762 763define <vscale x 1 x i64> @vsra_vi_nxv1i64_1(<vscale x 1 x i64> %va) {764; CHECK-LABEL: vsra_vi_nxv1i64_1:765; CHECK: # %bb.0:766; CHECK-NEXT: li a0, 32767; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma768; CHECK-NEXT: vsra.vx v8, v8, a0769; CHECK-NEXT: ret770 %vc = ashr <vscale x 1 x i64> %va, splat (i64 32)771 ret <vscale x 1 x i64> %vc772}773 774define <vscale x 2 x i64> @vsra_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb) {775; CHECK-LABEL: vsra_vv_nxv2i64:776; CHECK: # %bb.0:777; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma778; CHECK-NEXT: vsra.vv v8, v8, v10779; CHECK-NEXT: ret780 %vc = ashr <vscale x 2 x i64> %va, %vb781 ret <vscale x 2 x i64> %vc782}783 784define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {785; CHECK-LABEL: vsra_vx_nxv2i64:786; CHECK: # %bb.0:787; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma788; CHECK-NEXT: vsra.vx v8, v8, a0789; CHECK-NEXT: ret790 %head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0791 %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer792 %vc = ashr <vscale x 2 x i64> %va, %splat793 ret <vscale x 2 x i64> %vc794}795 796define <vscale x 2 x i64> @vsra_vi_nxv2i64_0(<vscale x 2 x i64> %va) {797; CHECK-LABEL: vsra_vi_nxv2i64_0:798; CHECK: # %bb.0:799; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma800; CHECK-NEXT: vsra.vi v8, v8, 31801; CHECK-NEXT: ret802 %vc = ashr <vscale x 2 x i64> %va, splat (i64 31)803 ret <vscale x 2 x i64> %vc804}805 806define <vscale x 2 x i64> @vsra_vi_nxv2i64_1(<vscale x 2 x i64> %va) {807; CHECK-LABEL: vsra_vi_nxv2i64_1:808; CHECK: # %bb.0:809; CHECK-NEXT: li a0, 32810; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma811; CHECK-NEXT: vsra.vx v8, v8, a0812; CHECK-NEXT: ret813 %vc = ashr <vscale x 2 x i64> %va, splat (i64 32)814 ret <vscale x 2 x i64> %vc815}816 817define <vscale x 4 x i64> @vsra_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb) {818; CHECK-LABEL: vsra_vv_nxv4i64:819; CHECK: # %bb.0:820; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma821; CHECK-NEXT: vsra.vv v8, v8, v12822; CHECK-NEXT: ret823 %vc = ashr <vscale x 4 x i64> %va, %vb824 ret <vscale x 4 x i64> %vc825}826 827define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {828; CHECK-LABEL: vsra_vx_nxv4i64:829; CHECK: # %bb.0:830; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma831; CHECK-NEXT: vsra.vx v8, v8, a0832; CHECK-NEXT: ret833 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0834 %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer835 %vc = ashr <vscale x 4 x i64> %va, %splat836 ret <vscale x 4 x i64> %vc837}838 839define <vscale x 4 x i64> @vsra_vi_nxv4i64_0(<vscale x 4 x i64> %va) {840; CHECK-LABEL: vsra_vi_nxv4i64_0:841; CHECK: # %bb.0:842; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma843; CHECK-NEXT: vsra.vi v8, v8, 31844; CHECK-NEXT: ret845 %vc = ashr <vscale x 4 x i64> %va, splat (i64 31)846 ret <vscale x 4 x i64> %vc847}848 849define <vscale x 4 x i64> @vsra_vi_nxv4i64_1(<vscale x 4 x i64> %va) {850; CHECK-LABEL: vsra_vi_nxv4i64_1:851; CHECK: # %bb.0:852; CHECK-NEXT: li a0, 32853; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma854; CHECK-NEXT: vsra.vx v8, v8, a0855; CHECK-NEXT: ret856 %vc = ashr <vscale x 4 x i64> %va, splat (i64 32)857 ret <vscale x 4 x i64> %vc858}859 860define <vscale x 8 x i64> @vsra_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {861; CHECK-LABEL: vsra_vv_nxv8i64:862; CHECK: # %bb.0:863; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma864; CHECK-NEXT: vsra.vv v8, v8, v16865; CHECK-NEXT: ret866 %vc = ashr <vscale x 8 x i64> %va, %vb867 ret <vscale x 8 x i64> %vc868}869 870define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {871; CHECK-LABEL: vsra_vx_nxv8i64:872; CHECK: # %bb.0:873; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma874; CHECK-NEXT: vsra.vx v8, v8, a0875; CHECK-NEXT: ret876 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0877 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer878 %vc = ashr <vscale x 8 x i64> %va, %splat879 ret <vscale x 8 x i64> %vc880}881 882define <vscale x 8 x i64> @vsra_vi_nxv8i64_0(<vscale x 8 x i64> %va) {883; CHECK-LABEL: vsra_vi_nxv8i64_0:884; CHECK: # %bb.0:885; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma886; CHECK-NEXT: vsra.vi v8, v8, 31887; CHECK-NEXT: ret888 %vc = ashr <vscale x 8 x i64> %va, splat (i64 31)889 ret <vscale x 8 x i64> %vc890}891 892define <vscale x 8 x i64> @vsra_vi_nxv8i64_1(<vscale x 8 x i64> %va) {893; CHECK-LABEL: vsra_vi_nxv8i64_1:894; CHECK: # %bb.0:895; CHECK-NEXT: li a0, 32896; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma897; CHECK-NEXT: vsra.vx v8, v8, a0898; CHECK-NEXT: ret899 %vc = ashr <vscale x 8 x i64> %va, splat (i64 32)900 ret <vscale x 8 x i64> %vc901}902 903define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {904; CHECK-LABEL: vsra_vv_mask_nxv4i32:905; CHECK: # %bb.0:906; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu907; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t908; CHECK-NEXT: ret909 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer910 %vc = ashr <vscale x 8 x i32> %va, %vs911 ret <vscale x 8 x i32> %vc912}913 914define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {915; CHECK-LABEL: vsra_vx_mask_nxv8i32:916; CHECK: # %bb.0:917; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu918; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t919; CHECK-NEXT: ret920 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0921 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer922 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer923 %vc = ashr <vscale x 8 x i32> %va, %vs924 ret <vscale x 8 x i32> %vc925}926 927define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {928; CHECK-LABEL: vsra_vi_mask_nxv8i32:929; CHECK: # %bb.0:930; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu931; CHECK-NEXT: vsra.vi v8, v8, 31, v0.t932; CHECK-NEXT: ret933 %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> splat (i32 31), <vscale x 8 x i32> zeroinitializer934 %vc = ashr <vscale x 8 x i32> %va, %vs935 ret <vscale x 8 x i32> %vc936}937 938; Negative test. We shouldn't look through the vp.trunc as it isn't vlmax like939; the rest of the code.940define <vscale x 1 x i8> @vsra_vv_nxv1i8_sext_zext_mixed_trunc(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 zeroext %evl) {941; CHECK-LABEL: vsra_vv_nxv1i8_sext_zext_mixed_trunc:942; CHECK: # %bb.0:943; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma944; CHECK-NEXT: vsext.vf4 v9, v8945; CHECK-NEXT: vzext.vf4 v10, v8946; CHECK-NEXT: vsra.vv v8, v9, v10947; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma948; CHECK-NEXT: vnsrl.wi v8, v8, 0949; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma950; CHECK-NEXT: vnsrl.wi v8, v8, 0, v0.t951; CHECK-NEXT: ret952 %sexted_va = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>953 %zexted_vb = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>954 %expand = ashr <vscale x 1 x i32> %sexted_va, %zexted_vb955 %vc = trunc <vscale x 1 x i32> %expand to <vscale x 1 x i16>956 %vd = call <vscale x 1 x i8> @llvm.vp.trunc.nxv1i8.nxvi16(<vscale x 1 x i16> %vc, <vscale x 1 x i1> %m, i32 %evl)957 ret <vscale x 1 x i8> %vd958}959