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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \3; RUN: | FileCheck %s --check-prefixes=CHECK,RV324; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \5; RUN: | FileCheck %s --check-prefixes=CHECK,RV646 7define <vscale x 8 x i7> @vsra_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) {8; CHECK-LABEL: vsra_vx_nxv8i7:9; CHECK: # %bb.0:10; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma11; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t12; CHECK-NEXT: vmv.v.x v9, a013; CHECK-NEXT: li a0, 12714; CHECK-NEXT: vsra.vi v8, v8, 1, v0.t15; CHECK-NEXT: vand.vx v9, v9, a0, v0.t16; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t17; CHECK-NEXT: ret18 %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 019 %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer20 %v = call <vscale x 8 x i7> @llvm.vp.ashr.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl)21 ret <vscale x 8 x i7> %v22}23 24define <vscale x 1 x i8> @vsra_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {25; CHECK-LABEL: vsra_vv_nxv1i8:26; CHECK: # %bb.0:27; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma28; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t29; CHECK-NEXT: ret30 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl)31 ret <vscale x 1 x i8> %v32}33 34define <vscale x 1 x i8> @vsra_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) {35; CHECK-LABEL: vsra_vv_nxv1i8_unmasked:36; CHECK: # %bb.0:37; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma38; CHECK-NEXT: vsra.vv v8, v8, v939; CHECK-NEXT: ret40 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)41 ret <vscale x 1 x i8> %v42}43 44define <vscale x 1 x i8> @vsra_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {45; CHECK-LABEL: vsra_vx_nxv1i8:46; CHECK: # %bb.0:47; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma48; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t49; CHECK-NEXT: ret50 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 051 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer52 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl)53 ret <vscale x 1 x i8> %v54}55 56define <vscale x 1 x i8> @vsra_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) {57; CHECK-LABEL: vsra_vx_nxv1i8_unmasked:58; CHECK: # %bb.0:59; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma60; CHECK-NEXT: vsra.vx v8, v8, a061; CHECK-NEXT: ret62 %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 063 %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer64 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)65 ret <vscale x 1 x i8> %v66}67 68define <vscale x 1 x i8> @vsra_vi_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {69; CHECK-LABEL: vsra_vi_nxv1i8:70; CHECK: # %bb.0:71; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma72; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t73; CHECK-NEXT: ret74 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 5), <vscale x 1 x i1> %m, i32 %evl)75 ret <vscale x 1 x i8> %v76}77 78define <vscale x 1 x i8> @vsra_vi_nxv1i8_unmasked(<vscale x 1 x i8> %va, i32 zeroext %evl) {79; CHECK-LABEL: vsra_vi_nxv1i8_unmasked:80; CHECK: # %bb.0:81; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma82; CHECK-NEXT: vsra.vi v8, v8, 583; CHECK-NEXT: ret84 %v = call <vscale x 1 x i8> @llvm.vp.ashr.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> splat (i8 5), <vscale x 1 x i1> splat (i1 true), i32 %evl)85 ret <vscale x 1 x i8> %v86}87 88define <vscale x 2 x i8> @vsra_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {89; CHECK-LABEL: vsra_vv_nxv2i8:90; CHECK: # %bb.0:91; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma92; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t93; CHECK-NEXT: ret94 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl)95 ret <vscale x 2 x i8> %v96}97 98define <vscale x 2 x i8> @vsra_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) {99; CHECK-LABEL: vsra_vv_nxv2i8_unmasked:100; CHECK: # %bb.0:101; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma102; CHECK-NEXT: vsra.vv v8, v8, v9103; CHECK-NEXT: ret104 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)105 ret <vscale x 2 x i8> %v106}107 108define <vscale x 2 x i8> @vsra_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {109; CHECK-LABEL: vsra_vx_nxv2i8:110; CHECK: # %bb.0:111; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma112; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t113; CHECK-NEXT: ret114 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0115 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer116 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl)117 ret <vscale x 2 x i8> %v118}119 120define <vscale x 2 x i8> @vsra_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) {121; CHECK-LABEL: vsra_vx_nxv2i8_unmasked:122; CHECK: # %bb.0:123; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma124; CHECK-NEXT: vsra.vx v8, v8, a0125; CHECK-NEXT: ret126 %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0127 %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer128 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)129 ret <vscale x 2 x i8> %v130}131 132define <vscale x 2 x i8> @vsra_vi_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {133; CHECK-LABEL: vsra_vi_nxv2i8:134; CHECK: # %bb.0:135; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma136; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t137; CHECK-NEXT: ret138 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 5), <vscale x 2 x i1> %m, i32 %evl)139 ret <vscale x 2 x i8> %v140}141 142define <vscale x 2 x i8> @vsra_vi_nxv2i8_unmasked(<vscale x 2 x i8> %va, i32 zeroext %evl) {143; CHECK-LABEL: vsra_vi_nxv2i8_unmasked:144; CHECK: # %bb.0:145; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma146; CHECK-NEXT: vsra.vi v8, v8, 5147; CHECK-NEXT: ret148 %v = call <vscale x 2 x i8> @llvm.vp.ashr.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> splat (i8 5), <vscale x 2 x i1> splat (i1 true), i32 %evl)149 ret <vscale x 2 x i8> %v150}151 152define <vscale x 4 x i8> @vsra_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {153; CHECK-LABEL: vsra_vv_nxv4i8:154; CHECK: # %bb.0:155; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma156; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t157; CHECK-NEXT: ret158 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl)159 ret <vscale x 4 x i8> %v160}161 162define <vscale x 4 x i8> @vsra_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) {163; CHECK-LABEL: vsra_vv_nxv4i8_unmasked:164; CHECK: # %bb.0:165; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma166; CHECK-NEXT: vsra.vv v8, v8, v9167; CHECK-NEXT: ret168 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)169 ret <vscale x 4 x i8> %v170}171 172define <vscale x 4 x i8> @vsra_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {173; CHECK-LABEL: vsra_vx_nxv4i8:174; CHECK: # %bb.0:175; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma176; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t177; CHECK-NEXT: ret178 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0179 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer180 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl)181 ret <vscale x 4 x i8> %v182}183 184define <vscale x 4 x i8> @vsra_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) {185; CHECK-LABEL: vsra_vx_nxv4i8_unmasked:186; CHECK: # %bb.0:187; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma188; CHECK-NEXT: vsra.vx v8, v8, a0189; CHECK-NEXT: ret190 %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0191 %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer192 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)193 ret <vscale x 4 x i8> %v194}195 196define <vscale x 4 x i8> @vsra_vi_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {197; CHECK-LABEL: vsra_vi_nxv4i8:198; CHECK: # %bb.0:199; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma200; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t201; CHECK-NEXT: ret202 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 5), <vscale x 4 x i1> %m, i32 %evl)203 ret <vscale x 4 x i8> %v204}205 206define <vscale x 4 x i8> @vsra_vi_nxv4i8_unmasked(<vscale x 4 x i8> %va, i32 zeroext %evl) {207; CHECK-LABEL: vsra_vi_nxv4i8_unmasked:208; CHECK: # %bb.0:209; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma210; CHECK-NEXT: vsra.vi v8, v8, 5211; CHECK-NEXT: ret212 %v = call <vscale x 4 x i8> @llvm.vp.ashr.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> splat (i8 5), <vscale x 4 x i1> splat (i1 true), i32 %evl)213 ret <vscale x 4 x i8> %v214}215 216define <vscale x 8 x i8> @vsra_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {217; CHECK-LABEL: vsra_vv_nxv8i8:218; CHECK: # %bb.0:219; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma220; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t221; CHECK-NEXT: ret222 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl)223 ret <vscale x 8 x i8> %v224}225 226define <vscale x 8 x i8> @vsra_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) {227; CHECK-LABEL: vsra_vv_nxv8i8_unmasked:228; CHECK: # %bb.0:229; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma230; CHECK-NEXT: vsra.vv v8, v8, v9231; CHECK-NEXT: ret232 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)233 ret <vscale x 8 x i8> %v234}235 236define <vscale x 8 x i8> @vsra_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {237; CHECK-LABEL: vsra_vx_nxv8i8:238; CHECK: # %bb.0:239; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma240; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t241; CHECK-NEXT: ret242 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0243 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer244 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl)245 ret <vscale x 8 x i8> %v246}247 248define <vscale x 8 x i8> @vsra_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) {249; CHECK-LABEL: vsra_vx_nxv8i8_unmasked:250; CHECK: # %bb.0:251; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma252; CHECK-NEXT: vsra.vx v8, v8, a0253; CHECK-NEXT: ret254 %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0255 %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer256 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)257 ret <vscale x 8 x i8> %v258}259 260define <vscale x 8 x i8> @vsra_vi_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {261; CHECK-LABEL: vsra_vi_nxv8i8:262; CHECK: # %bb.0:263; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma264; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t265; CHECK-NEXT: ret266 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 5), <vscale x 8 x i1> %m, i32 %evl)267 ret <vscale x 8 x i8> %v268}269 270define <vscale x 8 x i8> @vsra_vi_nxv8i8_unmasked(<vscale x 8 x i8> %va, i32 zeroext %evl) {271; CHECK-LABEL: vsra_vi_nxv8i8_unmasked:272; CHECK: # %bb.0:273; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma274; CHECK-NEXT: vsra.vi v8, v8, 5275; CHECK-NEXT: ret276 %v = call <vscale x 8 x i8> @llvm.vp.ashr.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> splat (i8 5), <vscale x 8 x i1> splat (i1 true), i32 %evl)277 ret <vscale x 8 x i8> %v278}279 280define <vscale x 16 x i8> @vsra_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {281; CHECK-LABEL: vsra_vv_nxv16i8:282; CHECK: # %bb.0:283; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma284; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t285; CHECK-NEXT: ret286 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl)287 ret <vscale x 16 x i8> %v288}289 290define <vscale x 16 x i8> @vsra_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) {291; CHECK-LABEL: vsra_vv_nxv16i8_unmasked:292; CHECK: # %bb.0:293; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma294; CHECK-NEXT: vsra.vv v8, v8, v10295; CHECK-NEXT: ret296 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)297 ret <vscale x 16 x i8> %v298}299 300define <vscale x 16 x i8> @vsra_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {301; CHECK-LABEL: vsra_vx_nxv16i8:302; CHECK: # %bb.0:303; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma304; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t305; CHECK-NEXT: ret306 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0307 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer308 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl)309 ret <vscale x 16 x i8> %v310}311 312define <vscale x 16 x i8> @vsra_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) {313; CHECK-LABEL: vsra_vx_nxv16i8_unmasked:314; CHECK: # %bb.0:315; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma316; CHECK-NEXT: vsra.vx v8, v8, a0317; CHECK-NEXT: ret318 %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0319 %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer320 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)321 ret <vscale x 16 x i8> %v322}323 324define <vscale x 16 x i8> @vsra_vi_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {325; CHECK-LABEL: vsra_vi_nxv16i8:326; CHECK: # %bb.0:327; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma328; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t329; CHECK-NEXT: ret330 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 5), <vscale x 16 x i1> %m, i32 %evl)331 ret <vscale x 16 x i8> %v332}333 334define <vscale x 16 x i8> @vsra_vi_nxv16i8_unmasked(<vscale x 16 x i8> %va, i32 zeroext %evl) {335; CHECK-LABEL: vsra_vi_nxv16i8_unmasked:336; CHECK: # %bb.0:337; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma338; CHECK-NEXT: vsra.vi v8, v8, 5339; CHECK-NEXT: ret340 %v = call <vscale x 16 x i8> @llvm.vp.ashr.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> splat (i8 5), <vscale x 16 x i1> splat (i1 true), i32 %evl)341 ret <vscale x 16 x i8> %v342}343 344define <vscale x 32 x i8> @vsra_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {345; CHECK-LABEL: vsra_vv_nxv32i8:346; CHECK: # %bb.0:347; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma348; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t349; CHECK-NEXT: ret350 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl)351 ret <vscale x 32 x i8> %v352}353 354define <vscale x 32 x i8> @vsra_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) {355; CHECK-LABEL: vsra_vv_nxv32i8_unmasked:356; CHECK: # %bb.0:357; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma358; CHECK-NEXT: vsra.vv v8, v8, v12359; CHECK-NEXT: ret360 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)361 ret <vscale x 32 x i8> %v362}363 364define <vscale x 32 x i8> @vsra_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {365; CHECK-LABEL: vsra_vx_nxv32i8:366; CHECK: # %bb.0:367; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma368; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t369; CHECK-NEXT: ret370 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0371 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer372 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl)373 ret <vscale x 32 x i8> %v374}375 376define <vscale x 32 x i8> @vsra_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) {377; CHECK-LABEL: vsra_vx_nxv32i8_unmasked:378; CHECK: # %bb.0:379; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma380; CHECK-NEXT: vsra.vx v8, v8, a0381; CHECK-NEXT: ret382 %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0383 %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer384 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)385 ret <vscale x 32 x i8> %v386}387 388define <vscale x 32 x i8> @vsra_vi_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {389; CHECK-LABEL: vsra_vi_nxv32i8:390; CHECK: # %bb.0:391; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma392; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t393; CHECK-NEXT: ret394 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 5), <vscale x 32 x i1> %m, i32 %evl)395 ret <vscale x 32 x i8> %v396}397 398define <vscale x 32 x i8> @vsra_vi_nxv32i8_unmasked(<vscale x 32 x i8> %va, i32 zeroext %evl) {399; CHECK-LABEL: vsra_vi_nxv32i8_unmasked:400; CHECK: # %bb.0:401; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma402; CHECK-NEXT: vsra.vi v8, v8, 5403; CHECK-NEXT: ret404 %v = call <vscale x 32 x i8> @llvm.vp.ashr.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> splat (i8 5), <vscale x 32 x i1> splat (i1 true), i32 %evl)405 ret <vscale x 32 x i8> %v406}407 408define <vscale x 64 x i8> @vsra_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {409; CHECK-LABEL: vsra_vv_nxv64i8:410; CHECK: # %bb.0:411; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma412; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t413; CHECK-NEXT: ret414 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl)415 ret <vscale x 64 x i8> %v416}417 418define <vscale x 64 x i8> @vsra_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) {419; CHECK-LABEL: vsra_vv_nxv64i8_unmasked:420; CHECK: # %bb.0:421; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma422; CHECK-NEXT: vsra.vv v8, v8, v16423; CHECK-NEXT: ret424 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> splat (i1 true), i32 %evl)425 ret <vscale x 64 x i8> %v426}427 428define <vscale x 64 x i8> @vsra_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) {429; CHECK-LABEL: vsra_vx_nxv64i8:430; CHECK: # %bb.0:431; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma432; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t433; CHECK-NEXT: ret434 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0435 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer436 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl)437 ret <vscale x 64 x i8> %v438}439 440define <vscale x 64 x i8> @vsra_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) {441; CHECK-LABEL: vsra_vx_nxv64i8_unmasked:442; CHECK: # %bb.0:443; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma444; CHECK-NEXT: vsra.vx v8, v8, a0445; CHECK-NEXT: ret446 %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0447 %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer448 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> splat (i1 true), i32 %evl)449 ret <vscale x 64 x i8> %v450}451 452define <vscale x 64 x i8> @vsra_vi_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i1> %m, i32 zeroext %evl) {453; CHECK-LABEL: vsra_vi_nxv64i8:454; CHECK: # %bb.0:455; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma456; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t457; CHECK-NEXT: ret458 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 5), <vscale x 64 x i1> %m, i32 %evl)459 ret <vscale x 64 x i8> %v460}461 462define <vscale x 64 x i8> @vsra_vi_nxv64i8_unmasked(<vscale x 64 x i8> %va, i32 zeroext %evl) {463; CHECK-LABEL: vsra_vi_nxv64i8_unmasked:464; CHECK: # %bb.0:465; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma466; CHECK-NEXT: vsra.vi v8, v8, 5467; CHECK-NEXT: ret468 %v = call <vscale x 64 x i8> @llvm.vp.ashr.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> splat (i8 5), <vscale x 64 x i1> splat (i1 true), i32 %evl)469 ret <vscale x 64 x i8> %v470}471 472define <vscale x 1 x i16> @vsra_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {473; CHECK-LABEL: vsra_vv_nxv1i16:474; CHECK: # %bb.0:475; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma476; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t477; CHECK-NEXT: ret478 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl)479 ret <vscale x 1 x i16> %v480}481 482define <vscale x 1 x i16> @vsra_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) {483; CHECK-LABEL: vsra_vv_nxv1i16_unmasked:484; CHECK: # %bb.0:485; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma486; CHECK-NEXT: vsra.vv v8, v8, v9487; CHECK-NEXT: ret488 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)489 ret <vscale x 1 x i16> %v490}491 492define <vscale x 1 x i16> @vsra_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {493; CHECK-LABEL: vsra_vx_nxv1i16:494; CHECK: # %bb.0:495; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma496; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t497; CHECK-NEXT: ret498 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0499 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer500 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl)501 ret <vscale x 1 x i16> %v502}503 504define <vscale x 1 x i16> @vsra_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) {505; CHECK-LABEL: vsra_vx_nxv1i16_unmasked:506; CHECK: # %bb.0:507; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma508; CHECK-NEXT: vsra.vx v8, v8, a0509; CHECK-NEXT: ret510 %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0511 %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer512 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)513 ret <vscale x 1 x i16> %v514}515 516define <vscale x 1 x i16> @vsra_vi_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {517; CHECK-LABEL: vsra_vi_nxv1i16:518; CHECK: # %bb.0:519; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma520; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t521; CHECK-NEXT: ret522 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 5), <vscale x 1 x i1> %m, i32 %evl)523 ret <vscale x 1 x i16> %v524}525 526define <vscale x 1 x i16> @vsra_vi_nxv1i16_unmasked(<vscale x 1 x i16> %va, i32 zeroext %evl) {527; CHECK-LABEL: vsra_vi_nxv1i16_unmasked:528; CHECK: # %bb.0:529; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma530; CHECK-NEXT: vsra.vi v8, v8, 5531; CHECK-NEXT: ret532 %v = call <vscale x 1 x i16> @llvm.vp.ashr.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> splat (i16 5), <vscale x 1 x i1> splat (i1 true), i32 %evl)533 ret <vscale x 1 x i16> %v534}535 536define <vscale x 2 x i16> @vsra_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {537; CHECK-LABEL: vsra_vv_nxv2i16:538; CHECK: # %bb.0:539; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma540; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t541; CHECK-NEXT: ret542 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl)543 ret <vscale x 2 x i16> %v544}545 546define <vscale x 2 x i16> @vsra_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) {547; CHECK-LABEL: vsra_vv_nxv2i16_unmasked:548; CHECK: # %bb.0:549; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma550; CHECK-NEXT: vsra.vv v8, v8, v9551; CHECK-NEXT: ret552 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)553 ret <vscale x 2 x i16> %v554}555 556define <vscale x 2 x i16> @vsra_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {557; CHECK-LABEL: vsra_vx_nxv2i16:558; CHECK: # %bb.0:559; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma560; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t561; CHECK-NEXT: ret562 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0563 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer564 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl)565 ret <vscale x 2 x i16> %v566}567 568define <vscale x 2 x i16> @vsra_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) {569; CHECK-LABEL: vsra_vx_nxv2i16_unmasked:570; CHECK: # %bb.0:571; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma572; CHECK-NEXT: vsra.vx v8, v8, a0573; CHECK-NEXT: ret574 %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0575 %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer576 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)577 ret <vscale x 2 x i16> %v578}579 580define <vscale x 2 x i16> @vsra_vi_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {581; CHECK-LABEL: vsra_vi_nxv2i16:582; CHECK: # %bb.0:583; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma584; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t585; CHECK-NEXT: ret586 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 5), <vscale x 2 x i1> %m, i32 %evl)587 ret <vscale x 2 x i16> %v588}589 590define <vscale x 2 x i16> @vsra_vi_nxv2i16_unmasked(<vscale x 2 x i16> %va, i32 zeroext %evl) {591; CHECK-LABEL: vsra_vi_nxv2i16_unmasked:592; CHECK: # %bb.0:593; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma594; CHECK-NEXT: vsra.vi v8, v8, 5595; CHECK-NEXT: ret596 %v = call <vscale x 2 x i16> @llvm.vp.ashr.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> splat (i16 5), <vscale x 2 x i1> splat (i1 true), i32 %evl)597 ret <vscale x 2 x i16> %v598}599 600define <vscale x 4 x i16> @vsra_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {601; CHECK-LABEL: vsra_vv_nxv4i16:602; CHECK: # %bb.0:603; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma604; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t605; CHECK-NEXT: ret606 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl)607 ret <vscale x 4 x i16> %v608}609 610define <vscale x 4 x i16> @vsra_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) {611; CHECK-LABEL: vsra_vv_nxv4i16_unmasked:612; CHECK: # %bb.0:613; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma614; CHECK-NEXT: vsra.vv v8, v8, v9615; CHECK-NEXT: ret616 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)617 ret <vscale x 4 x i16> %v618}619 620define <vscale x 4 x i16> @vsra_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {621; CHECK-LABEL: vsra_vx_nxv4i16:622; CHECK: # %bb.0:623; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma624; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t625; CHECK-NEXT: ret626 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0627 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer628 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl)629 ret <vscale x 4 x i16> %v630}631 632define <vscale x 4 x i16> @vsra_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) {633; CHECK-LABEL: vsra_vx_nxv4i16_unmasked:634; CHECK: # %bb.0:635; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma636; CHECK-NEXT: vsra.vx v8, v8, a0637; CHECK-NEXT: ret638 %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0639 %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer640 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)641 ret <vscale x 4 x i16> %v642}643 644define <vscale x 4 x i16> @vsra_vi_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {645; CHECK-LABEL: vsra_vi_nxv4i16:646; CHECK: # %bb.0:647; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma648; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t649; CHECK-NEXT: ret650 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 5), <vscale x 4 x i1> %m, i32 %evl)651 ret <vscale x 4 x i16> %v652}653 654define <vscale x 4 x i16> @vsra_vi_nxv4i16_unmasked(<vscale x 4 x i16> %va, i32 zeroext %evl) {655; CHECK-LABEL: vsra_vi_nxv4i16_unmasked:656; CHECK: # %bb.0:657; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma658; CHECK-NEXT: vsra.vi v8, v8, 5659; CHECK-NEXT: ret660 %v = call <vscale x 4 x i16> @llvm.vp.ashr.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> splat (i16 5), <vscale x 4 x i1> splat (i1 true), i32 %evl)661 ret <vscale x 4 x i16> %v662}663 664define <vscale x 8 x i16> @vsra_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {665; CHECK-LABEL: vsra_vv_nxv8i16:666; CHECK: # %bb.0:667; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma668; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t669; CHECK-NEXT: ret670 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl)671 ret <vscale x 8 x i16> %v672}673 674define <vscale x 8 x i16> @vsra_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) {675; CHECK-LABEL: vsra_vv_nxv8i16_unmasked:676; CHECK: # %bb.0:677; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma678; CHECK-NEXT: vsra.vv v8, v8, v10679; CHECK-NEXT: ret680 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)681 ret <vscale x 8 x i16> %v682}683 684define <vscale x 8 x i16> @vsra_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {685; CHECK-LABEL: vsra_vx_nxv8i16:686; CHECK: # %bb.0:687; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma688; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t689; CHECK-NEXT: ret690 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0691 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer692 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl)693 ret <vscale x 8 x i16> %v694}695 696define <vscale x 8 x i16> @vsra_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) {697; CHECK-LABEL: vsra_vx_nxv8i16_unmasked:698; CHECK: # %bb.0:699; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma700; CHECK-NEXT: vsra.vx v8, v8, a0701; CHECK-NEXT: ret702 %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0703 %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer704 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)705 ret <vscale x 8 x i16> %v706}707 708define <vscale x 8 x i16> @vsra_vi_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {709; CHECK-LABEL: vsra_vi_nxv8i16:710; CHECK: # %bb.0:711; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma712; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t713; CHECK-NEXT: ret714 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 5), <vscale x 8 x i1> %m, i32 %evl)715 ret <vscale x 8 x i16> %v716}717 718define <vscale x 8 x i16> @vsra_vi_nxv8i16_unmasked(<vscale x 8 x i16> %va, i32 zeroext %evl) {719; CHECK-LABEL: vsra_vi_nxv8i16_unmasked:720; CHECK: # %bb.0:721; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma722; CHECK-NEXT: vsra.vi v8, v8, 5723; CHECK-NEXT: ret724 %v = call <vscale x 8 x i16> @llvm.vp.ashr.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> splat (i16 5), <vscale x 8 x i1> splat (i1 true), i32 %evl)725 ret <vscale x 8 x i16> %v726}727 728define <vscale x 16 x i16> @vsra_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {729; CHECK-LABEL: vsra_vv_nxv16i16:730; CHECK: # %bb.0:731; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma732; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t733; CHECK-NEXT: ret734 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl)735 ret <vscale x 16 x i16> %v736}737 738define <vscale x 16 x i16> @vsra_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) {739; CHECK-LABEL: vsra_vv_nxv16i16_unmasked:740; CHECK: # %bb.0:741; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma742; CHECK-NEXT: vsra.vv v8, v8, v12743; CHECK-NEXT: ret744 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)745 ret <vscale x 16 x i16> %v746}747 748define <vscale x 16 x i16> @vsra_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {749; CHECK-LABEL: vsra_vx_nxv16i16:750; CHECK: # %bb.0:751; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma752; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t753; CHECK-NEXT: ret754 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0755 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer756 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl)757 ret <vscale x 16 x i16> %v758}759 760define <vscale x 16 x i16> @vsra_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) {761; CHECK-LABEL: vsra_vx_nxv16i16_unmasked:762; CHECK: # %bb.0:763; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma764; CHECK-NEXT: vsra.vx v8, v8, a0765; CHECK-NEXT: ret766 %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0767 %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer768 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)769 ret <vscale x 16 x i16> %v770}771 772define <vscale x 16 x i16> @vsra_vi_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {773; CHECK-LABEL: vsra_vi_nxv16i16:774; CHECK: # %bb.0:775; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma776; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t777; CHECK-NEXT: ret778 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 5), <vscale x 16 x i1> %m, i32 %evl)779 ret <vscale x 16 x i16> %v780}781 782define <vscale x 16 x i16> @vsra_vi_nxv16i16_unmasked(<vscale x 16 x i16> %va, i32 zeroext %evl) {783; CHECK-LABEL: vsra_vi_nxv16i16_unmasked:784; CHECK: # %bb.0:785; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma786; CHECK-NEXT: vsra.vi v8, v8, 5787; CHECK-NEXT: ret788 %v = call <vscale x 16 x i16> @llvm.vp.ashr.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> splat (i16 5), <vscale x 16 x i1> splat (i1 true), i32 %evl)789 ret <vscale x 16 x i16> %v790}791 792define <vscale x 32 x i16> @vsra_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {793; CHECK-LABEL: vsra_vv_nxv32i16:794; CHECK: # %bb.0:795; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma796; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t797; CHECK-NEXT: ret798 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl)799 ret <vscale x 32 x i16> %v800}801 802define <vscale x 32 x i16> @vsra_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) {803; CHECK-LABEL: vsra_vv_nxv32i16_unmasked:804; CHECK: # %bb.0:805; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma806; CHECK-NEXT: vsra.vv v8, v8, v16807; CHECK-NEXT: ret808 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> splat (i1 true), i32 %evl)809 ret <vscale x 32 x i16> %v810}811 812define <vscale x 32 x i16> @vsra_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {813; CHECK-LABEL: vsra_vx_nxv32i16:814; CHECK: # %bb.0:815; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma816; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t817; CHECK-NEXT: ret818 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0819 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer820 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl)821 ret <vscale x 32 x i16> %v822}823 824define <vscale x 32 x i16> @vsra_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) {825; CHECK-LABEL: vsra_vx_nxv32i16_unmasked:826; CHECK: # %bb.0:827; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma828; CHECK-NEXT: vsra.vx v8, v8, a0829; CHECK-NEXT: ret830 %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0831 %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer832 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> splat (i1 true), i32 %evl)833 ret <vscale x 32 x i16> %v834}835 836define <vscale x 32 x i16> @vsra_vi_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {837; CHECK-LABEL: vsra_vi_nxv32i16:838; CHECK: # %bb.0:839; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma840; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t841; CHECK-NEXT: ret842 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 5), <vscale x 32 x i1> %m, i32 %evl)843 ret <vscale x 32 x i16> %v844}845 846define <vscale x 32 x i16> @vsra_vi_nxv32i16_unmasked(<vscale x 32 x i16> %va, i32 zeroext %evl) {847; CHECK-LABEL: vsra_vi_nxv32i16_unmasked:848; CHECK: # %bb.0:849; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma850; CHECK-NEXT: vsra.vi v8, v8, 5851; CHECK-NEXT: ret852 %v = call <vscale x 32 x i16> @llvm.vp.ashr.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> splat (i16 5), <vscale x 32 x i1> splat (i1 true), i32 %evl)853 ret <vscale x 32 x i16> %v854}855 856define <vscale x 1 x i32> @vsra_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {857; CHECK-LABEL: vsra_vv_nxv1i32:858; CHECK: # %bb.0:859; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma860; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t861; CHECK-NEXT: ret862 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl)863 ret <vscale x 1 x i32> %v864}865 866define <vscale x 1 x i32> @vsra_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) {867; CHECK-LABEL: vsra_vv_nxv1i32_unmasked:868; CHECK: # %bb.0:869; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma870; CHECK-NEXT: vsra.vv v8, v8, v9871; CHECK-NEXT: ret872 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)873 ret <vscale x 1 x i32> %v874}875 876define <vscale x 1 x i32> @vsra_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {877; CHECK-LABEL: vsra_vx_nxv1i32:878; CHECK: # %bb.0:879; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma880; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t881; CHECK-NEXT: ret882 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0883 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer884 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl)885 ret <vscale x 1 x i32> %v886}887 888define <vscale x 1 x i32> @vsra_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) {889; CHECK-LABEL: vsra_vx_nxv1i32_unmasked:890; CHECK: # %bb.0:891; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma892; CHECK-NEXT: vsra.vx v8, v8, a0893; CHECK-NEXT: ret894 %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0895 %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer896 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)897 ret <vscale x 1 x i32> %v898}899 900define <vscale x 1 x i32> @vsra_vi_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {901; CHECK-LABEL: vsra_vi_nxv1i32:902; CHECK: # %bb.0:903; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma904; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t905; CHECK-NEXT: ret906 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 5), <vscale x 1 x i1> %m, i32 %evl)907 ret <vscale x 1 x i32> %v908}909 910define <vscale x 1 x i32> @vsra_vi_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 zeroext %evl) {911; CHECK-LABEL: vsra_vi_nxv1i32_unmasked:912; CHECK: # %bb.0:913; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma914; CHECK-NEXT: vsra.vi v8, v8, 5915; CHECK-NEXT: ret916 %v = call <vscale x 1 x i32> @llvm.vp.ashr.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> splat (i32 5), <vscale x 1 x i1> splat (i1 true), i32 %evl)917 ret <vscale x 1 x i32> %v918}919 920define <vscale x 2 x i32> @vsra_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {921; CHECK-LABEL: vsra_vv_nxv2i32:922; CHECK: # %bb.0:923; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma924; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t925; CHECK-NEXT: ret926 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl)927 ret <vscale x 2 x i32> %v928}929 930define <vscale x 2 x i32> @vsra_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) {931; CHECK-LABEL: vsra_vv_nxv2i32_unmasked:932; CHECK: # %bb.0:933; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma934; CHECK-NEXT: vsra.vv v8, v8, v9935; CHECK-NEXT: ret936 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)937 ret <vscale x 2 x i32> %v938}939 940define <vscale x 2 x i32> @vsra_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {941; CHECK-LABEL: vsra_vx_nxv2i32:942; CHECK: # %bb.0:943; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma944; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t945; CHECK-NEXT: ret946 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0947 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer948 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl)949 ret <vscale x 2 x i32> %v950}951 952define <vscale x 2 x i32> @vsra_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) {953; CHECK-LABEL: vsra_vx_nxv2i32_unmasked:954; CHECK: # %bb.0:955; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma956; CHECK-NEXT: vsra.vx v8, v8, a0957; CHECK-NEXT: ret958 %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0959 %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer960 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)961 ret <vscale x 2 x i32> %v962}963 964define <vscale x 2 x i32> @vsra_vi_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {965; CHECK-LABEL: vsra_vi_nxv2i32:966; CHECK: # %bb.0:967; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma968; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t969; CHECK-NEXT: ret970 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 5), <vscale x 2 x i1> %m, i32 %evl)971 ret <vscale x 2 x i32> %v972}973 974define <vscale x 2 x i32> @vsra_vi_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 zeroext %evl) {975; CHECK-LABEL: vsra_vi_nxv2i32_unmasked:976; CHECK: # %bb.0:977; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma978; CHECK-NEXT: vsra.vi v8, v8, 5979; CHECK-NEXT: ret980 %v = call <vscale x 2 x i32> @llvm.vp.ashr.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> splat (i32 5), <vscale x 2 x i1> splat (i1 true), i32 %evl)981 ret <vscale x 2 x i32> %v982}983 984define <vscale x 4 x i32> @vsra_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {985; CHECK-LABEL: vsra_vv_nxv4i32:986; CHECK: # %bb.0:987; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma988; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t989; CHECK-NEXT: ret990 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl)991 ret <vscale x 4 x i32> %v992}993 994define <vscale x 4 x i32> @vsra_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) {995; CHECK-LABEL: vsra_vv_nxv4i32_unmasked:996; CHECK: # %bb.0:997; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma998; CHECK-NEXT: vsra.vv v8, v8, v10999; CHECK-NEXT: ret1000 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1001 ret <vscale x 4 x i32> %v1002}1003 1004define <vscale x 4 x i32> @vsra_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1005; CHECK-LABEL: vsra_vx_nxv4i32:1006; CHECK: # %bb.0:1007; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1008; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t1009; CHECK-NEXT: ret1010 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01011 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1012 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl)1013 ret <vscale x 4 x i32> %v1014}1015 1016define <vscale x 4 x i32> @vsra_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) {1017; CHECK-LABEL: vsra_vx_nxv4i32_unmasked:1018; CHECK: # %bb.0:1019; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma1020; CHECK-NEXT: vsra.vx v8, v8, a01021; CHECK-NEXT: ret1022 %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 01023 %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer1024 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1025 ret <vscale x 4 x i32> %v1026}1027 1028define <vscale x 4 x i32> @vsra_vi_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1029; CHECK-LABEL: vsra_vi_nxv4i32:1030; CHECK: # %bb.0:1031; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1032; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1033; CHECK-NEXT: ret1034 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 5), <vscale x 4 x i1> %m, i32 %evl)1035 ret <vscale x 4 x i32> %v1036}1037 1038define <vscale x 4 x i32> @vsra_vi_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 zeroext %evl) {1039; CHECK-LABEL: vsra_vi_nxv4i32_unmasked:1040; CHECK: # %bb.0:1041; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma1042; CHECK-NEXT: vsra.vi v8, v8, 51043; CHECK-NEXT: ret1044 %v = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> splat (i32 5), <vscale x 4 x i1> splat (i1 true), i32 %evl)1045 ret <vscale x 4 x i32> %v1046}1047 1048define <vscale x 8 x i32> @vsra_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1049; CHECK-LABEL: vsra_vv_nxv8i32:1050; CHECK: # %bb.0:1051; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1052; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t1053; CHECK-NEXT: ret1054 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl)1055 ret <vscale x 8 x i32> %v1056}1057 1058define <vscale x 8 x i32> @vsra_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) {1059; CHECK-LABEL: vsra_vv_nxv8i32_unmasked:1060; CHECK: # %bb.0:1061; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1062; CHECK-NEXT: vsra.vv v8, v8, v121063; CHECK-NEXT: ret1064 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1065 ret <vscale x 8 x i32> %v1066}1067 1068define <vscale x 8 x i32> @vsra_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1069; CHECK-LABEL: vsra_vx_nxv8i32:1070; CHECK: # %bb.0:1071; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1072; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t1073; CHECK-NEXT: ret1074 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01075 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1076 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl)1077 ret <vscale x 8 x i32> %v1078}1079 1080define <vscale x 8 x i32> @vsra_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) {1081; CHECK-LABEL: vsra_vx_nxv8i32_unmasked:1082; CHECK: # %bb.0:1083; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma1084; CHECK-NEXT: vsra.vx v8, v8, a01085; CHECK-NEXT: ret1086 %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 01087 %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer1088 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1089 ret <vscale x 8 x i32> %v1090}1091 1092define <vscale x 8 x i32> @vsra_vi_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1093; CHECK-LABEL: vsra_vi_nxv8i32:1094; CHECK: # %bb.0:1095; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1096; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1097; CHECK-NEXT: ret1098 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 5), <vscale x 8 x i1> %m, i32 %evl)1099 ret <vscale x 8 x i32> %v1100}1101 1102define <vscale x 8 x i32> @vsra_vi_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 zeroext %evl) {1103; CHECK-LABEL: vsra_vi_nxv8i32_unmasked:1104; CHECK: # %bb.0:1105; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma1106; CHECK-NEXT: vsra.vi v8, v8, 51107; CHECK-NEXT: ret1108 %v = call <vscale x 8 x i32> @llvm.vp.ashr.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> splat (i32 5), <vscale x 8 x i1> splat (i1 true), i32 %evl)1109 ret <vscale x 8 x i32> %v1110}1111 1112define <vscale x 16 x i32> @vsra_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1113; CHECK-LABEL: vsra_vv_nxv16i32:1114; CHECK: # %bb.0:1115; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1116; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t1117; CHECK-NEXT: ret1118 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl)1119 ret <vscale x 16 x i32> %v1120}1121 1122define <vscale x 16 x i32> @vsra_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) {1123; CHECK-LABEL: vsra_vv_nxv16i32_unmasked:1124; CHECK: # %bb.0:1125; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1126; CHECK-NEXT: vsra.vv v8, v8, v161127; CHECK-NEXT: ret1128 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> splat (i1 true), i32 %evl)1129 ret <vscale x 16 x i32> %v1130}1131 1132define <vscale x 16 x i32> @vsra_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {1133; CHECK-LABEL: vsra_vx_nxv16i32:1134; CHECK: # %bb.0:1135; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1136; CHECK-NEXT: vsra.vx v8, v8, a0, v0.t1137; CHECK-NEXT: ret1138 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01139 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1140 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl)1141 ret <vscale x 16 x i32> %v1142}1143 1144define <vscale x 16 x i32> @vsra_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) {1145; CHECK-LABEL: vsra_vx_nxv16i32_unmasked:1146; CHECK: # %bb.0:1147; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma1148; CHECK-NEXT: vsra.vx v8, v8, a01149; CHECK-NEXT: ret1150 %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 01151 %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer1152 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> splat (i1 true), i32 %evl)1153 ret <vscale x 16 x i32> %v1154}1155 1156define <vscale x 16 x i32> @vsra_vi_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {1157; CHECK-LABEL: vsra_vi_nxv16i32:1158; CHECK: # %bb.0:1159; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1160; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1161; CHECK-NEXT: ret1162 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 5), <vscale x 16 x i1> %m, i32 %evl)1163 ret <vscale x 16 x i32> %v1164}1165 1166define <vscale x 16 x i32> @vsra_vi_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 zeroext %evl) {1167; CHECK-LABEL: vsra_vi_nxv16i32_unmasked:1168; CHECK: # %bb.0:1169; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma1170; CHECK-NEXT: vsra.vi v8, v8, 51171; CHECK-NEXT: ret1172 %v = call <vscale x 16 x i32> @llvm.vp.ashr.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> splat (i32 5), <vscale x 16 x i1> splat (i1 true), i32 %evl)1173 ret <vscale x 16 x i32> %v1174}1175 1176define <vscale x 1 x i64> @vsra_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1177; CHECK-LABEL: vsra_vv_nxv1i64:1178; CHECK: # %bb.0:1179; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1180; CHECK-NEXT: vsra.vv v8, v8, v9, v0.t1181; CHECK-NEXT: ret1182 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl)1183 ret <vscale x 1 x i64> %v1184}1185 1186define <vscale x 1 x i64> @vsra_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) {1187; CHECK-LABEL: vsra_vv_nxv1i64_unmasked:1188; CHECK: # %bb.0:1189; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1190; CHECK-NEXT: vsra.vv v8, v8, v91191; CHECK-NEXT: ret1192 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> splat (i1 true), i32 %evl)1193 ret <vscale x 1 x i64> %v1194}1195 1196define <vscale x 1 x i64> @vsra_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {1197; RV32-LABEL: vsra_vx_nxv1i64:1198; RV32: # %bb.0:1199; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1200; RV32-NEXT: vsra.vx v8, v8, a0, v0.t1201; RV32-NEXT: ret1202;1203; RV64-LABEL: vsra_vx_nxv1i64:1204; RV64: # %bb.0:1205; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1206; RV64-NEXT: vsra.vx v8, v8, a0, v0.t1207; RV64-NEXT: ret1208 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01209 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1210 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl)1211 ret <vscale x 1 x i64> %v1212}1213 1214define <vscale x 1 x i64> @vsra_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) {1215; RV32-LABEL: vsra_vx_nxv1i64_unmasked:1216; RV32: # %bb.0:1217; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma1218; RV32-NEXT: vsra.vx v8, v8, a01219; RV32-NEXT: ret1220;1221; RV64-LABEL: vsra_vx_nxv1i64_unmasked:1222; RV64: # %bb.0:1223; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma1224; RV64-NEXT: vsra.vx v8, v8, a01225; RV64-NEXT: ret1226 %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 01227 %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer1228 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> splat (i1 true), i32 %evl)1229 ret <vscale x 1 x i64> %v1230}1231 1232define <vscale x 1 x i64> @vsra_vi_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {1233; CHECK-LABEL: vsra_vi_nxv1i64:1234; CHECK: # %bb.0:1235; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1236; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1237; CHECK-NEXT: ret1238 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 5), <vscale x 1 x i1> %m, i32 %evl)1239 ret <vscale x 1 x i64> %v1240}1241 1242define <vscale x 1 x i64> @vsra_vi_nxv1i64_unmasked(<vscale x 1 x i64> %va, i32 zeroext %evl) {1243; CHECK-LABEL: vsra_vi_nxv1i64_unmasked:1244; CHECK: # %bb.0:1245; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma1246; CHECK-NEXT: vsra.vi v8, v8, 51247; CHECK-NEXT: ret1248 %v = call <vscale x 1 x i64> @llvm.vp.ashr.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> splat (i64 5), <vscale x 1 x i1> splat (i1 true), i32 %evl)1249 ret <vscale x 1 x i64> %v1250}1251 1252define <vscale x 2 x i64> @vsra_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1253; CHECK-LABEL: vsra_vv_nxv2i64:1254; CHECK: # %bb.0:1255; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1256; CHECK-NEXT: vsra.vv v8, v8, v10, v0.t1257; CHECK-NEXT: ret1258 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl)1259 ret <vscale x 2 x i64> %v1260}1261 1262define <vscale x 2 x i64> @vsra_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) {1263; CHECK-LABEL: vsra_vv_nxv2i64_unmasked:1264; CHECK: # %bb.0:1265; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1266; CHECK-NEXT: vsra.vv v8, v8, v101267; CHECK-NEXT: ret1268 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> splat (i1 true), i32 %evl)1269 ret <vscale x 2 x i64> %v1270}1271 1272define <vscale x 2 x i64> @vsra_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {1273; RV32-LABEL: vsra_vx_nxv2i64:1274; RV32: # %bb.0:1275; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1276; RV32-NEXT: vsra.vx v8, v8, a0, v0.t1277; RV32-NEXT: ret1278;1279; RV64-LABEL: vsra_vx_nxv2i64:1280; RV64: # %bb.0:1281; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1282; RV64-NEXT: vsra.vx v8, v8, a0, v0.t1283; RV64-NEXT: ret1284 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01285 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1286 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl)1287 ret <vscale x 2 x i64> %v1288}1289 1290define <vscale x 2 x i64> @vsra_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) {1291; RV32-LABEL: vsra_vx_nxv2i64_unmasked:1292; RV32: # %bb.0:1293; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma1294; RV32-NEXT: vsra.vx v8, v8, a01295; RV32-NEXT: ret1296;1297; RV64-LABEL: vsra_vx_nxv2i64_unmasked:1298; RV64: # %bb.0:1299; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma1300; RV64-NEXT: vsra.vx v8, v8, a01301; RV64-NEXT: ret1302 %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 01303 %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer1304 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> splat (i1 true), i32 %evl)1305 ret <vscale x 2 x i64> %v1306}1307 1308define <vscale x 2 x i64> @vsra_vi_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {1309; CHECK-LABEL: vsra_vi_nxv2i64:1310; CHECK: # %bb.0:1311; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1312; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1313; CHECK-NEXT: ret1314 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 5), <vscale x 2 x i1> %m, i32 %evl)1315 ret <vscale x 2 x i64> %v1316}1317 1318define <vscale x 2 x i64> @vsra_vi_nxv2i64_unmasked(<vscale x 2 x i64> %va, i32 zeroext %evl) {1319; CHECK-LABEL: vsra_vi_nxv2i64_unmasked:1320; CHECK: # %bb.0:1321; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma1322; CHECK-NEXT: vsra.vi v8, v8, 51323; CHECK-NEXT: ret1324 %v = call <vscale x 2 x i64> @llvm.vp.ashr.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> splat (i64 5), <vscale x 2 x i1> splat (i1 true), i32 %evl)1325 ret <vscale x 2 x i64> %v1326}1327 1328define <vscale x 4 x i64> @vsra_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1329; CHECK-LABEL: vsra_vv_nxv4i64:1330; CHECK: # %bb.0:1331; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1332; CHECK-NEXT: vsra.vv v8, v8, v12, v0.t1333; CHECK-NEXT: ret1334 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl)1335 ret <vscale x 4 x i64> %v1336}1337 1338define <vscale x 4 x i64> @vsra_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) {1339; CHECK-LABEL: vsra_vv_nxv4i64_unmasked:1340; CHECK: # %bb.0:1341; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1342; CHECK-NEXT: vsra.vv v8, v8, v121343; CHECK-NEXT: ret1344 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> splat (i1 true), i32 %evl)1345 ret <vscale x 4 x i64> %v1346}1347 1348define <vscale x 4 x i64> @vsra_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) {1349; RV32-LABEL: vsra_vx_nxv4i64:1350; RV32: # %bb.0:1351; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1352; RV32-NEXT: vsra.vx v8, v8, a0, v0.t1353; RV32-NEXT: ret1354;1355; RV64-LABEL: vsra_vx_nxv4i64:1356; RV64: # %bb.0:1357; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1358; RV64-NEXT: vsra.vx v8, v8, a0, v0.t1359; RV64-NEXT: ret1360 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01361 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1362 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl)1363 ret <vscale x 4 x i64> %v1364}1365 1366define <vscale x 4 x i64> @vsra_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) {1367; RV32-LABEL: vsra_vx_nxv4i64_unmasked:1368; RV32: # %bb.0:1369; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma1370; RV32-NEXT: vsra.vx v8, v8, a01371; RV32-NEXT: ret1372;1373; RV64-LABEL: vsra_vx_nxv4i64_unmasked:1374; RV64: # %bb.0:1375; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma1376; RV64-NEXT: vsra.vx v8, v8, a01377; RV64-NEXT: ret1378 %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 01379 %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer1380 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> splat (i1 true), i32 %evl)1381 ret <vscale x 4 x i64> %v1382}1383 1384define <vscale x 4 x i64> @vsra_vi_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {1385; CHECK-LABEL: vsra_vi_nxv4i64:1386; CHECK: # %bb.0:1387; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1388; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1389; CHECK-NEXT: ret1390 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 5), <vscale x 4 x i1> %m, i32 %evl)1391 ret <vscale x 4 x i64> %v1392}1393 1394define <vscale x 4 x i64> @vsra_vi_nxv4i64_unmasked(<vscale x 4 x i64> %va, i32 zeroext %evl) {1395; CHECK-LABEL: vsra_vi_nxv4i64_unmasked:1396; CHECK: # %bb.0:1397; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma1398; CHECK-NEXT: vsra.vi v8, v8, 51399; CHECK-NEXT: ret1400 %v = call <vscale x 4 x i64> @llvm.vp.ashr.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> splat (i64 5), <vscale x 4 x i1> splat (i1 true), i32 %evl)1401 ret <vscale x 4 x i64> %v1402}1403 1404define <vscale x 6 x i64> @vsra_vv_nxv6i64(<vscale x 6 x i64> %va, <vscale x 6 x i64> %b, <vscale x 6 x i1> %m, i32 zeroext %evl) {1405; CHECK-LABEL: vsra_vv_nxv6i64:1406; CHECK: # %bb.0:1407; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1408; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t1409; CHECK-NEXT: ret1410 %v = call <vscale x 6 x i64> @llvm.vp.ashr.nxv6i64(<vscale x 6 x i64> %va, <vscale x 6 x i64> %b, <vscale x 6 x i1> %m, i32 %evl)1411 ret <vscale x 6 x i64> %v1412}1413 1414define <vscale x 8 x i64> @vsra_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1415; CHECK-LABEL: vsra_vv_nxv8i64:1416; CHECK: # %bb.0:1417; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1418; CHECK-NEXT: vsra.vv v8, v8, v16, v0.t1419; CHECK-NEXT: ret1420 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl)1421 ret <vscale x 8 x i64> %v1422}1423 1424define <vscale x 8 x i64> @vsra_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) {1425; CHECK-LABEL: vsra_vv_nxv8i64_unmasked:1426; CHECK: # %bb.0:1427; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1428; CHECK-NEXT: vsra.vv v8, v8, v161429; CHECK-NEXT: ret1430 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> splat (i1 true), i32 %evl)1431 ret <vscale x 8 x i64> %v1432}1433 1434define <vscale x 8 x i64> @vsra_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {1435; RV32-LABEL: vsra_vx_nxv8i64:1436; RV32: # %bb.0:1437; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1438; RV32-NEXT: vsra.vx v8, v8, a0, v0.t1439; RV32-NEXT: ret1440;1441; RV64-LABEL: vsra_vx_nxv8i64:1442; RV64: # %bb.0:1443; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1444; RV64-NEXT: vsra.vx v8, v8, a0, v0.t1445; RV64-NEXT: ret1446 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01447 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1448 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl)1449 ret <vscale x 8 x i64> %v1450}1451 1452define <vscale x 8 x i64> @vsra_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) {1453; RV32-LABEL: vsra_vx_nxv8i64_unmasked:1454; RV32: # %bb.0:1455; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma1456; RV32-NEXT: vsra.vx v8, v8, a01457; RV32-NEXT: ret1458;1459; RV64-LABEL: vsra_vx_nxv8i64_unmasked:1460; RV64: # %bb.0:1461; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma1462; RV64-NEXT: vsra.vx v8, v8, a01463; RV64-NEXT: ret1464 %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 01465 %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer1466 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> splat (i1 true), i32 %evl)1467 ret <vscale x 8 x i64> %v1468}1469 1470define <vscale x 8 x i64> @vsra_vi_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {1471; CHECK-LABEL: vsra_vi_nxv8i64:1472; CHECK: # %bb.0:1473; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1474; CHECK-NEXT: vsra.vi v8, v8, 5, v0.t1475; CHECK-NEXT: ret1476 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 5), <vscale x 8 x i1> %m, i32 %evl)1477 ret <vscale x 8 x i64> %v1478}1479 1480define <vscale x 8 x i64> @vsra_vi_nxv8i64_unmasked(<vscale x 8 x i64> %va, i32 zeroext %evl) {1481; CHECK-LABEL: vsra_vi_nxv8i64_unmasked:1482; CHECK: # %bb.0:1483; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma1484; CHECK-NEXT: vsra.vi v8, v8, 51485; CHECK-NEXT: ret1486 %v = call <vscale x 8 x i64> @llvm.vp.ashr.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> splat (i64 5), <vscale x 8 x i1> splat (i1 true), i32 %evl)1487 ret <vscale x 8 x i64> %v1488}1489